1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef __AXP_TRAINING_STATIC_H
7 #define __AXP_TRAINING_STATIC_H
10 * STATIC_TRAINING - Set only if static parameters for training are set and
14 MV_DRAM_TRAINING_INIT ddr3_db_rev2_667[MV_MAX_DDR3_STATIC_SIZE] = {
16 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
18 {0x000016A0, 0xC002011A},
20 {0x000016A0, 0xC0420100},
22 {0x000016A0, 0xC082020A},
24 {0x000016A0, 0xC0C20017},
26 {0x000016A0, 0xC1020113},
28 {0x000016A0, 0xC1420107},
30 {0x000016A0, 0xC182011F},
32 {0x000016A0, 0xC1C2001C},
34 {0x000016A0, 0xC202010D},
38 {0x000016A0, 0xC0004A06},
40 {0x000016A0, 0xC040690D},
42 {0x000016A0, 0xC0806A0D},
44 {0x000016A0, 0xC0C0A01B},
46 {0x000016A0, 0xC1003A01},
48 {0x000016A0, 0xC1408113},
50 {0x000016A0, 0xC1805609},
52 {0x000016A0, 0xC1C04504},
54 {0x000016A0, 0xC2009518},
56 /*center DQS on read cycle */
57 {0x000016A0, 0xC803000F},
59 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
60 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
63 {0x00001480, 0x00000001},
67 MV_DRAM_TRAINING_INIT ddr3_db_rev2_800[MV_MAX_DDR3_STATIC_SIZE] = {
69 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
71 {0x000016A0, 0xC0020301},
73 {0x000016A0, 0xC0420202},
75 {0x000016A0, 0xC0820314},
77 {0x000016A0, 0xC0C20117},
79 {0x000016A0, 0xC1020219},
81 {0x000016A0, 0xC142020B},
83 {0x000016A0, 0xC182030A},
85 {0x000016A0, 0xC1C2011D},
87 {0x000016A0, 0xC2020212},
91 {0x000016A0, 0xC0007A12},
93 {0x000016A0, 0xC0408D16},
95 {0x000016A0, 0xC0809E1B},
97 {0x000016A0, 0xC0C0AC1F},
99 {0x000016A0, 0xC1005E0A},
101 {0x000016A0, 0xC140A91D},
103 {0x000016A0, 0xC1808E17},
105 {0x000016A0, 0xC1C05509},
107 {0x000016A0, 0xC2003A01},
111 {0x000016A0, 0xC0007A12},
113 {0x000016A0, 0xC0408D16},
115 {0x000016A0, 0xC0809E1B},
117 {0x000016A0, 0xC0C0AC1F},
119 {0x000016A0, 0xC1005E0A},
121 {0x000016A0, 0xC140A91D},
123 {0x000016A0, 0xC1808E17},
125 {0x000016A0, 0xC1C05509},
127 {0x000016A0, 0xC2003A01},
129 /*center DQS on read cycle */
130 {0x000016A0, 0xC803000B},
132 {0x00001538, 0x0000000D}, /*Read Data Sample Delays Register */
133 {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
136 {0x00001480, 0x00000001},
140 MV_DRAM_TRAINING_INIT ddr3_db_400[MV_MAX_DDR3_STATIC_SIZE] = {
142 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
144 {0x000016A0, 0xC002010C},
146 {0x000016A0, 0xC042001C},
148 {0x000016A0, 0xC0820115},
150 {0x000016A0, 0xC0C20019},
152 {0x000016A0, 0xC1020108},
154 {0x000016A0, 0xC1420100},
156 {0x000016A0, 0xC1820111},
158 {0x000016A0, 0xC1C2001B},
160 /*{0x000016A0, 0xC2020117}, */
161 {0x000016A0, 0xC202010C},
165 {0x000016A0, 0xC0005508},
167 {0x000016A0, 0xC0409819},
169 {0x000016A0, 0xC080650C},
171 {0x000016A0, 0xC0C0700F},
173 {0x000016A0, 0xC1004103},
175 {0x000016A0, 0xC140A81D},
177 {0x000016A0, 0xC180650C},
179 {0x000016A0, 0xC1C08013},
181 {0x000016A0, 0xC2005508},
183 /*center DQS on read cycle */
184 {0x000016A0, 0xC803000F},
186 {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
187 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
190 {0x00001480, 0x00000001},
194 MV_DRAM_TRAINING_INIT ddr3_db_533[MV_MAX_DDR3_STATIC_SIZE] = {
196 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
198 {0x000016A0, 0xC002040C},
200 {0x000016A0, 0xC0420117},
202 {0x000016A0, 0xC082041B},
204 {0x000016A0, 0xC0C20117},
206 {0x000016A0, 0xC102040A},
208 {0x000016A0, 0xC1420117},
210 {0x000016A0, 0xC1820419},
212 {0x000016A0, 0xC1C20117},
214 {0x000016A0, 0xC2020117},
218 {0x000016A0, 0xC0008113},
220 {0x000016A0, 0xC0404504},
222 {0x000016A0, 0xC0808514},
224 {0x000016A0, 0xC0C09418},
226 {0x000016A0, 0xC1006D0E},
228 {0x000016A0, 0xC1405508},
230 {0x000016A0, 0xC1807D12},
232 {0x000016A0, 0xC1C0b01F},
234 {0x000016A0, 0xC2005D0A},
236 /*center DQS on read cycle */
237 {0x000016A0, 0xC803000F},
239 {0x00001538, 0x00000008}, /*Read Data Sample Delays Register */
240 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
243 {0x00001480, 0x00000001},
247 MV_DRAM_TRAINING_INIT ddr3_db_600[MV_MAX_DDR3_STATIC_SIZE] = {
249 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
251 {0x000016A0, 0xC0020104},
253 {0x000016A0, 0xC0420010},
255 {0x000016A0, 0xC0820112},
257 {0x000016A0, 0xC0C20009},
259 {0x000016A0, 0xC102001F},
261 {0x000016A0, 0xC1420014},
263 {0x000016A0, 0xC1820109},
265 {0x000016A0, 0xC1C2000C},
267 {0x000016A0, 0xC2020112},
271 {0x000016A0, 0xC0009919},
273 {0x000016A0, 0xC0405508},
275 {0x000016A0, 0xC0809919},
277 {0x000016A0, 0xC0C09C1A},
279 {0x000016A0, 0xC1008113},
281 {0x000016A0, 0xC140650C},
283 {0x000016A0, 0xC1809518},
285 {0x000016A0, 0xC1C04103},
287 {0x000016A0, 0xC2006D0E},
289 /*center DQS on read cycle */
290 {0x000016A0, 0xC803000F},
292 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
293 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
295 {0x00001480, 0x00000001},
299 MV_DRAM_TRAINING_INIT ddr3_db_667[MV_MAX_DDR3_STATIC_SIZE] = {
302 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
304 {0x000016A0, 0xC0020103},
306 {0x000016A0, 0xC0420012},
308 {0x000016A0, 0xC0820113},
310 {0x000016A0, 0xC0C20012},
312 {0x000016A0, 0xC1020100},
314 {0x000016A0, 0xC1420016},
316 {0x000016A0, 0xC1820109},
318 {0x000016A0, 0xC1C20010},
320 {0x000016A0, 0xC2020112},
324 {0x000016A0, 0xC000b11F},
326 {0x000016A0, 0xC040690D},
328 {0x000016A0, 0xC0803600},
330 {0x000016A0, 0xC0C0a81D},
332 {0x000016A0, 0xC1009919},
334 {0x000016A0, 0xC1407911},
336 {0x000016A0, 0xC180ad1e},
338 {0x000016A0, 0xC1C04d06},
340 {0x000016A0, 0xC2008514},
342 /*center DQS on read cycle */
343 {0x000016A0, 0xC803000F},
345 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
346 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
349 {0x00001480, 0x00000001},
353 MV_DRAM_TRAINING_INIT ddr3_db_800[MV_MAX_DDR3_STATIC_SIZE] = {
356 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
358 {0x000016A0, 0xC0020213},
360 {0x000016A0, 0xC0420108},
362 {0x000016A0, 0xC0820210},
364 {0x000016A0, 0xC0C20108},
366 {0x000016A0, 0xC102011A},
368 {0x000016A0, 0xC1420300},
370 {0x000016A0, 0xC1820204},
372 {0x000016A0, 0xC1C20106},
374 {0x000016A0, 0xC2020112},
378 {0x000016A0, 0xC000620B},
380 {0x000016A0, 0xC0408D16},
382 {0x000016A0, 0xC0806A0D},
384 {0x000016A0, 0xC0C03D02},
386 {0x000016A0, 0xC1004a05},
388 {0x000016A0, 0xC140A11B},
390 {0x000016A0, 0xC1805E0A},
392 {0x000016A0, 0xC1C06D0E},
394 {0x000016A0, 0xC200AD1E},
396 /*center DQS on read cycle */
397 {0x000016A0, 0xC803000F},
399 {0x00001538, 0x0000000C}, /*Read Data Sample Delays Register */
400 {0x0000153C, 0x0000000E}, /*Read Data Ready Delay Register */
403 {0x00001480, 0x00000001},
407 MV_DRAM_TRAINING_INIT ddr3_rd_667_0[MV_MAX_DDR3_STATIC_SIZE] = {
409 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
411 {0x000016A0, 0xC002010E},
413 {0x000016A0, 0xC042001E},
415 {0x000016A0, 0xC0820118},
417 {0x000016A0, 0xC0C2001E},
419 {0x000016A0, 0xC102010C},
421 {0x000016A0, 0xC1420102},
423 {0x000016A0, 0xC1820111},
425 {0x000016A0, 0xC1C2001C},
427 {0x000016A0, 0xC2020109},
431 {0x000016A0, 0xC0003600},
433 {0x000016A0, 0xC040690D},
435 {0x000016A0, 0xC0805207},
437 {0x000016A0, 0xC0C0A81D},
439 {0x000016A0, 0xC1009919},
441 {0x000016A0, 0xC1407911},
443 {0x000016A0, 0xC1803E02},
445 {0x000016A0, 0xC1C05107},
447 {0x000016A0, 0xC2008113},
449 /*center DQS on read cycle */
450 {0x000016A0, 0xC803000F},
452 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
453 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
456 {0x00001480, 0x00000001},
460 MV_DRAM_TRAINING_INIT ddr3_rd_667_1[MV_MAX_DDR3_STATIC_SIZE] = {
462 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
464 {0x000016A0, 0xC0020106},
466 {0x000016A0, 0xC0420016},
468 {0x000016A0, 0xC0820117},
470 {0x000016A0, 0xC0C2000F},
472 {0x000016A0, 0xC1020105},
474 {0x000016A0, 0xC142001B},
476 {0x000016A0, 0xC182010C},
478 {0x000016A0, 0xC1C20011},
480 {0x000016A0, 0xC2020101},
484 {0x000016A0, 0xC0003600},
486 {0x000016A0, 0xC0406D0E},
488 {0x000016A0, 0xC0803600},
490 {0x000016A0, 0xC0C04504},
492 {0x000016A0, 0xC1009919},
494 {0x000016A0, 0xC1407911},
496 {0x000016A0, 0xC1803600},
498 {0x000016A0, 0xC1C0610B},
500 {0x000016A0, 0xC2008113},
502 /*center DQS on read cycle */
503 {0x000016A0, 0xC803000F},
505 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
506 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
509 {0x00001480, 0x00000001},
513 MV_DRAM_TRAINING_INIT ddr3_rd_667_2[MV_MAX_DDR3_STATIC_SIZE] = {
515 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
517 {0x000016A0, 0xC002010C},
519 {0x000016A0, 0xC042001B},
521 {0x000016A0, 0xC082011D},
523 {0x000016A0, 0xC0C20015},
525 {0x000016A0, 0xC102010B},
527 {0x000016A0, 0xC1420101},
529 {0x000016A0, 0xC1820113},
531 {0x000016A0, 0xC1C20017},
533 {0x000016A0, 0xC2020107},
537 {0x000016A0, 0xC0003600},
539 {0x000016A0, 0xC0406D0E},
541 {0x000016A0, 0xC0803600},
543 {0x000016A0, 0xC0C04504},
545 {0x000016A0, 0xC1009919},
547 {0x000016A0, 0xC1407911},
549 {0x000016A0, 0xC180B11F},
551 {0x000016A0, 0xC1C0610B},
553 {0x000016A0, 0xC2008113},
555 /*center DQS on read cycle */
556 {0x000016A0, 0xC803000F},
558 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
559 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
562 {0x00001480, 0x00000001},
566 MV_DRAM_TRAINING_INIT ddr3_db_667_M[MV_MAX_DDR3_STATIC_SIZE] = {
568 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
571 {0x000016A0, 0xC0020103},
573 {0x000016A0, 0xC0420012},
575 {0x000016A0, 0xC0820113},
577 {0x000016A0, 0xC0C20012},
579 {0x000016A0, 0xC1020100},
581 {0x000016A0, 0xC1420016},
583 {0x000016A0, 0xC1820109},
585 {0x000016A0, 0xC1C20010},
587 {0x000016A0, 0xC2020112},
591 {0x000016A0, 0xC000b11F},
593 {0x000016A0, 0xC040690D},
595 {0x000016A0, 0xC0803600},
597 {0x000016A0, 0xC0C0a81D},
599 {0x000016A0, 0xC1009919},
601 {0x000016A0, 0xC1407911},
603 {0x000016A0, 0xC180ad1e},
605 {0x000016A0, 0xC1C04d06},
607 {0x000016A0, 0xC2008514},
609 /*center DQS on read cycle */
610 {0x000016A0, 0xC803000F},
614 {0x000016A0, 0xC0060103},
616 {0x000016A0, 0xC0460012},
618 {0x000016A0, 0xC0860113},
620 {0x000016A0, 0xC0C60012},
622 {0x000016A0, 0xC1060100},
624 {0x000016A0, 0xC1460016},
626 {0x000016A0, 0xC1860109},
628 {0x000016A0, 0xC1C60010},
630 {0x000016A0, 0xC2060112},
634 {0x000016A0, 0xC004b11F},
636 {0x000016A0, 0xC044690D},
638 {0x000016A0, 0xC0843600},
640 {0x000016A0, 0xC0C4a81D},
642 {0x000016A0, 0xC1049919},
644 {0x000016A0, 0xC1447911},
646 {0x000016A0, 0xC184ad1e},
648 {0x000016A0, 0xC1C44d06},
650 {0x000016A0, 0xC2048514},
652 /*center DQS on read cycle */
653 {0x000016A0, 0xC807000F},
657 {0x00001538, 0x00000B0B}, /*Read Data Sample Delays Register */
658 {0x0000153C, 0x00000F0F}, /*Read Data Ready Delay Register */
661 {0x00001480, 0x00000001},
665 MV_DRAM_TRAINING_INIT ddr3_rd_667_3[MV_MAX_DDR3_STATIC_SIZE] = {
667 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
669 {0x000016A0, 0xC0020118},
671 {0x000016A0, 0xC0420108},
673 {0x000016A0, 0xC0820202},
675 {0x000016A0, 0xC0C20108},
677 {0x000016A0, 0xC1020117},
679 {0x000016A0, 0xC142010C},
681 {0x000016A0, 0xC182011B},
683 {0x000016A0, 0xC1C20107},
685 {0x000016A0, 0xC2020113},
689 {0x000016A0, 0xC0003600},
691 {0x000016A0, 0xC0406D0E},
693 {0x000016A0, 0xC0805207},
695 {0x000016A0, 0xC0C0A81D},
697 {0x000016A0, 0xC1009919},
699 {0x000016A0, 0xC1407911},
701 {0x000016A0, 0xC1803E02},
703 {0x000016A0, 0xC1C04D06},
705 {0x000016A0, 0xC2008113},
707 /*center DQS on read cycle */
708 {0x000016A0, 0xC803000F},
710 {0x00001538, 0x0000000B}, /*Read Data Sample Delays Register */
711 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
714 {0x00001480, 0x00000001},
718 MV_DRAM_TRAINING_INIT ddr3_pcac_600[MV_MAX_DDR3_STATIC_SIZE] = {
720 /*PUP RdSampleDly (+CL) Phase RL ADLL value */
722 {0x000016A0, 0xC0020404},
724 {0x000016A0, 0xC042031E},
726 {0x000016A0, 0xC0820411},
728 {0x000016A0, 0xC0C20400},
730 {0x000016A0, 0xC1020404},
732 {0x000016A0, 0xC142031D},
734 {0x000016A0, 0xC182040C},
736 {0x000016A0, 0xC1C2031B},
738 {0x000016A0, 0xC2020112},
742 {0x000016A0, 0xC0004905},
744 {0x000016A0, 0xC040A81D},
746 {0x000016A0, 0xC0804504},
748 {0x000016A0, 0xC0C08013},
750 {0x000016A0, 0xC1004504},
752 {0x000016A0, 0xC140A81D},
754 {0x000016A0, 0xC1805909},
756 {0x000016A0, 0xC1C09418},
758 {0x000016A0, 0xC2006D0E},
760 /*center DQS on read cycle */
761 {0x000016A0, 0xC803000F},
762 {0x00001538, 0x00000009}, /*Read Data Sample Delays Register */
763 {0x0000153C, 0x0000000D}, /*Read Data Ready Delay Register */
765 {0x00001480, 0x00000001},
769 #endif /* __AXP_TRAINING_STATIC_H */