1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR_TOPOLOGY_DEF_H
7 #define _DDR_TOPOLOGY_DEF_H
9 #include "ddr3_training_ip_def.h"
10 #include "ddr3_topology_def.h"
12 #if defined(CONFIG_ARMADA_38X)
13 #include "ddr3_a38x.h"
16 /* bus width in bits */
24 enum hws_temperature {
46 /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
50 * mirror enable/disable
51 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
53 int mirror_enable_bitmask;
55 /* DQS Swap (polarity) - true if enable */
58 /* CK swap (polarity) - true if enable */
63 /* bus configuration */
64 struct bus_params as_bus_params[MAX_BUS_NUM];
67 enum hws_speed_bin speed_bin_index;
69 /* bus width of memory */
70 enum hws_bus_width bus_width;
72 /* Bus memory size (MBit) */
73 enum hws_mem_size memory_size;
75 /* The DDR frequency for each interfaces */
76 enum hws_ddr_freq memory_freq;
79 * delay CAS Write Latency
80 * - 0 for using default value (jedec suggested)
86 * - 0 for using default value (jedec suggested)
90 /* operation temperature */
91 enum hws_temperature interface_temp;
93 /* 2T vs 1T mode (by default computed from number of CSs) */
94 enum hws_timing timing;
97 struct hws_topology_map {
98 /* Number of interfaces (default is 12) */
101 /* Controller configuration per interface */
102 struct if_params interface_params[MAX_INTERFACE_NUM];
104 /* BUS per interface (default is 4) */
105 u8 num_of_bus_per_interface;
107 /* Bit mask for active buses */
111 /* DDR3 training global configuration parameters */
112 struct tune_train_params {
120 #endif /* _DDR_TOPOLOGY_DEF_H */