1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR_TOPOLOGY_DEF_H
7 #define _DDR_TOPOLOGY_DEF_H
9 #include "ddr3_training_ip_def.h"
10 #include "ddr3_topology_def.h"
12 #if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)
13 #include "mv_ddr_plat.h"
16 #include "mv_ddr_topology.h"
17 #include "mv_ddr_spd.h"
18 #include "ddr3_logging_def.h"
21 /* Chip Select (CS) bitmask (bits 0-CS0, bit 1- CS1 ...) */
25 * mirror enable/disable
26 * (bits 0-CS0 mirroring, bit 1- CS1 mirroring ...)
28 int mirror_enable_bitmask;
30 /* DQS Swap (polarity) - true if enable */
33 /* CK swap (polarity) - true if enable */
38 /* bus configuration */
39 struct bus_params as_bus_params[MAX_BUS_NUM];
42 enum hws_speed_bin speed_bin_index;
44 /* sdram device width */
45 enum mv_ddr_dev_width bus_width;
47 /* total sdram capacity per die, megabits */
48 enum mv_ddr_die_capacity memory_size;
50 /* The DDR frequency for each interfaces */
51 enum hws_ddr_freq memory_freq;
54 * delay CAS Write Latency
55 * - 0 for using default value (jedec suggested)
61 * - 0 for using default value (jedec suggested)
65 /* operation temperature */
66 enum mv_ddr_temperature interface_temp;
68 /* 2T vs 1T mode (by default computed from number of CSs) */
69 enum mv_ddr_timing timing;
72 struct mv_ddr_topology_map {
73 /* debug level configuration */
74 enum mv_ddr_debug_level debug_level;
76 /* Number of interfaces (default is 12) */
79 /* Controller configuration per interface */
80 struct if_params interface_params[MAX_INTERFACE_NUM];
82 /* Bit mask for active buses */
85 /* source of ddr configuration data */
86 enum mv_ddr_cfg_src cfg_src;
89 union mv_ddr_spd_data spd_data;
91 /* timing parameters */
92 unsigned int timing_data[MV_DDR_TDATA_LAST];
95 /* DDR3 training global configuration parameters */
96 struct tune_train_params {
114 #endif /* _DDR_TOPOLOGY_DEF_H */