1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR3_TRAINING_IP_FLOW_H_
7 #define _DDR3_TRAINING_IP_FLOW_H_
9 #include "ddr3_training_ip.h"
10 #include "ddr3_training_ip_db.h"
12 #define KILLER_PATTERN_LENGTH 32
13 #define EXT_ACCESS_BURST_LENGTH 8
15 #define ECC_READ_BUS_0 0
16 #define ECC_PHY_ACCESS_3 3
17 #define ECC_PHY_ACCESS_4 4
18 #define ECC_PHY_ACCESS_8 8
19 #define BUS_WIDTH_IN_BITS 8
20 #define MAX_POLLING_ITERATIONS 1000000
21 #define ADLL_LENGTH 32
23 #define GP_RSVD0_REG 0x182e0
27 * Table 2: DFX address space
28 * Address Bits Value Description
29 * [31 : 20] 0x? DFX base address bases PCIe mapping
30 * [19 : 15] 0...Number_of_client-1 Client Index inside pipe.
31 * See also Table 1 Multi_cast = 29 Broadcast = 28
32 * [14 : 13] 2'b01 Access to Client Internal Register
33 * [12 : 0] Client Internal Register offset See related Client Registers
34 * [14 : 13] 2'b00 Access to Ram Wrappers Internal Register
35 * [12 : 6] 0 Number_of_rams-1 Ram Index inside Client
36 * [5 : 0] Ram Wrapper Internal Register offset See related Ram Wrappers
41 #define AUTO_ZQC_TIMING 15384
51 struct mv_ddr_mr_data {
56 struct write_supp_result {
57 enum hws_wl_supp stage;
61 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id,
62 enum mv_ddr_freq frequency,
63 u32 *round_trip_delay_arr);
64 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id,
65 enum mv_ddr_freq frequency,
66 u32 *total_round_trip_delay_arr);
67 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access,
68 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
69 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type,
70 u32 if_id, u32 exp_value, u32 mask, u32 offset,
72 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access,
73 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
74 int ddr3_tip_bus_read_modify_write(u32 dev_num,
75 enum hws_access_type access_type,
76 u32 if_id, u32 phy_id,
77 enum hws_ddr_phy phy_type,
78 u32 reg_addr, u32 data_value, u32 reg_mask);
79 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access,
80 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
82 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access,
83 u32 if_id, enum hws_access_type e_phy_access, u32 phy_id,
84 enum hws_ddr_phy e_phy_type, u32 reg_addr,
86 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id,
87 enum mv_ddr_freq memory_freq);
88 int ddr3_tip_adjust_dqs(u32 dev_num);
89 int ddr3_tip_init_controller(u32 dev_num);
90 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
91 u32 num_of_bursts, u32 *addr);
92 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
93 u32 num_of_bursts, u32 *addr);
94 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 ui_freq);
95 int mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq);
96 int ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num);
97 int ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 ui_freq);
98 int ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num);
99 int ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove);
100 int ddr3_tip_dynamic_write_leveling_supp(u32 dev_num);
101 int ddr3_tip_static_init_controller(u32 dev_num);
102 int ddr3_tip_configure_phy(u32 dev_num);
103 int ddr3_tip_load_pattern_to_odpg(u32 dev_num, enum hws_access_type access_type,
104 u32 if_id, enum hws_pattern pattern,
106 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern e_pattern);
107 int ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type,
108 u32 if_id, enum hws_dir direction, u32 tx_phases,
109 u32 tx_burst_size, u32 rx_phases,
110 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
111 u32 addr_stress_jump, u32 single_pattern);
112 int ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask);
113 int ddr3_tip_write_cs_result(u32 dev_num, u32 offset);
114 int ddr3_tip_reset_fifo_ptr(u32 dev_num);
115 int ddr3_tip_read_pup_value(u32 dev_num, u32 pup_values[], int reg_addr, u32 mask);
116 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr, u32 mask);
117 int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[], u32 reg_addr);
118 int ddr3_tip_tune_training_params(u32 dev_num, struct tune_train_params *params);
120 #endif /* _DDR3_TRAINING_IP_FLOW_H_ */