1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR3_TRAINING_IP_H_
7 #define _DDR3_TRAINING_IP_H_
9 #include "ddr_topology_def.h"
11 #define TIP_ENG_LOCK 0x02000000
12 #define TIP_TX_DLL_RANGE_MAX 64
14 #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
15 #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
17 #define INIT_CONTROLLER_MASK_BIT 0x00000001
18 #define STATIC_LEVELING_MASK_BIT 0x00000002
19 #define SET_LOW_FREQ_MASK_BIT 0x00000004
20 #define LOAD_PATTERN_MASK_BIT 0x00000008
21 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
22 #define WRITE_LEVELING_MASK_BIT 0x00000020
23 #define LOAD_PATTERN_2_MASK_BIT 0x00000040
24 #define READ_LEVELING_MASK_BIT 0x00000080
25 #define SW_READ_LEVELING_MASK_BIT 0x00000100
26 #define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
27 #define PBS_RX_MASK_BIT 0x00000400
28 #define PBS_TX_MASK_BIT 0x00000800
29 #define SET_TARGET_FREQ_MASK_BIT 0x00001000
30 #define ADJUST_DQS_MASK_BIT 0x00002000
31 #define WRITE_LEVELING_TF_MASK_BIT 0x00004000
32 #define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
33 #define READ_LEVELING_TF_MASK_BIT 0x00010000
34 #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
35 #define DM_PBS_TX_MASK_BIT 0x00040000
36 #define RL_DQS_BURST_MASK_BIT 0x00080000
37 #define CENTRALIZATION_RX_MASK_BIT 0x00100000
38 #define CENTRALIZATION_TX_MASK_BIT 0x00200000
39 #define TX_EMPHASIS_MASK_BIT 0x00400000
40 #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
41 #define VREF_CALIBRATION_MASK_BIT 0x01000000
42 #define WRITE_LEVELING_LF_MASK_BIT 0x02000000
44 /* DDR4 Specific Training Mask bits */
52 enum hws_training_result {
57 enum auto_tune_stage {
73 WRITE_LEVELING_SUPP_TF,
80 PER_BIT_READ_LEVELING_TF,
85 enum hws_access_type {
86 ACCESS_TYPE_UNICAST = 0,
87 ACCESS_TYPE_MULTICAST = 1
95 struct init_cntr_param {
102 struct pattern_info {
105 u8 delay_between_bursts;
116 struct hws_tip_freq_config_info {
122 struct hws_cs_config_info {
132 struct hws_xsb_info {
133 struct dfx_access *dfx_table;
136 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
137 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
138 int hws_ddr3_tip_init_controller(u32 dev_num,
139 struct init_cntr_param *init_cntr_prm);
140 int hws_ddr3_tip_load_topology_map(u32 dev_num,
141 struct mv_ddr_topology_map *topology);
142 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
143 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
144 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
145 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
146 #endif /* _DDR3_TRAINING_IP_H_ */