1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _DDR3_LOGGING_CONFIG_H
7 #define _DDR3_LOGGING_CONFIG_H
10 #define DEBUG_TRAINING_BIST_ENGINE(level, s)
11 #define DEBUG_TRAINING_IP(level, s)
12 #define DEBUG_CENTRALIZATION_ENGINE(level, s)
13 #define DEBUG_TRAINING_HW_ALG(level, s)
14 #define DEBUG_TRAINING_IP_ENGINE(level, s)
15 #define DEBUG_LEVELING(level, s)
16 #define DEBUG_PBS_ENGINE(level, s)
17 #define DEBUG_TRAINING_STATIC_IP(level, s)
18 #define DEBUG_TRAINING_ACCESS(level, s)
20 #ifdef LIB_FUNCTIONAL_DEBUG_ONLY
21 #define DEBUG_TRAINING_BIST_ENGINE(level, s)
22 #define DEBUG_TRAINING_IP_ENGINE(level, s)
23 #define DEBUG_TRAINING_IP(level, s) \
24 if (level >= debug_training) \
26 #define DEBUG_CENTRALIZATION_ENGINE(level, s) \
27 if (level >= debug_centralization) \
29 #define DEBUG_TRAINING_HW_ALG(level, s) \
30 if (level >= debug_training_hw_alg) \
32 #define DEBUG_LEVELING(level, s) \
33 if (level >= debug_leveling) \
35 #define DEBUG_PBS_ENGINE(level, s) \
36 if (level >= debug_pbs) \
38 #define DEBUG_TRAINING_STATIC_IP(level, s) \
39 if (level >= debug_training_static) \
41 #define DEBUG_TRAINING_ACCESS(level, s) \
42 if (level >= debug_training_access) \
45 #define DEBUG_TRAINING_BIST_ENGINE(level, s) \
46 if (level >= debug_training_bist) \
49 #define DEBUG_TRAINING_IP_ENGINE(level, s) \
50 if (level >= debug_training_ip) \
52 #define DEBUG_TRAINING_IP(level, s) \
53 if (level >= debug_training) \
55 #define DEBUG_CENTRALIZATION_ENGINE(level, s) \
56 if (level >= debug_centralization) \
58 #define DEBUG_TRAINING_HW_ALG(level, s) \
59 if (level >= debug_training_hw_alg) \
61 #define DEBUG_LEVELING(level, s) \
62 if (level >= debug_leveling) \
64 #define DEBUG_PBS_ENGINE(level, s) \
65 if (level >= debug_pbs) \
67 #define DEBUG_TRAINING_STATIC_IP(level, s) \
68 if (level >= debug_training_static) \
70 #define DEBUG_TRAINING_ACCESS(level, s) \
71 if (level >= debug_training_access) \
78 enum mv_ddr_debug_level {
79 DEBUG_LEVEL_TRACE = 1,
81 DEBUG_LEVEL_ERROR = 3,
85 enum ddr_lib_debug_block {
87 DEBUG_BLOCK_TRAINING_MAIN,
89 DEBUG_BLOCK_CENTRALIZATION,
96 DEBUG_STAGES_REG_DUMP,
97 /* All excluding IP and REG_DUMP, should be enabled separatelly */
101 int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
102 int ddr3_tip_print_stability_log(u32 dev_num);
104 #endif /* _DDR3_LOGGING_CONFIG_H */