1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
7 #include "mv_ddr_training_db.h"
8 #include "mv_ddr_regs.h"
11 u8 debug_pbs = DEBUG_LEVEL_ERROR;
14 * API to change flags outside of the lib
16 #if defined(SILENT_LIB)
17 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
21 #else /* SILENT_LIB */
22 /* Debug flags for other Training modules */
23 u8 debug_training_static = DEBUG_LEVEL_ERROR;
24 u8 debug_training = DEBUG_LEVEL_ERROR;
25 u8 debug_leveling = DEBUG_LEVEL_ERROR;
26 u8 debug_centralization = DEBUG_LEVEL_ERROR;
27 u8 debug_training_ip = DEBUG_LEVEL_ERROR;
28 u8 debug_training_bist = DEBUG_LEVEL_ERROR;
29 u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
30 u8 debug_training_access = DEBUG_LEVEL_ERROR;
31 u8 debug_training_device = DEBUG_LEVEL_ERROR;
34 void mv_ddr_user_log_level_set(enum ddr_lib_debug_block block)
36 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
37 ddr3_hws_set_log_level(block, tm->debug_level);
40 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
43 case DEBUG_BLOCK_STATIC:
44 debug_training_static = level;
46 case DEBUG_BLOCK_TRAINING_MAIN:
47 debug_training = level;
49 case DEBUG_BLOCK_LEVELING:
50 debug_leveling = level;
52 case DEBUG_BLOCK_CENTRALIZATION:
53 debug_centralization = level;
59 debug_training_hw_alg = level;
61 case DEBUG_BLOCK_DEVICE:
62 debug_training_device = level;
64 case DEBUG_BLOCK_ACCESS:
65 debug_training_access = level;
67 case DEBUG_STAGES_REG_DUMP:
68 if (level == DEBUG_LEVEL_TRACE)
75 debug_training_static = level;
76 debug_training = level;
77 debug_leveling = level;
78 debug_centralization = level;
80 debug_training_hw_alg = level;
81 debug_training_access = level;
82 debug_training_device = level;
85 #endif /* SILENT_LIB */
87 #if defined(DDR_VIEWER_TOOL)
88 static char *convert_freq(enum mv_ddr_freq freq);
89 #if defined(EXCLUDE_SWITCH_DEBUG)
90 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
91 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
92 u32 ctrl_adll1[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
93 u32 ctrl_level_phase[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
94 #endif /* EXCLUDE_SWITCH_DEBUG */
95 #endif /* DDR_VIEWER_TOOL */
97 struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM];
98 u8 is_default_centralization = 0;
99 u8 is_tune_result = 0;
100 u8 is_validate_window_per_if = 0;
101 u8 is_validate_window_per_pup = 0;
103 u32 is_bist_reset_bit = 1;
104 u8 is_run_leveling_sweep_tests;
106 static struct hws_xsb_info xsb_info[MAX_DEVICE_NUM];
109 * Dump Dunit & Phy registers
111 int ddr3_tip_reg_dump(u32 dev_num)
113 u32 if_id, reg_addr, data_value, bus_id;
114 u32 read_data[MAX_INTERFACE_NUM];
115 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
116 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
118 printf("-- dunit registers --\n");
119 for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) {
120 printf("0x%x ", reg_addr);
121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
122 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
123 CHECK_STATUS(ddr3_tip_if_read
124 (dev_num, ACCESS_TYPE_UNICAST,
125 if_id, reg_addr, read_data,
127 printf("0x%x ", read_data[if_id]);
132 printf("-- Phy registers --\n");
133 for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) {
134 printf("0x%x ", reg_addr);
135 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
136 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
138 bus_id < octets_per_if_num;
140 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
141 CHECK_STATUS(ddr3_tip_bus_read
143 ACCESS_TYPE_UNICAST, bus_id,
144 DDR_PHY_DATA, reg_addr,
146 printf("0x%x ", data_value);
149 bus_id < octets_per_if_num;
151 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
152 CHECK_STATUS(ddr3_tip_bus_read
154 ACCESS_TYPE_UNICAST, bus_id,
155 DDR_PHY_CONTROL, reg_addr,
157 printf("0x%x ", data_value);
167 * Register access func registration
169 int ddr3_tip_init_config_func(u32 dev_num,
170 struct hws_tip_config_func_db *config_func)
172 if (config_func == NULL)
175 memcpy(&config_func_info[dev_num], config_func,
176 sizeof(struct hws_tip_config_func_db));
182 * Get training result info pointer
184 enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
186 return training_result[stage];
192 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
194 if (config_func_info[dev_num].tip_get_device_info_func != NULL) {
195 return config_func_info[dev_num].
196 tip_get_device_info_func((u8) dev_num, info_ptr);
202 #if defined(DDR_VIEWER_TOOL)
204 * Convert freq to character string
206 static char *convert_freq(enum mv_ddr_freq freq)
209 case MV_DDR_FREQ_LOW_FREQ:
210 return "MV_DDR_FREQ_LOW_FREQ";
212 case MV_DDR_FREQ_400:
215 case MV_DDR_FREQ_533:
218 case MV_DDR_FREQ_667:
221 case MV_DDR_FREQ_800:
224 case MV_DDR_FREQ_933:
227 case MV_DDR_FREQ_1066:
230 case MV_DDR_FREQ_311:
233 case MV_DDR_FREQ_333:
236 case MV_DDR_FREQ_467:
239 case MV_DDR_FREQ_850:
242 case MV_DDR_FREQ_900:
245 case MV_DDR_FREQ_360:
246 return "MV_DDR_FREQ_360";
248 case MV_DDR_FREQ_1000:
249 return "MV_DDR_FREQ_1000";
252 return "Unknown Frequency";
257 * Convert device ID to character string
259 static char *convert_dev_id(u32 dev_id)
272 return "Unknown Device";
277 * Convert device ID to character string
279 static char *convert_mem_size(u32 dev_id)
294 return "wrong mem size";
298 int print_device_info(u8 dev_num)
300 struct ddr3_device_info info_ptr;
301 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
303 CHECK_STATUS(ddr3_tip_get_device_info(dev_num, &info_ptr));
304 printf("=== DDR setup START===\n");
305 printf("\tDevice ID: %s\n", convert_dev_id(info_ptr.device_id));
306 printf("\tDDR3 CK delay: %d\n", info_ptr.ck_delay);
308 printf("=== DDR setup END===\n");
313 void hws_ddr3_tip_sweep_test(int enable)
316 is_validate_window_per_if = 1;
317 is_validate_window_per_pup = 1;
318 debug_training = DEBUG_LEVEL_TRACE;
320 is_validate_window_per_if = 0;
321 is_validate_window_per_pup = 0;
324 #endif /* DDR_VIEWER_TOOL */
326 char *ddr3_tip_convert_tune_result(enum hws_result tune_result)
328 switch (tune_result) {
334 return "NOT COMPLETED";
343 int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
346 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
348 #if defined(DDR_VIEWER_TOOL)
349 if ((is_validate_window_per_if != 0) ||
350 (is_validate_window_per_pup != 0)) {
352 enum mv_ddr_freq freq;
354 freq = tm->interface_params[first_active_if].memory_freq;
356 is_pup_log = (is_validate_window_per_pup != 0) ? 1 : 0;
357 printf("===VALIDATE WINDOW LOG START===\n");
358 printf("DDR Frequency: %s ======\n", convert_freq(freq));
359 /* print sweep windows */
360 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
361 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
362 #if defined(EXCLUDE_SWITCH_DEBUG)
363 if (is_run_leveling_sweep_tests == 1) {
364 ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
365 ddr3_tip_run_leveling_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
367 #endif /* EXCLUDE_SWITCH_DEBUG */
368 ddr3_tip_print_all_pbs_result(dev_num);
369 ddr3_tip_print_wl_supp_result(dev_num);
370 printf("===VALIDATE WINDOW LOG END ===\n");
371 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
372 ddr3_tip_reg_dump(dev_num);
374 #endif /* DDR_VIEWER_TOOL */
376 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
377 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
379 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
380 ("IF %d Status:\n", if_id));
382 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
383 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
384 ("\tInit Controller: %s\n",
385 ddr3_tip_convert_tune_result
386 (training_result[INIT_CONTROLLER]
389 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
390 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
391 ("\tLow freq Config: %s\n",
392 ddr3_tip_convert_tune_result
393 (training_result[SET_LOW_FREQ]
396 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
397 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
398 ("\tLoad Pattern: %s\n",
399 ddr3_tip_convert_tune_result
400 (training_result[LOAD_PATTERN]
403 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
404 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
405 ("\tMedium freq Config: %s\n",
406 ddr3_tip_convert_tune_result
407 (training_result[SET_MEDIUM_FREQ]
410 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
411 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
413 ddr3_tip_convert_tune_result
414 (training_result[WRITE_LEVELING]
417 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
418 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
419 ("\tLoad Pattern: %s\n",
420 ddr3_tip_convert_tune_result
421 (training_result[LOAD_PATTERN_2]
424 if (mask_tune_func & READ_LEVELING_MASK_BIT) {
425 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
427 ddr3_tip_convert_tune_result
428 (training_result[READ_LEVELING]
431 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
432 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
434 ddr3_tip_convert_tune_result
435 (training_result[WRITE_LEVELING_SUPP]
438 if (mask_tune_func & PBS_RX_MASK_BIT) {
439 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
441 ddr3_tip_convert_tune_result
442 (training_result[PBS_RX]
445 if (mask_tune_func & PBS_TX_MASK_BIT) {
446 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
448 ddr3_tip_convert_tune_result
449 (training_result[PBS_TX]
452 if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
453 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
454 ("\tTarget freq Config: %s\n",
455 ddr3_tip_convert_tune_result
456 (training_result[SET_TARGET_FREQ]
459 if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
460 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
462 ddr3_tip_convert_tune_result
463 (training_result[WRITE_LEVELING_TF]
466 if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
467 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
469 ddr3_tip_convert_tune_result
470 (training_result[READ_LEVELING_TF]
473 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
474 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
475 ("\tWL TF Supp: %s\n",
476 ddr3_tip_convert_tune_result
478 [WRITE_LEVELING_SUPP_TF]
481 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
482 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
484 ddr3_tip_convert_tune_result
485 (training_result[CENTRALIZATION_RX]
488 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
489 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
490 ("\tVREF_CALIBRATION: %s\n",
491 ddr3_tip_convert_tune_result
492 (training_result[VREF_CALIBRATION]
495 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
496 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
498 ddr3_tip_convert_tune_result
499 (training_result[CENTRALIZATION_TX]
507 #if !defined(EXCLUDE_DEBUG_PRINTS)
509 * Print stability log info
511 int ddr3_tip_print_stability_log(u32 dev_num)
513 u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
515 u32 read_data[MAX_INTERFACE_NUM];
516 unsigned int max_cs = mv_ddr_cs_num_get();
517 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
520 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
521 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
522 printf("Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,");
523 for (csindex = 0; csindex < max_cs; csindex++) {
524 printf("CS%d , ", csindex);
526 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
527 printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
529 for (idx = 0; idx < 11; idx++)
530 printf("PBSTx-Pad%d,", idx);
532 for (idx = 0; idx < 11; idx++)
533 printf("PBSRx-Pad%d,", idx);
539 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
540 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
542 printf("Data: %d,%d,", if_id,
543 (config_func_info[dev_num].tip_get_temperature != NULL)
544 ? (config_func_info[dev_num].
545 tip_get_temperature(dev_num)) : (0));
547 CHECK_STATUS(ddr3_tip_if_read
548 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x14c8,
549 read_data, MASK_ALL_BITS));
550 printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
551 ((read_data[if_id] & 0xfc00) >> 10));
552 CHECK_STATUS(ddr3_tip_if_read
553 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x17c8,
554 read_data, MASK_ALL_BITS));
555 printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
556 ((read_data[if_id] & 0xfc00) >> 10));
557 CHECK_STATUS(ddr3_tip_if_read
558 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1dc8,
559 read_data, MASK_ALL_BITS));
560 printf("%d,%d,", ((read_data[if_id] & 0x3f0000) >> 16),
561 ((read_data[if_id] & 0xfc00000) >> 22));
563 for (csindex = 0; csindex < max_cs; csindex++) {
564 printf("CS%d , ", csindex);
565 for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) {
567 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
568 ddr3_tip_bus_read(dev_num, if_id,
570 bus_id, DDR_PHY_DATA,
573 printf("%d,%d,", (reg_data & 0x1f),
574 ((reg_data & 0x3e0) >> 5));
576 ddr3_tip_bus_read(dev_num, if_id,
578 bus_id, DDR_PHY_DATA,
583 ((reg_data & 0x1c0) >> 6) * 32,
585 (reg_data & 0x1c0) >> 6);
587 CHECK_STATUS(ddr3_tip_if_read
588 (dev_num, ACCESS_TYPE_UNICAST,
590 RD_DATA_SMPL_DLYS_REG,
591 read_data, MASK_ALL_BITS));
594 (0x1f << (8 * csindex))) >>
596 ddr3_tip_bus_read(dev_num, if_id,
597 ACCESS_TYPE_UNICAST, bus_id,
601 printf("%d,%d,%d,%d,",
603 ((reg_data & 0x1c0) >> 6) * 32 +
604 read_data[if_id] * 64,
606 ((reg_data & 0x1c0) >> 6),
609 ddr3_tip_bus_read(dev_num, if_id,
610 ACCESS_TYPE_UNICAST, bus_id,
612 CTX_PHY_REG(csindex),
614 printf("%d,", (reg_data & 0x3f));
615 ddr3_tip_bus_read(dev_num, if_id,
616 ACCESS_TYPE_UNICAST, bus_id,
618 CRX_PHY_REG(csindex),
620 printf("%d,", (reg_data & 0x1f));
622 ddr3_tip_bus_read(dev_num, if_id,
623 ACCESS_TYPE_UNICAST, bus_id,
627 printf("%d,", (reg_data & 0x7));
629 /* Need to add the Read Function from device */
632 for (idx = 0; idx < 11; idx++) {
633 ddr3_tip_bus_read(dev_num, if_id,
635 bus_id, DDR_PHY_DATA,
639 printf("%d,", (reg_data & 0x3f));
642 for (idx = 0; idx < 11; idx++) {
643 ddr3_tip_bus_read(dev_num, if_id,
645 bus_id, DDR_PHY_DATA,
649 printf("%d,", (reg_data & 0x3f));
658 #endif /* EXCLUDE_DEBUG_PRINTS */
661 * Register XSB information
663 int ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table)
665 memcpy(&xsb_info[dev_num], xsb_info_table, sizeof(struct hws_xsb_info));
672 int ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
673 u32 reg_addr, u32 mask)
676 u32 if_id = 0, bus_id = 0;
677 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
678 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
681 * multi CS support - reg_addr is calucalated in calling function
684 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
685 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
686 for (bus_id = 0; bus_id < octets_per_if_num;
688 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
689 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
692 DDR_PHY_DATA, reg_addr,
695 octets_per_if_num + bus_id] =
706 int ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
709 u32 if_id = 0, bus_id = 0;
711 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
712 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
715 * multi CS support - reg_addr is calucalated in calling function
718 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
719 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
720 for (bus_id = 0; bus_id < octets_per_if_num;
722 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
723 data = pup_values[if_id *
726 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
730 bus_id, DDR_PHY_DATA,
741 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
742 int reg_addr, u32 mask)
745 u32 if_id = 0, bus_id = 0;
746 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
747 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
749 /* multi CS support - reg_addr is calucalated in calling function with CS offset */
750 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
751 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
752 for (bus_id = 0; bus_id < octets_per_if_num; bus_id++) {
753 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
754 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
757 DDR_PHY_DATA, reg_addr,
759 pup_values[if_id * octets_per_if_num + bus_id] = data_value & mask;
767 * Write Leveling Value
769 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
770 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr)
772 u32 if_id = 0, bus_id = 0;
774 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
775 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
777 /* multi CS support - reg_addr is calucalated in calling function with CS offset */
778 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
779 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
780 for (bus_id = 0 ; bus_id < octets_per_if_num ; bus_id++) {
781 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_id);
782 data = pup_values[if_id * octets_per_if_num + bus_id] +
783 pup_ph_values[if_id * octets_per_if_num + bus_id];
784 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
798 #if !defined(EXCLUDE_SWITCH_DEBUG)
799 struct hws_tip_config_func_db config_func_info[MAX_DEVICE_NUM];
800 u32 start_xsb_offset = 0;
803 u8 is_dfs_disabled = 0;
804 u32 default_centrlization_value = 0x12;
805 u32 activate_select_before_run_alg = 1, activate_deselect_after_run_alg = 1,
806 rl_test = 0, reset_read_fifo = 0;
808 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
809 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
811 u32 xsb_test_table[][8] = {
812 {0x00000000, 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555,
813 0x66666666, 0x77777777},
814 {0x88888888, 0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd,
815 0xeeeeeeee, 0xffffffff},
816 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
817 0x00000000, 0xffffffff},
818 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
819 0x00000000, 0xffffffff},
820 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
821 0x00000000, 0xffffffff},
822 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
823 0x00000000, 0xffffffff},
824 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
825 0xffffffff, 0xffffffff},
826 {0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
827 0x00000000, 0x00000000},
828 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
829 0xffffffff, 0xffffffff}
832 int ddr3_tip_print_adll(void)
834 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0;
835 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
836 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
838 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
839 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
840 for (bus_cnt = 0; bus_cnt < octets_per_if_num;
842 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
843 CHECK_STATUS(ddr3_tip_bus_read
845 ACCESS_TYPE_UNICAST, bus_cnt,
846 DDR_PHY_DATA, 0x1, &data_p1));
847 CHECK_STATUS(ddr3_tip_bus_read
848 (dev_num, if_id, ACCESS_TYPE_UNICAST,
849 bus_cnt, DDR_PHY_DATA, 0x2, &data_p2));
850 CHECK_STATUS(ddr3_tip_bus_read
851 (dev_num, if_id, ACCESS_TYPE_UNICAST,
852 bus_cnt, DDR_PHY_DATA, 0x3, &ui_data3));
853 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
854 (" IF %d bus_cnt %d phy_reg_1_data 0x%x phy_reg_2_data 0x%x phy_reg_3_data 0x%x\n",
855 if_id, bus_cnt, data_p1, data_p2,
863 #endif /* EXCLUDE_SWITCH_DEBUG */
865 #if defined(DDR_VIEWER_TOOL)
869 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
872 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
873 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
875 for (j = 0; j < octets_per_if_num; j++) {
876 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, j);
877 for (i = 0; i < MAX_INTERFACE_NUM; i++)
878 printf("%d ,", adll[i * octets_per_if_num + j]);
885 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
888 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
889 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
891 for (j = 0; j < octets_per_if_num; j++) {
892 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, j);
893 for (i = 0; i < MAX_INTERFACE_NUM; i++)
894 printf("%d ,", adll[i * octets_per_if_num + j] >> 6);
900 #endif /* DDR_VIEWER_TOOL */
902 #if !defined(EXCLUDE_SWITCH_DEBUG)
903 /* byte_index - only byte 0, 1, 2, or 3, oxff - test all bytes */
904 static u32 ddr3_tip_compare(u32 if_id, u32 *p_src, u32 *p_dst,
907 u32 burst_cnt = 0, addr_offset, i_id;
912 0xff) ? (u32) 0xffffffff : (u32) (0xff << (byte_index * 8));
913 for (burst_cnt = 0; burst_cnt < EXT_ACCESS_BURST_LENGTH; burst_cnt++) {
914 if ((p_src[burst_cnt] & addr_offset) !=
915 (p_dst[if_id] & addr_offset))
919 if (b_is_fail == 1) {
920 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
921 ("IF %d exp: ", if_id));
922 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
923 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
924 ("0x%8x ", p_src[i_id]));
926 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
927 ("\n_i_f %d rcv: ", if_id));
928 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
929 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
930 ("(0x%8x ", p_dst[i_id]));
932 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("\n "));
937 #endif /* EXCLUDE_SWITCH_DEBUG */
939 #if defined(DDR_VIEWER_TOOL)
943 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
946 u32 pup = 0, start_pup = 0, end_pup = 0;
947 u32 adll = 0, rep = 0, pattern_idx = 0;
948 u32 res[MAX_INTERFACE_NUM] = { 0 };
952 enum hws_access_type pup_access;
954 unsigned int max_cs = mv_ddr_cs_num_get();
955 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
956 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
963 end_pup = octets_per_if_num - 1;
964 pup_access = ACCESS_TYPE_UNICAST;
968 pup_access = ACCESS_TYPE_MULTICAST;
971 for (cs = 0; cs < max_cs; cs++) {
972 reg = (direction == 0) ? CTX_PHY_REG(cs) : CRX_PHY_REG(cs);
973 for (adll = 0; adll < ADLL_LENGTH; adll++) {
975 if_id <= MAX_INTERFACE_NUM - 1;
980 for (pup = start_pup; pup <= end_pup; pup++) {
981 ctrl_sweepres[adll][if_id][pup] =
987 for (adll = 0; adll < (MAX_INTERFACE_NUM * MAX_BUS_NUM); adll++)
989 /* Save DQS value(after algorithm run) */
990 ddr3_tip_read_adll_value(dev_num, ctrl_adll,
994 * Sweep ADLL from 0:31 on all I/F on all Pup and perform
995 * BIST on each stage.
997 for (pup = start_pup; pup <= end_pup; pup++) {
998 for (adll = 0; adll < ADLL_LENGTH; adll++) {
999 for (rep = 0; rep < repeat_num; rep++) {
1000 for (pattern_idx = PATTERN_KILLER_DQ0;
1001 pattern_idx < PATTERN_LAST;
1004 (direction == 0) ? (adll * 2) : adll;
1005 CHECK_STATUS(ddr3_tip_bus_write
1006 (dev_num, ACCESS_TYPE_MULTICAST, 0,
1007 pup_access, pup, DDR_PHY_DATA,
1009 hws_ddr3_run_bist(dev_num, sweep_pattern, res,
1011 /* ddr3_tip_reset_fifo_ptr(dev_num); */
1013 if_id < MAX_INTERFACE_NUM;
1018 ctrl_sweepres[adll][if_id][pup]
1024 ACCESS_TYPE_UNICAST,
1026 ACCESS_TYPE_UNICAST,
1040 printf("Final, CS %d,%s, Sweep, Result, Adll,", cs,
1041 ((direction == 0) ? "TX" : "RX"));
1042 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1043 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1045 for (pup = start_pup; pup <= end_pup; pup++) {
1046 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
1047 printf("I/F%d-PHY%d , ", if_id, pup);
1050 printf("I/F%d , ", if_id);
1055 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1056 adll_value = (direction == 0) ? (adll * 2) : adll;
1057 printf("Final,%s, Sweep, Result, %d ,",
1058 ((direction == 0) ? "TX" : "RX"), adll_value);
1061 if_id <= MAX_INTERFACE_NUM - 1;
1063 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1064 for (pup = start_pup; pup <= end_pup; pup++) {
1066 ctrl_sweepres[adll][if_id]
1074 * Write back to the phy the Rx DQS value, we store in
1077 ddr3_tip_write_adll_value(dev_num, ctrl_adll, reg);
1078 /* print adll results */
1079 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS);
1080 printf("%s, DQS, ADLL,,,", (direction == 0) ? "Tx" : "Rx");
1081 print_adll(dev_num, ctrl_adll);
1083 ddr3_tip_reset_fifo_ptr(dev_num);
1088 #if defined(EXCLUDE_SWITCH_DEBUG)
1089 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num,
1090 u32 direction, u32 mode)
1092 u32 pup = 0, start_pup = 0, end_pup = 0, start_adll = 0;
1093 u32 adll = 0, rep = 0, pattern_idx = 0;
1094 u32 read_data[MAX_INTERFACE_NUM];
1095 u32 res[MAX_INTERFACE_NUM] = { 0 };
1096 int if_id = 0, gap = 0;
1099 enum hws_access_type pup_access;
1101 unsigned int max_cs = mv_ddr_cs_num_get();
1102 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE);
1103 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1105 if (mode == 1) { /* per pup */
1107 end_pup = octets_per_if_num - 1;
1108 pup_access = ACCESS_TYPE_UNICAST;
1112 pup_access = ACCESS_TYPE_MULTICAST;
1115 for (cs = 0; cs < max_cs; cs++) {
1116 reg = (direction == 0) ? WL_PHY_REG(cs) : RL_PHY_REG(cs);
1117 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1118 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
1119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1120 for (pup = start_pup; pup <= end_pup; pup++)
1121 ctrl_sweepres[adll][if_id][pup] = 0;
1125 for (adll = 0; adll < MAX_INTERFACE_NUM * MAX_BUS_NUM; adll++) {
1126 ctrl_adll[adll] = 0;
1127 ctrl_level_phase[adll] = 0;
1128 ctrl_adll1[adll] = 0;
1131 /* save leveling value after running algorithm */
1132 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, 0x1f);
1133 read_phase_value(dev_num, ctrl_level_phase, reg, 0x7 << 6);
1136 ddr3_tip_read_adll_value(dev_num, ctrl_adll1,
1137 CTX_PHY_REG(cs), MASK_ALL_BITS);
1139 /* Sweep ADLL from 0 to 31 on all interfaces, all pups,
1140 * and perform BIST on each stage
1142 for (pup = start_pup; pup <= end_pup; pup++) {
1143 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1144 for (rep = 0; rep < repeat_num; rep++) {
1145 adll_value = (direction == 0) ? (adll * 2) : (adll * 3);
1146 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1147 start_adll = ctrl_adll[if_id * cs * octets_per_if_num + pup] +
1148 (ctrl_level_phase[if_id * cs *
1153 start_adll = (start_adll > 32) ? (start_adll - 32) : 0;
1155 start_adll = (start_adll > 48) ? (start_adll - 48) : 0;
1157 adll_value += start_adll;
1159 gap = ctrl_adll1[if_id * cs * octets_per_if_num + pup] -
1160 ctrl_adll[if_id * cs * octets_per_if_num + pup];
1161 gap = (((adll_value % 32) + gap) % 64);
1163 adll_value = ((adll_value % 32) +
1164 (((adll_value - (adll_value % 32)) / 32) << 6));
1166 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1167 ACCESS_TYPE_UNICAST,
1175 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1176 ACCESS_TYPE_UNICAST,
1185 for (pattern_idx = PATTERN_KILLER_DQ0;
1186 pattern_idx < PATTERN_LAST;
1188 hws_ddr3_run_bist(dev_num, sweep_pattern, res, cs);
1189 ddr3_tip_reset_fifo_ptr(dev_num);
1190 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1191 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1192 if (pup != 4) { /* TODO: remove literal */
1193 ctrl_sweepres[adll][if_id][pup] += res[if_id];
1195 CHECK_STATUS(ddr3_tip_if_read(dev_num,
1196 ACCESS_TYPE_UNICAST,
1201 ctrl_sweepres[adll][if_id][pup] += read_data[if_id];
1202 CHECK_STATUS(ddr3_tip_if_write(dev_num,
1203 ACCESS_TYPE_UNICAST,
1208 CHECK_STATUS(ddr3_tip_if_write(dev_num,
1209 ACCESS_TYPE_UNICAST,
1220 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1221 start_adll = ctrl_adll[if_id * cs * octets_per_if_num + pup] +
1222 ctrl_level_phase[if_id * cs * octets_per_if_num + pup];
1223 CHECK_STATUS(ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST, if_id, pup_access, pup,
1224 DDR_PHY_DATA, reg, start_adll));
1226 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
1227 ACCESS_TYPE_UNICAST,
1240 printf("Final,CS %d,%s,Leveling,Result,Adll,", cs, ((direction == 0) ? "TX" : "RX"));
1242 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1243 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1245 for (pup = start_pup; pup <= end_pup; pup++) {
1246 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup);
1247 printf("I/F%d-PHY%d , ", if_id, pup);
1250 printf("I/F%d , ", if_id);
1255 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1256 adll_value = (direction == 0) ? ((adll * 2) - 32) : ((adll * 3) - 48);
1257 printf("Final,%s,LevelingSweep,Result, %d ,", ((direction == 0) ? "TX" : "RX"), adll_value);
1259 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1260 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1261 for (pup = start_pup; pup <= end_pup; pup++)
1262 printf("%8d , ", ctrl_sweepres[adll][if_id][pup]);
1267 /* write back to the phy the Rx DQS value, we store in the beginning */
1268 write_leveling_value(dev_num, ctrl_adll, ctrl_level_phase, reg);
1270 ddr3_tip_write_adll_value(dev_num, ctrl_adll1, CTX_PHY_REG(cs));
1272 /* print adll results */
1273 ddr3_tip_read_adll_value(dev_num, ctrl_adll, reg, MASK_ALL_BITS);
1274 printf("%s,DQS,Leveling,,,", (direction == 0) ? "Tx" : "Rx");
1275 print_adll(dev_num, ctrl_adll);
1276 print_ph(dev_num, ctrl_level_phase);
1278 ddr3_tip_reset_fifo_ptr(dev_num);
1282 #endif /* EXCLUDE_SWITCH_DEBUG */
1284 void print_topology(struct mv_ddr_topology_map *topology_db)
1289 printf("\tinterface_mask: 0x%x\n", topology_db->if_act_mask);
1290 printf("\tNumber of buses: 0x%x\n",
1291 ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE));
1292 printf("\tbus_act_mask: 0x%x\n", topology_db->bus_act_mask);
1294 for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) {
1295 VALIDATE_IF_ACTIVE(topology_db->if_act_mask, ui);
1296 printf("\n\tInterface ID: %d\n", ui);
1297 printf("\t\tDDR Frequency: %s\n",
1298 convert_freq(topology_db->
1299 interface_params[ui].memory_freq));
1300 printf("\t\tSpeed_bin: %d\n",
1301 topology_db->interface_params[ui].speed_bin_index);
1302 printf("\t\tBus_width: %d\n",
1303 (4 << topology_db->interface_params[ui].bus_width));
1304 printf("\t\tMem_size: %s\n",
1305 convert_mem_size(topology_db->
1306 interface_params[ui].memory_size));
1307 printf("\t\tCAS-WL: %d\n",
1308 topology_db->interface_params[ui].cas_wl);
1309 printf("\t\tCAS-L: %d\n",
1310 topology_db->interface_params[ui].cas_l);
1311 printf("\t\tTemperature: %d\n",
1312 topology_db->interface_params[ui].interface_temp);
1314 for (uj = 0; uj < 4; uj++) {
1315 printf("\t\tBus %d parameters- CS Mask: 0x%x\t", uj,
1316 topology_db->interface_params[ui].
1317 as_bus_params[uj].cs_bitmask);
1318 printf("Mirror: 0x%x\t",
1319 topology_db->interface_params[ui].
1320 as_bus_params[uj].mirror_enable_bitmask);
1321 printf("DQS Swap is %s \t",
1323 interface_params[ui].as_bus_params[uj].
1324 is_dqs_swap == 1) ? "enabled" : "disabled");
1325 printf("Ck Swap:%s\t",
1327 interface_params[ui].as_bus_params[uj].
1328 is_ck_swap == 1) ? "enabled" : "disabled");
1333 #endif /* DDR_VIEWER_TOOL */
1335 #if !defined(EXCLUDE_SWITCH_DEBUG)
1337 * Execute XSB Test transaction (rd/wr/both)
1339 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
1340 u32 read_type, u32 burst_length)
1342 u32 seq = 0, if_id = 0, addr, cnt;
1343 int ret = MV_OK, ret_tmp;
1344 u32 data_read[MAX_INTERFACE_NUM];
1345 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
1347 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1348 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id);
1350 for (cnt = 0; cnt <= burst_length; cnt++) {
1351 seq = (seq + 1) % 8;
1352 if (write_type != 0) {
1353 CHECK_STATUS(ddr3_tip_ext_write
1354 (dev_num, if_id, addr, 1,
1355 xsb_test_table[seq]));
1357 if (read_type != 0) {
1358 CHECK_STATUS(ddr3_tip_ext_read
1359 (dev_num, if_id, addr, 1,
1362 if ((read_type != 0) && (write_type != 0)) {
1364 ddr3_tip_compare(if_id,
1365 xsb_test_table[seq],
1368 addr += (EXT_ACCESS_BURST_LENGTH * 4);
1369 ret = (ret != MV_OK) ? ret : ret_tmp;
1377 #else /*EXCLUDE_SWITCH_DEBUG */
1378 u32 start_xsb_offset = 0;
1380 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
1381 u32 read_type, u32 burst_length)
1386 #endif /* EXCLUDE_SWITCH_DEBUG */