2 * Copyright 2008, 2010-2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
14 * Use our own stack based buffer before relocation to allow accessing longer
15 * hwconfig strings that might be in the environment before we've relocated.
16 * This is pretty fragile on both the use of stack and if the buffer is big
17 * enough. However we will get a warning from getenv_f for the later.
20 /* Board-specific functions defined in each board's ddr.c */
21 extern void fsl_ddr_board_options(memctl_options_t *popts,
23 unsigned int ctrl_num);
26 unsigned int odt_rd_cfg;
27 unsigned int odt_wr_cfg;
28 unsigned int odt_rtt_norm;
29 unsigned int odt_rtt_wr;
32 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
33 static const struct dynamic_odt single_Q[4] = {
36 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
42 FSL_DDR_ODT_NEVER, /* tied high */
48 FSL_DDR_ODT_CS_AND_OTHER_DIMM,
54 FSL_DDR_ODT_NEVER, /* tied high */
60 static const struct dynamic_odt single_D[4] = {
77 static const struct dynamic_odt single_S[4] = {
89 static const struct dynamic_odt dual_DD[4] = {
92 FSL_DDR_ODT_SAME_DIMM,
97 FSL_DDR_ODT_OTHER_DIMM,
98 FSL_DDR_ODT_OTHER_DIMM,
104 FSL_DDR_ODT_SAME_DIMM,
109 FSL_DDR_ODT_OTHER_DIMM,
110 FSL_DDR_ODT_OTHER_DIMM,
116 static const struct dynamic_odt dual_DS[4] = {
119 FSL_DDR_ODT_SAME_DIMM,
124 FSL_DDR_ODT_OTHER_DIMM,
125 FSL_DDR_ODT_OTHER_DIMM,
130 FSL_DDR_ODT_OTHER_DIMM,
137 static const struct dynamic_odt dual_SD[4] = {
139 FSL_DDR_ODT_OTHER_DIMM,
147 FSL_DDR_ODT_SAME_DIMM,
152 FSL_DDR_ODT_OTHER_DIMM,
153 FSL_DDR_ODT_OTHER_DIMM,
159 static const struct dynamic_odt dual_SS[4] = {
161 FSL_DDR_ODT_OTHER_DIMM,
168 FSL_DDR_ODT_OTHER_DIMM,
176 static const struct dynamic_odt dual_D0[4] = {
179 FSL_DDR_ODT_SAME_DIMM,
193 static const struct dynamic_odt dual_0D[4] = {
198 FSL_DDR_ODT_SAME_DIMM,
210 static const struct dynamic_odt dual_S0[4] = {
223 static const struct dynamic_odt dual_0S[4] = {
236 static const struct dynamic_odt odt_unknown[4] = {
262 #else /* CONFIG_SYS_FSL_DDR3 || CONFIG_SYS_FSL_DDR4 */
263 static const struct dynamic_odt single_Q[4] = {
270 static const struct dynamic_odt single_D[4] = {
287 static const struct dynamic_odt single_S[4] = {
299 static const struct dynamic_odt dual_DD[4] = {
301 FSL_DDR_ODT_OTHER_DIMM,
302 FSL_DDR_ODT_OTHER_DIMM,
313 FSL_DDR_ODT_OTHER_DIMM,
314 FSL_DDR_ODT_OTHER_DIMM,
326 static const struct dynamic_odt dual_DS[4] = {
328 FSL_DDR_ODT_OTHER_DIMM,
329 FSL_DDR_ODT_OTHER_DIMM,
340 FSL_DDR_ODT_OTHER_DIMM,
341 FSL_DDR_ODT_OTHER_DIMM,
348 static const struct dynamic_odt dual_SD[4] = {
350 FSL_DDR_ODT_OTHER_DIMM,
351 FSL_DDR_ODT_OTHER_DIMM,
357 FSL_DDR_ODT_OTHER_DIMM,
358 FSL_DDR_ODT_OTHER_DIMM,
370 static const struct dynamic_odt dual_SS[4] = {
372 FSL_DDR_ODT_OTHER_DIMM,
373 FSL_DDR_ODT_OTHER_DIMM,
379 FSL_DDR_ODT_OTHER_DIMM,
380 FSL_DDR_ODT_OTHER_DIMM,
387 static const struct dynamic_odt dual_D0[4] = {
404 static const struct dynamic_odt dual_0D[4] = {
421 static const struct dynamic_odt dual_S0[4] = {
434 static const struct dynamic_odt dual_0S[4] = {
447 static const struct dynamic_odt odt_unknown[4] = {
476 * Automatically seleect bank interleaving mode based on DIMMs
477 * in this order: cs0_cs1_cs2_cs3, cs0_cs1, null.
478 * This function only deal with one or two slots per controller.
480 static inline unsigned int auto_bank_intlv(dimm_params_t *pdimm)
482 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
483 if (pdimm[0].n_ranks == 4)
484 return FSL_DDR_CS0_CS1_CS2_CS3;
485 else if (pdimm[0].n_ranks == 2)
486 return FSL_DDR_CS0_CS1;
487 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
488 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
489 if (pdimm[0].n_ranks == 4)
490 return FSL_DDR_CS0_CS1_CS2_CS3;
492 if (pdimm[0].n_ranks == 2) {
493 if (pdimm[1].n_ranks == 2)
494 return FSL_DDR_CS0_CS1_CS2_CS3;
496 return FSL_DDR_CS0_CS1;
502 unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
503 memctl_options_t *popts,
504 dimm_params_t *pdimm,
505 unsigned int ctrl_num)
508 char buffer[HWCONFIG_BUFFER_SIZE];
510 #if defined(CONFIG_SYS_FSL_DDR3) || \
511 defined(CONFIG_SYS_FSL_DDR2) || \
512 defined(CONFIG_SYS_FSL_DDR4)
513 const struct dynamic_odt *pdodt = odt_unknown;
518 * Extract hwconfig from environment since we have not properly setup
519 * the environment but need it for ddr config params
521 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
524 #if defined(CONFIG_SYS_FSL_DDR3) || \
525 defined(CONFIG_SYS_FSL_DDR2) || \
526 defined(CONFIG_SYS_FSL_DDR4)
527 /* Chip select options. */
528 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
529 switch (pdimm[0].n_ranks) {
540 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
541 switch (pdimm[0].n_ranks) {
542 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
545 if (pdimm[1].n_ranks)
546 printf("Error: Quad- and Dual-rank DIMMs cannot be used together\n");
550 switch (pdimm[1].n_ranks) {
563 switch (pdimm[1].n_ranks) {
576 switch (pdimm[1].n_ranks) {
586 #endif /* CONFIG_DIMM_SLOTS_PER_CTLR */
587 #endif /* CONFIG_SYS_FSL_DDR2, 3, 4 */
589 /* Pick chip-select local options. */
590 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
591 #if defined(CONFIG_SYS_FSL_DDR3) || \
592 defined(CONFIG_SYS_FSL_DDR2) || \
593 defined(CONFIG_SYS_FSL_DDR4)
594 popts->cs_local_opts[i].odt_rd_cfg = pdodt[i].odt_rd_cfg;
595 popts->cs_local_opts[i].odt_wr_cfg = pdodt[i].odt_wr_cfg;
596 popts->cs_local_opts[i].odt_rtt_norm = pdodt[i].odt_rtt_norm;
597 popts->cs_local_opts[i].odt_rtt_wr = pdodt[i].odt_rtt_wr;
599 popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
600 popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
602 popts->cs_local_opts[i].auto_precharge = 0;
605 /* Pick interleaving mode. */
608 * 0 = no interleaving
609 * 1 = interleaving between 2 controllers
611 popts->memctl_interleaving = 0;
617 * 3 = superbank (only if CS interleaving is enabled)
619 popts->memctl_interleaving_mode = 0;
622 * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
623 * 1: page: bit to the left of the column bits selects the memctl
624 * 2: bank: bit to the left of the bank bits selects the memctl
625 * 3: superbank: bit to the left of the chip select selects the memctl
627 * NOTE: ba_intlv (rank interleaving) is independent of memory
628 * controller interleaving; it is only within a memory controller.
629 * Must use superbank interleaving if rank interleaving is used and
630 * memory controller interleaving is enabled.
637 * 0x60 = CS0,CS1 + CS2,CS3
638 * 0x04 = CS0,CS1,CS2,CS3
640 popts->ba_intlv_ctl = 0;
642 /* Memory Organization Parameters */
643 popts->registered_dimm_en = common_dimm->all_dimms_registered;
645 /* Operational Mode Paramters */
648 popts->ecc_mode = 0; /* 0 = disabled, 1 = enabled */
649 #ifdef CONFIG_DDR_ECC
650 if (hwconfig_sub_f("fsl_ddr", "ecc", buf)) {
651 if (hwconfig_subarg_cmp_f("fsl_ddr", "ecc", "on", buf))
656 popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
663 #if defined(CONFIG_SYS_FSL_DDR1)
664 popts->dqs_config = 0;
665 #elif defined(CONFIG_SYS_FSL_DDR2) || defined(CONFIG_SYS_FSL_DDR3)
666 popts->dqs_config = 1;
669 /* Choose self-refresh during sleep. */
670 popts->self_refresh_in_sleep = 1;
672 /* Choose dynamic power management mode. */
673 popts->dynamic_power = 0;
676 * check first dimm for primary sdram width
677 * presuming all dimms are similar
678 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
680 #if defined(CONFIG_SYS_FSL_DDR1) || defined(CONFIG_SYS_FSL_DDR2)
681 if (pdimm[0].n_ranks != 0) {
682 if ((pdimm[0].data_width >= 64) && \
683 (pdimm[0].data_width <= 72))
684 popts->data_bus_width = 0;
685 else if ((pdimm[0].data_width >= 32) || \
686 (pdimm[0].data_width <= 40))
687 popts->data_bus_width = 1;
689 panic("Error: data width %u is invalid!\n",
690 pdimm[0].data_width);
694 if (pdimm[0].n_ranks != 0) {
695 if (pdimm[0].primary_sdram_width == 64)
696 popts->data_bus_width = 0;
697 else if (pdimm[0].primary_sdram_width == 32)
698 popts->data_bus_width = 1;
699 else if (pdimm[0].primary_sdram_width == 16)
700 popts->data_bus_width = 2;
702 panic("Error: primary sdram width %u is invalid!\n",
703 pdimm[0].primary_sdram_width);
708 popts->x4_en = (pdimm[0].device_width == 4) ? 1 : 0;
710 /* Choose burst length. */
711 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
712 #if defined(CONFIG_E500MC)
713 popts->otf_burst_chop_en = 0; /* on-the-fly burst chop disable */
714 popts->burst_length = DDR_BL8; /* Fixed 8-beat burst len */
716 if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
717 /* 32-bit or 16-bit bus */
718 popts->otf_burst_chop_en = 0;
719 popts->burst_length = DDR_BL8;
721 popts->otf_burst_chop_en = 1; /* on-the-fly burst chop */
722 popts->burst_length = DDR_OTF; /* on-the-fly BC4 and BL8 */
726 popts->burst_length = DDR_BL4; /* has to be 4 for DDR2 */
729 /* Choose ddr controller address mirror mode */
730 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
731 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
732 if (pdimm[i].n_ranks) {
733 popts->mirrored_dimm = pdimm[i].mirrored_dimm;
739 /* Global Timing Parameters. */
740 debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num));
742 /* Pick a caslat override. */
743 popts->cas_latency_override = 0;
744 popts->cas_latency_override_value = 3;
745 if (popts->cas_latency_override) {
746 debug("using caslat override value = %u\n",
747 popts->cas_latency_override_value);
750 /* Decide whether to use the computed derated latency */
751 popts->use_derated_caslat = 0;
753 /* Choose an additive latency. */
754 popts->additive_latency_override = 0;
755 popts->additive_latency_override_value = 3;
756 if (popts->additive_latency_override) {
757 debug("using additive latency override value = %u\n",
758 popts->additive_latency_override_value);
764 * Factors to consider for 2T_EN:
765 * - number of DIMMs installed
766 * - number of components, number of active ranks
767 * - how much time you want to spend playing around
770 popts->threet_en = 0;
772 /* for RDIMM, address parity enable */
776 * BSTTOPRE precharge interval
778 * Set this to 0 for global auto precharge
779 * The value of 0x100 has been used for DDR1, DDR2, DDR3.
780 * It is not wrong. Any value should be OK. The performance depends on
781 * applications. There is no one good value for all. One way to set
782 * is to use 1/4 of refint value.
784 popts->bstopre = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps)
788 * Window for four activates -- tFAW
790 * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
791 * FIXME: varies depending upon number of column addresses or data
792 * FIXME: width, was considering looking at pdimm->primary_sdram_width
794 #if defined(CONFIG_SYS_FSL_DDR1)
795 popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1);
797 #elif defined(CONFIG_SYS_FSL_DDR2)
799 * x4/x8; some datasheets have 35000
800 * x16 wide columns only? Use 50000?
802 popts->tfaw_window_four_activates_ps = 37500;
805 popts->tfaw_window_four_activates_ps = pdimm[0].tfaw_ps;
809 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
811 * due to ddr3 dimm is fly-by topology
812 * we suggest to enable write leveling to
813 * meet the tQDSS under different loading.
817 popts->wrlvl_override = 0;
821 * Check interleaving configuration from environment.
822 * Please refer to doc/README.fsl-ddr for the detail.
824 * If memory controller interleaving is enabled, then the data
825 * bus widths must be programmed identically for all memory controllers.
827 * Attempt to set all controllers to the same chip select
828 * interleaving mode. It will do a best effort to get the
829 * requested ranks interleaved together such that the result
830 * should be a subset of the requested configuration.
832 * if CONFIG_SYS_FSL_DDR_INTLV_256B is defined, mandatory interleaving
833 * with 256 Byte is enabled.
835 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
836 if (!hwconfig_sub_f("fsl_ddr", "ctlr_intlv", buf))
837 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
842 if (pdimm[0].n_ranks == 0) {
843 printf("There is no rank on CS0 for controller %d.\n", ctrl_num);
844 popts->memctl_interleaving = 0;
847 popts->memctl_interleaving = 1;
848 #ifdef CONFIG_SYS_FSL_DDR_INTLV_256B
849 popts->memctl_interleaving_mode = FSL_DDR_256B_INTERLEAVING;
850 popts->memctl_interleaving = 1;
851 debug("256 Byte interleaving\n");
854 * test null first. if CONFIG_HWCONFIG is not defined
855 * hwconfig_arg_cmp returns non-zero
857 if (hwconfig_subarg_cmp_f("fsl_ddr", "ctlr_intlv",
859 popts->memctl_interleaving = 0;
860 debug("memory controller interleaving disabled.\n");
861 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
864 popts->memctl_interleaving_mode =
865 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
866 0 : FSL_DDR_CACHE_LINE_INTERLEAVING;
867 popts->memctl_interleaving =
868 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
870 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
873 popts->memctl_interleaving_mode =
874 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
875 0 : FSL_DDR_PAGE_INTERLEAVING;
876 popts->memctl_interleaving =
877 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
879 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
882 popts->memctl_interleaving_mode =
883 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
884 0 : FSL_DDR_BANK_INTERLEAVING;
885 popts->memctl_interleaving =
886 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
888 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
891 popts->memctl_interleaving_mode =
892 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
893 0 : FSL_DDR_SUPERBANK_INTERLEAVING;
894 popts->memctl_interleaving =
895 ((CONFIG_NUM_DDR_CONTROLLERS == 3) && ctrl_num == 2) ?
897 #if (CONFIG_NUM_DDR_CONTROLLERS == 3)
898 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
901 popts->memctl_interleaving_mode =
902 FSL_DDR_3WAY_1KB_INTERLEAVING;
903 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
906 popts->memctl_interleaving_mode =
907 FSL_DDR_3WAY_4KB_INTERLEAVING;
908 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
911 popts->memctl_interleaving_mode =
912 FSL_DDR_3WAY_8KB_INTERLEAVING;
913 #elif (CONFIG_NUM_DDR_CONTROLLERS == 4)
914 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
917 popts->memctl_interleaving_mode =
918 FSL_DDR_4WAY_1KB_INTERLEAVING;
919 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
922 popts->memctl_interleaving_mode =
923 FSL_DDR_4WAY_4KB_INTERLEAVING;
924 } else if (hwconfig_subarg_cmp_f("fsl_ddr",
927 popts->memctl_interleaving_mode =
928 FSL_DDR_4WAY_8KB_INTERLEAVING;
931 popts->memctl_interleaving = 0;
932 printf("hwconfig has unrecognized parameter for ctlr_intlv.\n");
934 #endif /* CONFIG_SYS_FSL_DDR_INTLV_256B */
936 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
937 if ((hwconfig_sub_f("fsl_ddr", "bank_intlv", buf)) &&
938 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
939 /* test null first. if CONFIG_HWCONFIG is not defined,
940 * hwconfig_subarg_cmp_f returns non-zero */
941 if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
943 debug("bank interleaving disabled.\n");
944 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
946 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
947 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
949 popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
950 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
951 "cs0_cs1_and_cs2_cs3", buf))
952 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
953 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
954 "cs0_cs1_cs2_cs3", buf))
955 popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
956 else if (hwconfig_subarg_cmp_f("fsl_ddr", "bank_intlv",
958 popts->ba_intlv_ctl = auto_bank_intlv(pdimm);
960 printf("hwconfig has unrecognized parameter for bank_intlv.\n");
961 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
962 case FSL_DDR_CS0_CS1_CS2_CS3:
963 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
964 if (pdimm[0].n_ranks < 4) {
965 popts->ba_intlv_ctl = 0;
966 printf("Not enough bank(chip-select) for "
967 "CS0+CS1+CS2+CS3 on controller %d, "
968 "interleaving disabled!\n", ctrl_num);
970 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
971 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
972 if (pdimm[0].n_ranks == 4)
975 if ((pdimm[0].n_ranks < 2) && (pdimm[1].n_ranks < 2)) {
976 popts->ba_intlv_ctl = 0;
977 printf("Not enough bank(chip-select) for "
978 "CS0+CS1+CS2+CS3 on controller %d, "
979 "interleaving disabled!\n", ctrl_num);
981 if (pdimm[0].capacity != pdimm[1].capacity) {
982 popts->ba_intlv_ctl = 0;
983 printf("Not identical DIMM size for "
984 "CS0+CS1+CS2+CS3 on controller %d, "
985 "interleaving disabled!\n", ctrl_num);
989 case FSL_DDR_CS0_CS1:
990 if (pdimm[0].n_ranks < 2) {
991 popts->ba_intlv_ctl = 0;
992 printf("Not enough bank(chip-select) for "
993 "CS0+CS1 on controller %d, "
994 "interleaving disabled!\n", ctrl_num);
997 case FSL_DDR_CS2_CS3:
998 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
999 if (pdimm[0].n_ranks < 4) {
1000 popts->ba_intlv_ctl = 0;
1001 printf("Not enough bank(chip-select) for CS2+CS3 "
1002 "on controller %d, interleaving disabled!\n", ctrl_num);
1004 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1005 if (pdimm[1].n_ranks < 2) {
1006 popts->ba_intlv_ctl = 0;
1007 printf("Not enough bank(chip-select) for CS2+CS3 "
1008 "on controller %d, interleaving disabled!\n", ctrl_num);
1012 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1013 #if (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
1014 if (pdimm[0].n_ranks < 4) {
1015 popts->ba_intlv_ctl = 0;
1016 printf("Not enough bank(CS) for CS0+CS1 and "
1017 "CS2+CS3 on controller %d, "
1018 "interleaving disabled!\n", ctrl_num);
1020 #elif (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
1021 if ((pdimm[0].n_ranks < 2) || (pdimm[1].n_ranks < 2)) {
1022 popts->ba_intlv_ctl = 0;
1023 printf("Not enough bank(CS) for CS0+CS1 and "
1024 "CS2+CS3 on controller %d, "
1025 "interleaving disabled!\n", ctrl_num);
1030 popts->ba_intlv_ctl = 0;
1035 if (hwconfig_sub_f("fsl_ddr", "addr_hash", buf)) {
1036 if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash", "null", buf))
1037 popts->addr_hash = 0;
1038 else if (hwconfig_subarg_cmp_f("fsl_ddr", "addr_hash",
1040 popts->addr_hash = 1;
1043 if (pdimm[0].n_ranks == 4)
1044 popts->quad_rank_present = 1;
1046 ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
1047 if (popts->registered_dimm_en) {
1048 popts->rcw_override = 1;
1049 popts->rcw_1 = 0x000a5a00;
1050 if (ddr_freq <= 800)
1051 popts->rcw_2 = 0x00000000;
1052 else if (ddr_freq <= 1066)
1053 popts->rcw_2 = 0x00100000;
1054 else if (ddr_freq <= 1333)
1055 popts->rcw_2 = 0x00200000;
1057 popts->rcw_2 = 0x00300000;
1060 fsl_ddr_board_options(popts, pdimm, ctrl_num);
1065 void check_interleaving_options(fsl_ddr_info_t *pinfo)
1067 int i, j, k, check_n_ranks, intlv_invalid = 0;
1068 unsigned int check_intlv, check_n_row_addr, check_n_col_addr;
1069 unsigned long long check_rank_density;
1070 struct dimm_params_s *dimm;
1071 int first_ctrl = pinfo->first_ctrl;
1072 int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
1075 * Check if all controllers are configured for memory
1076 * controller interleaving. Identical dimms are recommended. At least
1077 * the size, row and col address should be checked.
1080 check_n_ranks = pinfo->dimm_params[first_ctrl][0].n_ranks;
1081 check_rank_density = pinfo->dimm_params[first_ctrl][0].rank_density;
1082 check_n_row_addr = pinfo->dimm_params[first_ctrl][0].n_row_addr;
1083 check_n_col_addr = pinfo->dimm_params[first_ctrl][0].n_col_addr;
1084 check_intlv = pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode;
1085 for (i = first_ctrl; i <= last_ctrl; i++) {
1086 dimm = &pinfo->dimm_params[i][0];
1087 if (!pinfo->memctl_opts[i].memctl_interleaving) {
1089 } else if (((check_rank_density != dimm->rank_density) ||
1090 (check_n_ranks != dimm->n_ranks) ||
1091 (check_n_row_addr != dimm->n_row_addr) ||
1092 (check_n_col_addr != dimm->n_col_addr) ||
1094 pinfo->memctl_opts[i].memctl_interleaving_mode))){
1102 if (intlv_invalid) {
1103 for (i = first_ctrl; i <= last_ctrl; i++)
1104 pinfo->memctl_opts[i].memctl_interleaving = 0;
1105 printf("Not all DIMMs are identical. "
1106 "Memory controller interleaving disabled.\n");
1108 switch (check_intlv) {
1109 case FSL_DDR_256B_INTERLEAVING:
1110 case FSL_DDR_CACHE_LINE_INTERLEAVING:
1111 case FSL_DDR_PAGE_INTERLEAVING:
1112 case FSL_DDR_BANK_INTERLEAVING:
1113 case FSL_DDR_SUPERBANK_INTERLEAVING:
1114 #if (3 == CONFIG_NUM_DDR_CONTROLLERS)
1117 k = CONFIG_NUM_DDR_CONTROLLERS;
1120 case FSL_DDR_3WAY_1KB_INTERLEAVING:
1121 case FSL_DDR_3WAY_4KB_INTERLEAVING:
1122 case FSL_DDR_3WAY_8KB_INTERLEAVING:
1123 case FSL_DDR_4WAY_1KB_INTERLEAVING:
1124 case FSL_DDR_4WAY_4KB_INTERLEAVING:
1125 case FSL_DDR_4WAY_8KB_INTERLEAVING:
1127 k = CONFIG_NUM_DDR_CONTROLLERS;
1130 debug("%d of %d controllers are interleaving.\n", j, k);
1131 if (j && (j != k)) {
1132 for (i = first_ctrl; i <= last_ctrl; i++)
1133 pinfo->memctl_opts[i].memctl_interleaving = 0;
1134 if ((last_ctrl - first_ctrl) > 1)
1135 puts("Not all controllers have compatible interleaving mode. All disabled.\n");
1138 debug("Checking interleaving options completed\n");
1141 int fsl_use_spd(void)
1145 #ifdef CONFIG_DDR_SPD
1146 char buffer[HWCONFIG_BUFFER_SIZE];
1150 * Extract hwconfig from environment since we have not properly setup
1151 * the environment but need it for ddr config params
1153 if (getenv_f("hwconfig", buffer, sizeof(buffer)) > 0)
1156 /* if hwconfig is not enabled, or "sdram" is not defined, use spd */
1157 if (hwconfig_sub_f("fsl_ddr", "sdram", buf)) {
1158 if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram", "spd", buf))
1160 else if (hwconfig_subarg_cmp_f("fsl_ddr", "sdram",