2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <fsl_ddr_sdram.h>
10 #include <asm/processor.h>
11 #include <fsl_immap.h>
14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
19 * regs has the to-be-set values for DDR controller registers
20 * ctrl_num is the DDR controller number
21 * step: 0 goes through the initialization in one pass
22 * 1 sets registers and returns before enabling controller
23 * 2 resumes from step 1 and continues to initialize
24 * Dividing the initialization to two steps to deassert DDR reset signal
25 * to comply with JEDEC specs for RDIMMs.
27 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
28 unsigned int ctrl_num, int step)
30 unsigned int i, bus_width;
31 struct ccsr_ddr __iomem *ddr;
33 u32 total_gb_size_per_controller;
35 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
36 defined(CONFIG_SYS_FSL_ERRATUM_A008514)
39 #ifdef CONFIG_FSL_DDR_BIST
40 u32 mtcr, err_detect, err_sbe;
41 u32 cs0_bnds, cs1_bnds, cs2_bnds, cs3_bnds, cs0_config;
43 #ifdef CONFIG_FSL_DDR_BIST
44 char buffer[CONFIG_SYS_CBSIZE];
49 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
50 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
51 defined(CONFIG_SYS_FSL_ERRATUM_A008514)
52 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
55 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
57 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
58 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
59 defined(CONFIG_SYS_FSL_ERRATUM_A008514)
60 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
64 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
66 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
67 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
68 defined(CONFIG_SYS_FSL_ERRATUM_A008514)
69 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
73 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
75 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
76 #if defined(CONFIG_SYS_FSL_ERRATUM_A008336) || \
77 defined(CONFIG_SYS_FSL_ERRATUM_A008514)
78 eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR4_ADDR + 0x800;
83 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
90 #ifdef CONFIG_SYS_FSL_ERRATUM_A008336
92 /* A008336 only applies to general DDR controllers */
93 if ((ctrl_num == 0) || (ctrl_num == 1))
95 ddr_out32(eddrtqcr1, 0x63b30002);
97 #ifdef CONFIG_SYS_FSL_ERRATUM_A008514
99 /* A008514 only applies to DP-DDR controler */
102 ddr_out32(eddrtqcr1, 0x63b20002);
105 ddr_out32(&ddr->eor, regs->ddr_eor);
107 ddr_out32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
109 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
111 ddr_out32(&ddr->cs0_bnds, regs->cs[i].bnds);
112 ddr_out32(&ddr->cs0_config, regs->cs[i].config);
113 ddr_out32(&ddr->cs0_config_2, regs->cs[i].config_2);
116 ddr_out32(&ddr->cs1_bnds, regs->cs[i].bnds);
117 ddr_out32(&ddr->cs1_config, regs->cs[i].config);
118 ddr_out32(&ddr->cs1_config_2, regs->cs[i].config_2);
121 ddr_out32(&ddr->cs2_bnds, regs->cs[i].bnds);
122 ddr_out32(&ddr->cs2_config, regs->cs[i].config);
123 ddr_out32(&ddr->cs2_config_2, regs->cs[i].config_2);
126 ddr_out32(&ddr->cs3_bnds, regs->cs[i].bnds);
127 ddr_out32(&ddr->cs3_config, regs->cs[i].config);
128 ddr_out32(&ddr->cs3_config_2, regs->cs[i].config_2);
132 ddr_out32(&ddr->timing_cfg_3, regs->timing_cfg_3);
133 ddr_out32(&ddr->timing_cfg_0, regs->timing_cfg_0);
134 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1);
135 ddr_out32(&ddr->timing_cfg_2, regs->timing_cfg_2);
136 ddr_out32(&ddr->timing_cfg_4, regs->timing_cfg_4);
137 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5);
138 ddr_out32(&ddr->timing_cfg_6, regs->timing_cfg_6);
139 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7);
140 ddr_out32(&ddr->timing_cfg_8, regs->timing_cfg_8);
141 ddr_out32(&ddr->timing_cfg_9, regs->timing_cfg_9);
142 ddr_out32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
143 ddr_out32(&ddr->dq_map_0, regs->dq_map_0);
144 ddr_out32(&ddr->dq_map_1, regs->dq_map_1);
145 ddr_out32(&ddr->dq_map_2, regs->dq_map_2);
146 ddr_out32(&ddr->dq_map_3, regs->dq_map_3);
147 ddr_out32(&ddr->sdram_cfg_3, regs->ddr_sdram_cfg_3);
148 ddr_out32(&ddr->sdram_mode, regs->ddr_sdram_mode);
149 ddr_out32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
150 ddr_out32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
151 ddr_out32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
152 ddr_out32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
153 ddr_out32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
154 ddr_out32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
155 ddr_out32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
156 ddr_out32(&ddr->sdram_mode_9, regs->ddr_sdram_mode_9);
157 ddr_out32(&ddr->sdram_mode_10, regs->ddr_sdram_mode_10);
158 ddr_out32(&ddr->sdram_mode_11, regs->ddr_sdram_mode_11);
159 ddr_out32(&ddr->sdram_mode_12, regs->ddr_sdram_mode_12);
160 ddr_out32(&ddr->sdram_mode_13, regs->ddr_sdram_mode_13);
161 ddr_out32(&ddr->sdram_mode_14, regs->ddr_sdram_mode_14);
162 ddr_out32(&ddr->sdram_mode_15, regs->ddr_sdram_mode_15);
163 ddr_out32(&ddr->sdram_mode_16, regs->ddr_sdram_mode_16);
164 ddr_out32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
165 ddr_out32(&ddr->sdram_interval, regs->ddr_sdram_interval);
166 ddr_out32(&ddr->sdram_data_init, regs->ddr_data_init);
167 ddr_out32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
168 #ifndef CONFIG_SYS_FSL_DDR_EMU
170 * Skip these two registers if running on emulator
171 * because emulator doesn't have skew between bytes.
174 if (regs->ddr_wrlvl_cntl_2)
175 ddr_out32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
176 if (regs->ddr_wrlvl_cntl_3)
177 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
180 ddr_out32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
181 ddr_out32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
182 ddr_out32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
183 ddr_out32(&ddr->ddr_sdram_rcw_3, regs->ddr_sdram_rcw_3);
184 ddr_out32(&ddr->ddr_sdram_rcw_4, regs->ddr_sdram_rcw_4);
185 ddr_out32(&ddr->ddr_sdram_rcw_5, regs->ddr_sdram_rcw_5);
186 ddr_out32(&ddr->ddr_sdram_rcw_6, regs->ddr_sdram_rcw_6);
187 ddr_out32(&ddr->ddr_cdr1, regs->ddr_cdr1);
188 #ifdef CONFIG_DEEP_SLEEP
189 if (is_warm_boot()) {
190 ddr_out32(&ddr->sdram_cfg_2,
191 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
192 ddr_out32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
193 ddr_out32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
195 /* DRAM VRef will not be trained */
196 ddr_out32(&ddr->ddr_cdr2,
197 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
201 ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
202 ddr_out32(&ddr->init_addr, regs->ddr_init_addr);
203 ddr_out32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
204 ddr_out32(&ddr->ddr_cdr2, regs->ddr_cdr2);
206 ddr_out32(&ddr->err_disable, regs->err_disable);
207 ddr_out32(&ddr->err_int_en, regs->err_int_en);
208 for (i = 0; i < 32; i++) {
209 if (regs->debug[i]) {
210 debug("Write to debug_%d as %08x\n",
211 i+1, regs->debug[i]);
212 ddr_out32(&ddr->debug[i], regs->debug[i]);
215 #ifdef CONFIG_SYS_FSL_ERRATUM_A008378
216 /* Erratum applies when accumulated ECC is used, or DBI is enabled */
217 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
218 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
219 if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
220 IS_DBI(regs->ddr_sdram_cfg_3))
221 ddr_setbits32(ddr->debug[28], 0x9 << 20);
225 * For RDIMMs, JEDEC spec requires clocks to be stable before reset is
226 * deasserted. Clocks start when any chip select is enabled and clock
227 * control register is set. Because all DDR components are connected to
228 * one reset signal, this needs to be done in two steps. Step 1 is to
229 * get the clocks started. Step 2 resumes after reset signal is
238 /* Set, but do not enable the memory */
239 temp_sdram_cfg = regs->ddr_sdram_cfg;
240 temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
241 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg);
244 * 500 painful micro-seconds must elapse between
245 * the DDR clock setup and the DDR config enable.
246 * DDR2 need 200 us, and DDR3 need 500 us from spec,
247 * we choose the max, that is 500 us for all of case.
253 #ifdef CONFIG_DEEP_SLEEP
254 if (is_warm_boot()) {
255 /* enter self-refresh */
256 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
257 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
258 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
259 /* do board specific memory setup */
260 board_mem_sleep_setup();
262 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
265 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
266 /* Let the controller go */
267 ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
271 total_gb_size_per_controller = 0;
272 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
273 if (!(regs->cs[i].config & 0x80000000))
275 total_gb_size_per_controller += 1 << (
276 ((regs->cs[i].config >> 14) & 0x3) + 2 +
277 ((regs->cs[i].config >> 8) & 0x7) + 12 +
278 ((regs->cs[i].config >> 4) & 0x3) + 0 +
279 ((regs->cs[i].config >> 0) & 0x7) + 8 +
280 3 - ((regs->ddr_sdram_cfg >> 19) & 0x3) -
281 26); /* minus 26 (count of 64M) */
283 if (fsl_ddr_get_intl3r() & 0x80000000) /* 3-way interleaving */
284 total_gb_size_per_controller *= 3;
285 else if (regs->cs[0].config & 0x20000000) /* 2-way interleaving */
286 total_gb_size_per_controller <<= 1;
288 * total memory / bus width = transactions needed
289 * transactions needed / data rate = seconds
290 * to add plenty of buffer, double the time
291 * For example, 2GB on 666MT/s 64-bit bus takes about 402ms
292 * Let's wait for 800ms
294 bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK)
295 >> SDRAM_CFG_DBW_SHIFT);
296 timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 /
297 (get_ddr_freq(ctrl_num) >> 20)) << 2;
298 total_gb_size_per_controller >>= 4; /* shift down to gb size */
299 debug("total %d GB\n", total_gb_size_per_controller);
300 debug("Need to wait up to %d * 10ms\n", timeout);
302 /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done. */
303 while ((ddr_in32(&ddr->sdram_cfg_2) & SDRAM_CFG2_D_INIT) &&
305 udelay(10000); /* throttle polling rate */
310 printf("Waiting for D_INIT timeout. Memory may not work.\n");
311 #ifdef CONFIG_DEEP_SLEEP
312 if (is_warm_boot()) {
313 /* exit self-refresh */
314 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
315 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
316 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);
320 #ifdef CONFIG_FSL_DDR_BIST
321 #define BIST_PATTERN1 0xFFFFFFFF
322 #define BIST_PATTERN2 0x0
323 #define BIST_CR 0x80010000
324 #define BIST_CR_EN 0x80000000
325 #define BIST_CR_STAT 0x00000001
326 #define CTLR_INTLV_MASK 0x20000000
327 /* Perform build-in test on memory. Three-way interleaving is not yet
328 * supported by this code. */
329 if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
330 puts("Running BIST test. This will take a while...");
331 cs0_config = ddr_in32(&ddr->cs0_config);
332 if (cs0_config & CTLR_INTLV_MASK) {
333 cs0_bnds = ddr_in32(&cs0_bnds);
334 cs1_bnds = ddr_in32(&cs1_bnds);
335 cs2_bnds = ddr_in32(&cs2_bnds);
336 cs3_bnds = ddr_in32(&cs3_bnds);
337 /* set bnds to non-interleaving */
338 ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
339 ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
340 ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
341 ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
343 ddr_out32(&ddr->mtp1, BIST_PATTERN1);
344 ddr_out32(&ddr->mtp2, BIST_PATTERN1);
345 ddr_out32(&ddr->mtp3, BIST_PATTERN2);
346 ddr_out32(&ddr->mtp4, BIST_PATTERN2);
347 ddr_out32(&ddr->mtp5, BIST_PATTERN1);
348 ddr_out32(&ddr->mtp6, BIST_PATTERN1);
349 ddr_out32(&ddr->mtp7, BIST_PATTERN2);
350 ddr_out32(&ddr->mtp8, BIST_PATTERN2);
351 ddr_out32(&ddr->mtp9, BIST_PATTERN1);
352 ddr_out32(&ddr->mtp10, BIST_PATTERN2);
354 ddr_out32(&ddr->mtcr, mtcr);
356 while (timeout > 0 && (mtcr & BIST_CR_EN)) {
359 mtcr = ddr_in32(&ddr->mtcr);
365 err_detect = ddr_in32(&ddr->err_detect);
366 err_sbe = ddr_in32(&ddr->err_sbe);
367 if (mtcr & BIST_CR_STAT) {
368 printf("BIST test failed on controller %d.\n",
371 if (err_detect || (err_sbe & 0xffff)) {
372 printf("ECC error detected on controller %d.\n",
376 if (cs0_config & CTLR_INTLV_MASK) {
377 /* restore bnds registers */
378 ddr_out32(&cs0_bnds, cs0_bnds);
379 ddr_out32(&cs1_bnds, cs1_bnds);
380 ddr_out32(&cs2_bnds, cs2_bnds);
381 ddr_out32(&cs3_bnds, cs3_bnds);