2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * calculate the organization and timing parameter
5 * from ddr3 spd, please refer to the spec
6 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
12 #include <fsl_ddr_sdram.h>
17 * Calculate the Density of each Physical Rank.
18 * Returned size is in bytes.
21 * sdram capacity(bit) / 8 * primary bus width / sdram width
22 * * Logical Ranks per DIMM
24 * where: sdram capacity = spd byte4[3:0]
25 * primary bus width = spd byte13[2:0]
26 * sdram width = spd byte12[2:0]
27 * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
28 * spd byte12{5:3] * spd byte6[6:4] for 3DS
30 * To simplify each rank size = total DIMM size / Number of Package Ranks
31 * where Number of Package Ranks = spd byte12[5:3]
33 * SPD byte4 - sdram density and banks
34 * bit[3:0] size(bit) size(byte)
44 * SPD byte13 - module memory bus width
45 * bit[2:0] primary bus width
51 * SPD byte12 - module organization
52 * bit[2:0] sdram device width
58 * SPD byte12 - module organization
59 * bit[5:3] number of package ranks per DIMM
65 * SPD byte6 - SDRAM package type
76 * SPD byte6 - SRAM package type
77 * bit[1:0] Signal loading
80 * 10 Sigle load stack (3DS)
83 static unsigned long long
84 compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
86 unsigned long long bsize;
88 int nbit_sdram_cap_bsize = 0;
89 int nbit_primary_bus_width = 0;
90 int nbit_sdram_width = 0;
94 if ((spd->density_banks & 0xf) <= 7)
95 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
96 if ((spd->bus_width & 0x7) < 4)
97 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
98 if ((spd->organization & 0x7) < 4)
99 nbit_sdram_width = (spd->organization & 0x7) + 2;
100 package_3ds = (spd->package_type & 0x3) == 0x2;
102 die_count = (spd->package_type >> 4) & 0x7;
104 bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
105 nbit_primary_bus_width - nbit_sdram_width +
108 debug("DDR: DDR III rank density = 0x%16llx\n", bsize);
113 #define spd_to_ps(mtb, ftb) \
114 (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
116 * ddr_compute_dimm_parameters for DDR4 SPD
118 * Compute DIMM parameters based upon the SPD information in spd.
119 * Writes the results to the dimm_params_t structure pointed by pdimm.
122 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
123 const generic_spd_eeprom_t *spd,
124 dimm_params_t *pdimm,
125 unsigned int dimm_number)
129 const u8 udimm_rc_e_dq[18] = {
130 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
131 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
137 if (spd->mem_type != SPD_MEMTYPE_DDR4) {
138 printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
139 ctrl_num, dimm_number);
143 memset(pdimm, 0, sizeof(dimm_params_t));
147 retval = ddr4_spd_check(spd);
149 printf("DIMM %u: failed checksum\n", dimm_number);
154 * The part name in ASCII in the SPD EEPROM is not null terminated.
155 * Guarantee null termination here by presetting all bytes to 0
156 * and copying the part name in ASCII from the SPD onto it
158 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
159 if ((spd->info_size_crc & 0xF) > 2)
160 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
162 /* DIMM organization parameters */
163 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
164 pdimm->rank_density = compute_ranksize(spd);
165 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
166 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
167 if ((spd->bus_width >> 3) & 0x3)
168 pdimm->ec_sdram_width = 8;
170 pdimm->ec_sdram_width = 0;
171 pdimm->data_width = pdimm->primary_sdram_width
172 + pdimm->ec_sdram_width;
173 pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
175 /* These are the types defined by the JEDEC SPD spec */
176 pdimm->mirrored_dimm = 0;
177 pdimm->registered_dimm = 0;
178 switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
179 case DDR4_SPD_MODULETYPE_RDIMM:
180 /* Registered/buffered DIMMs */
181 pdimm->registered_dimm = 1;
184 case DDR4_SPD_MODULETYPE_UDIMM:
185 case DDR4_SPD_MODULETYPE_SO_DIMM:
186 /* Unbuffered DIMMs */
187 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
188 pdimm->mirrored_dimm = 1;
189 if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
190 (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
191 /* Fix SPD error found on DIMMs with raw card E0 */
192 for (i = 0; i < 18; i++) {
193 if (spd->mapping[i] == udimm_rc_e_dq[i])
196 debug("SPD byte %d: 0x%x, should be 0x%x\n",
197 60 + i, spd->mapping[i],
199 ptr = (u8 *)&spd->mapping[i];
200 *ptr = udimm_rc_e_dq[i];
203 puts("SPD DQ mapping error fixed\n");
208 printf("unknown module_type 0x%02X\n", spd->module_type);
212 /* SDRAM device parameters */
213 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
214 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
215 pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
216 pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
219 * The SPD spec has not the ECC bit,
220 * We consider the DIMM as ECC capability
221 * when the extension bus exist
223 if (pdimm->ec_sdram_width)
224 pdimm->edc_config = 0x02;
226 pdimm->edc_config = 0x00;
229 * The SPD spec has not the burst length byte
230 * but DDR4 spec has nature BL8 and BC4,
231 * BL8 -bit3, BC4 -bit2
233 pdimm->burst_lengths_bitmask = 0x0c;
234 pdimm->row_density = __ilog2(pdimm->rank_density);
236 /* MTB - medium timebase
237 * The MTB in the SPD spec is 125ps,
239 * FTB - fine timebase
240 * use 1/10th of ps as our unit to avoid floating point
241 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
243 if ((spd->timebases & 0xf) == 0x0) {
245 pdimm->ftb_10th_ps = 10;
248 printf("Unknown Timebases\n");
251 /* sdram minimum cycle time */
252 pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
254 /* sdram max cycle time */
255 pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
258 * CAS latency supported
265 pdimm->caslat_x = (spd->caslat_b1 << 7) |
266 (spd->caslat_b2 << 15) |
267 (spd->caslat_b3 << 23);
269 BUG_ON(spd->caslat_b4 != 0);
272 * min CAS latency time
274 pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
277 * min RAS to CAS delay time
279 pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
282 * Min Row Precharge Delay Time
284 pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
286 /* min active to precharge delay time */
287 pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
288 spd->tras_min_lsb) * pdimm->mtb_ps;
290 /* min active to actice/refresh delay time */
291 pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
292 spd->trc_min_lsb), spd->fine_trc_min);
293 /* Min Refresh Recovery Delay Time */
294 pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
296 pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
298 pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
300 /* min four active window delay time */
301 pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
304 /* min row active to row active delay time, different bank group */
305 pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
306 /* min row active to row active delay time, same bank group */
307 pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
308 /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
309 pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
312 * Average periodic refresh interval
313 * tREFI = 7.8 us at normal temperature range
315 pdimm->refresh_rate_ps = 7800000;
317 for (i = 0; i < 18; i++)
318 pdimm->dq_mapping[i] = spd->mapping[i];
320 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;