2 * Copyright 2014-2016 Freescale Semiconductor, Inc.
3 * Copyright 2017-2018 NXP Semiconductor
5 * SPDX-License-Identifier: GPL-2.0+
7 * calculate the organization and timing parameter
8 * from ddr3 spd, please refer to the spec
9 * JEDEC standard No.21-C 4_01_02_12R23A.pdf
15 #include <fsl_ddr_sdram.h>
20 * Calculate the Density of each Physical Rank.
21 * Returned size is in bytes.
24 * sdram capacity(bit) / 8 * primary bus width / sdram width
25 * * Logical Ranks per DIMM
27 * where: sdram capacity = spd byte4[3:0]
28 * primary bus width = spd byte13[2:0]
29 * sdram width = spd byte12[2:0]
30 * Logical Ranks per DIMM = spd byte12[5:3] for SDP, DDP, QDP
31 * spd byte12{5:3] * spd byte6[6:4] for 3DS
33 * To simplify each rank size = total DIMM size / Number of Package Ranks
34 * where Number of Package Ranks = spd byte12[5:3]
36 * SPD byte4 - sdram density and banks
37 * bit[3:0] size(bit) size(byte)
47 * SPD byte13 - module memory bus width
48 * bit[2:0] primary bus width
54 * SPD byte12 - module organization
55 * bit[2:0] sdram device width
61 * SPD byte12 - module organization
62 * bit[5:3] number of package ranks per DIMM
68 * SPD byte6 - SDRAM package type
79 * SPD byte6 - SRAM package type
80 * bit[1:0] Signal loading
83 * 10 Sigle load stack (3DS)
86 static unsigned long long
87 compute_ranksize(const struct ddr4_spd_eeprom_s *spd)
89 unsigned long long bsize;
91 int nbit_sdram_cap_bsize = 0;
92 int nbit_primary_bus_width = 0;
93 int nbit_sdram_width = 0;
97 if ((spd->density_banks & 0xf) <= 7)
98 nbit_sdram_cap_bsize = (spd->density_banks & 0xf) + 28;
99 if ((spd->bus_width & 0x7) < 4)
100 nbit_primary_bus_width = (spd->bus_width & 0x7) + 3;
101 if ((spd->organization & 0x7) < 4)
102 nbit_sdram_width = (spd->organization & 0x7) + 2;
103 package_3ds = (spd->package_type & 0x3) == 0x2;
104 if ((spd->package_type & 0x80) && !package_3ds) { /* other than 3DS */
105 printf("Warning: not supported SDRAM package type\n");
109 die_count = (spd->package_type >> 4) & 0x7;
111 bsize = 1ULL << (nbit_sdram_cap_bsize - 3 +
112 nbit_primary_bus_width - nbit_sdram_width +
115 debug("DDR: DDR rank density = 0x%16llx\n", bsize);
120 #define spd_to_ps(mtb, ftb) \
121 (mtb * pdimm->mtb_ps + (ftb * pdimm->ftb_10th_ps) / 10)
123 * ddr_compute_dimm_parameters for DDR4 SPD
125 * Compute DIMM parameters based upon the SPD information in spd.
126 * Writes the results to the dimm_params_t structure pointed by pdimm.
129 unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num,
130 const generic_spd_eeprom_t *spd,
131 dimm_params_t *pdimm,
132 unsigned int dimm_number)
136 const u8 udimm_rc_e_dq[18] = {
137 0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
138 0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
144 if (spd->mem_type != SPD_MEMTYPE_DDR4) {
145 printf("Ctrl %u DIMM %u: is not a DDR4 SPD.\n",
146 ctrl_num, dimm_number);
150 memset(pdimm, 0, sizeof(dimm_params_t));
154 retval = ddr4_spd_check(spd);
156 printf("DIMM %u: failed checksum\n", dimm_number);
161 * The part name in ASCII in the SPD EEPROM is not null terminated.
162 * Guarantee null termination here by presetting all bytes to 0
163 * and copying the part name in ASCII from the SPD onto it
165 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
166 if ((spd->info_size_crc & 0xF) > 2)
167 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
169 /* DIMM organization parameters */
170 pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
171 pdimm->rank_density = compute_ranksize(spd);
172 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
173 pdimm->die_density = spd->density_banks & 0xf;
174 pdimm->primary_sdram_width = 1 << (3 + (spd->bus_width & 0x7));
175 if ((spd->bus_width >> 3) & 0x3)
176 pdimm->ec_sdram_width = 8;
178 pdimm->ec_sdram_width = 0;
179 pdimm->data_width = pdimm->primary_sdram_width
180 + pdimm->ec_sdram_width;
181 pdimm->device_width = 1 << ((spd->organization & 0x7) + 2);
182 pdimm->package_3ds = (spd->package_type & 0x3) == 0x2 ?
183 (spd->package_type >> 4) & 0x7 : 0;
185 /* These are the types defined by the JEDEC SPD spec */
186 pdimm->mirrored_dimm = 0;
187 pdimm->registered_dimm = 0;
188 switch (spd->module_type & DDR4_SPD_MODULETYPE_MASK) {
189 case DDR4_SPD_MODULETYPE_RDIMM:
190 /* Registered/buffered DIMMs */
191 pdimm->registered_dimm = 1;
192 if (spd->mod_section.registered.reg_map & 0x1)
193 pdimm->mirrored_dimm = 1;
196 case DDR4_SPD_MODULETYPE_UDIMM:
197 case DDR4_SPD_MODULETYPE_SO_DIMM:
198 /* Unbuffered DIMMs */
199 if (spd->mod_section.unbuffered.addr_mapping & 0x1)
200 pdimm->mirrored_dimm = 1;
201 if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
202 (spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
203 /* Fix SPD error found on DIMMs with raw card E0 */
204 for (i = 0; i < 18; i++) {
205 if (spd->mapping[i] == udimm_rc_e_dq[i])
208 debug("SPD byte %d: 0x%x, should be 0x%x\n",
209 60 + i, spd->mapping[i],
211 ptr = (u8 *)&spd->mapping[i];
212 *ptr = udimm_rc_e_dq[i];
215 puts("SPD DQ mapping error fixed\n");
220 printf("unknown module_type 0x%02X\n", spd->module_type);
224 /* SDRAM device parameters */
225 pdimm->n_row_addr = ((spd->addressing >> 3) & 0x7) + 12;
226 pdimm->n_col_addr = (spd->addressing & 0x7) + 9;
227 pdimm->bank_addr_bits = (spd->density_banks >> 4) & 0x3;
228 pdimm->bank_group_bits = (spd->density_banks >> 6) & 0x3;
231 * The SPD spec has not the ECC bit,
232 * We consider the DIMM as ECC capability
233 * when the extension bus exist
235 if (pdimm->ec_sdram_width)
236 pdimm->edc_config = 0x02;
238 pdimm->edc_config = 0x00;
241 * The SPD spec has not the burst length byte
242 * but DDR4 spec has nature BL8 and BC4,
243 * BL8 -bit3, BC4 -bit2
245 pdimm->burst_lengths_bitmask = 0x0c;
246 pdimm->row_density = __ilog2(pdimm->rank_density);
248 /* MTB - medium timebase
249 * The MTB in the SPD spec is 125ps,
251 * FTB - fine timebase
252 * use 1/10th of ps as our unit to avoid floating point
253 * eg, 10 for 1ps, 25 for 2.5ps, 50 for 5ps
255 if ((spd->timebases & 0xf) == 0x0) {
257 pdimm->ftb_10th_ps = 10;
260 printf("Unknown Timebases\n");
263 /* sdram minimum cycle time */
264 pdimm->tckmin_x_ps = spd_to_ps(spd->tck_min, spd->fine_tck_min);
266 /* sdram max cycle time */
267 pdimm->tckmax_ps = spd_to_ps(spd->tck_max, spd->fine_tck_max);
270 * CAS latency supported
277 pdimm->caslat_x = (spd->caslat_b1 << 7) |
278 (spd->caslat_b2 << 15) |
279 (spd->caslat_b3 << 23);
281 BUG_ON(spd->caslat_b4 != 0);
284 * min CAS latency time
286 pdimm->taa_ps = spd_to_ps(spd->taa_min, spd->fine_taa_min);
289 * min RAS to CAS delay time
291 pdimm->trcd_ps = spd_to_ps(spd->trcd_min, spd->fine_trcd_min);
294 * Min Row Precharge Delay Time
296 pdimm->trp_ps = spd_to_ps(spd->trp_min, spd->fine_trp_min);
298 /* min active to precharge delay time */
299 pdimm->tras_ps = (((spd->tras_trc_ext & 0xf) << 8) +
300 spd->tras_min_lsb) * pdimm->mtb_ps;
302 /* min active to actice/refresh delay time */
303 pdimm->trc_ps = spd_to_ps((((spd->tras_trc_ext & 0xf0) << 4) +
304 spd->trc_min_lsb), spd->fine_trc_min);
305 /* Min Refresh Recovery Delay Time */
306 pdimm->trfc1_ps = ((spd->trfc1_min_msb << 8) | (spd->trfc1_min_lsb)) *
308 pdimm->trfc2_ps = ((spd->trfc2_min_msb << 8) | (spd->trfc2_min_lsb)) *
310 pdimm->trfc4_ps = ((spd->trfc4_min_msb << 8) | (spd->trfc4_min_lsb)) *
312 /* min four active window delay time */
313 pdimm->tfaw_ps = (((spd->tfaw_msb & 0xf) << 8) | spd->tfaw_min) *
316 /* min row active to row active delay time, different bank group */
317 pdimm->trrds_ps = spd_to_ps(spd->trrds_min, spd->fine_trrds_min);
318 /* min row active to row active delay time, same bank group */
319 pdimm->trrdl_ps = spd_to_ps(spd->trrdl_min, spd->fine_trrdl_min);
320 /* min CAS to CAS Delay Time (tCCD_Lmin), same bank group */
321 pdimm->tccdl_ps = spd_to_ps(spd->tccdl_min, spd->fine_tccdl_min);
323 if (pdimm->package_3ds) {
324 if (pdimm->die_density <= 0x4) {
325 pdimm->trfc_slr_ps = 260000;
326 } else if (pdimm->die_density <= 0x5) {
327 pdimm->trfc_slr_ps = 350000;
329 printf("WARN: Unsupported logical rank density 0x%x\n",
335 * Average periodic refresh interval
336 * tREFI = 7.8 us at normal temperature range
338 pdimm->refresh_rate_ps = 7800000;
340 for (i = 0; i < 18; i++)
341 pdimm->dq_mapping[i] = spd->mapping[i];
343 pdimm->dq_mapping_ors = ((spd->mapping[0] >> 6) & 0x3) == 0 ? 1 : 0;