drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 /*
  21  * Determine Rtt value.
  22  *
  23  * This should likely be either board or controller specific.
  24  *
  25  * Rtt(nominal) - DDR2:
  26  *      0 = Rtt disabled
  27  *      1 = 75 ohm
  28  *      2 = 150 ohm
  29  *      3 = 50 ohm
  30  * Rtt(nominal) - DDR3:
  31  *      0 = Rtt disabled
  32  *      1 = 60 ohm
  33  *      2 = 120 ohm
  34  *      3 = 40 ohm
  35  *      4 = 20 ohm
  36  *      5 = 30 ohm
  37  *
  38  * FIXME: Apparently 8641 needs a value of 2
  39  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  40  *
  41  * FIXME: There was some effort down this line earlier:
  42  *
  43  *      unsigned int i;
  44  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  45  *              if (popts->dimmslot[i].num_valid_cs
  46  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  47  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  48  *                      rtt = 2;
  49  *                      break;
  50  *              }
  51  *      }
  52  */
  53 static inline int fsl_ddr_get_rtt(void)
  54 {
  55         int rtt;
  56
  57 #if defined(CONFIG_SYS_FSL_DDR1)
  58         rtt = 0;
  59 #elif defined(CONFIG_SYS_FSL_DDR2)
  60         rtt = 3;
  61 #else
  62         rtt = 0;
  63 #endif
  64
  65         return rtt;
  66 }
  67
  68 #ifdef CONFIG_SYS_FSL_DDR4
  69 /*
  70  * compute CAS write latency according to DDR4 spec
  71  * CWL = 9 for <= 1600MT/s
  72  *       10 for <= 1866MT/s
  73  *       11 for <= 2133MT/s
  74  *       12 for <= 2400MT/s
  75  *       14 for <= 2667MT/s
  76  *       16 for <= 2933MT/s
  77  *       18 for higher
  78  */
  79 static inline unsigned int compute_cas_write_latency(
  80                                 const unsigned int ctrl_num)
  81 {
  82         unsigned int cwl;
  83         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  84         if (mclk_ps >= 1250)
  85                 cwl = 9;
  86         else if (mclk_ps >= 1070)
  87                 cwl = 10;
  88         else if (mclk_ps >= 935)
  89                 cwl = 11;
  90         else if (mclk_ps >= 833)
  91                 cwl = 12;
  92         else if (mclk_ps >= 750)
  93                 cwl = 14;
  94         else if (mclk_ps >= 681)
  95                 cwl = 16;
  96         else
  97                 cwl = 18;
  98
  99         return cwl;
 100 }
 101 #else
 102 /*
 103  * compute the CAS write latency according to DDR3 spec
 104  * CWL = 5 if tCK >= 2.5ns
 105  *       6 if 2.5ns > tCK >= 1.875ns
 106  *       7 if 1.875ns > tCK >= 1.5ns
 107  *       8 if 1.5ns > tCK >= 1.25ns
 108  *       9 if 1.25ns > tCK >= 1.07ns
 109  *       10 if 1.07ns > tCK >= 0.935ns
 110  *       11 if 0.935ns > tCK >= 0.833ns
 111  *       12 if 0.833ns > tCK >= 0.75ns
 112  */
 113 static inline unsigned int compute_cas_write_latency(
 114                                 const unsigned int ctrl_num)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 /*
 257  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 258  * Return 1 if other two slots configuration. Return 0 if single slot.
 259  */
 260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 261 {
 262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 263         if (dimm_params[0].n_ranks == 4)
 264                 return 2;
 265 #endif
 266
 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 268         if ((dimm_params[0].n_ranks == 2) &&
 269                 (dimm_params[1].n_ranks == 2))
 270                 return 2;
 271
 272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 273         if (dimm_params[0].n_ranks == 4)
 274                 return 2;
 275 #endif
 276
 277         if ((dimm_params[0].n_ranks != 0) &&
 278             (dimm_params[2].n_ranks != 0))
 279                 return 1;
 280 #endif
 281         return 0;
 282 }
 283
 284 /*
 285  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 286  *
 287  * Avoid writing for DDR I.  The new PQ38 DDR controller
 288  * dreams up non-zero default values to be backwards compatible.
 289  */
 290 static void set_timing_cfg_0(const unsigned int ctrl_num,
 291                                 fsl_ddr_cfg_regs_t *ddr,
 292                                 const memctl_options_t *popts,
 293                                 const dimm_params_t *dimm_params)
 294 {
 295         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 296         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 297         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 298         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 299         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 300
 301         /* Active powerdown exit timing (tXARD and tXARDS). */
 302         unsigned char act_pd_exit_mclk;
 303         /* Precharge powerdown exit timing (tXP). */
 304         unsigned char pre_pd_exit_mclk;
 305         /* ODT powerdown exit timing (tAXPD). */
 306         unsigned char taxpd_mclk = 0;
 307         /* Mode register set cycle time (tMRD). */
 308         unsigned char tmrd_mclk;
 309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 310         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 311 #endif
 312
 313 #ifdef CONFIG_SYS_FSL_DDR4
 314         /* tXP=max(4nCK, 6ns) */
 315         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 316         unsigned int data_rate = get_ddr_freq(ctrl_num);
 317
 318         /* for faster clock, need more time for data setup */
 319         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 320         twrt_mclk = 1;
 321         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 322         pre_pd_exit_mclk = act_pd_exit_mclk;
 323         /*
 324          * MRS_CYC = max(tMRD, tMOD)
 325          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 326          */
 327         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 328 #elif defined(CONFIG_SYS_FSL_DDR3)
 329         unsigned int data_rate = get_ddr_freq(ctrl_num);
 330         int txp;
 331         unsigned int ip_rev;
 332         int odt_overlap;
 333         /*
 334          * (tXARD and tXARDS). Empirical?
 335          * The DDR3 spec has not tXARD,
 336          * we use the tXP instead of it.
 337          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 338          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 339          * spec has not the tAXPD, we use
 340          * tAXPD=1, need design to confirm.
 341          */
 342         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 343
 344         ip_rev = fsl_ddr_get_version(ctrl_num);
 345         if (ip_rev >= 0x40700) {
 346                 /*
 347                  * MRS_CYC = max(tMRD, tMOD)
 348                  * tMRD = 4nCK (8nCK for RDIMM)
 349                  * tMOD = max(12nCK, 15ns)
 350                  */
 351                 tmrd_mclk = max((unsigned int)12,
 352                                 picos_to_mclk(ctrl_num, 15000));
 353         } else {
 354                 /*
 355                  * MRS_CYC = tMRD
 356                  * tMRD = 4nCK (8nCK for RDIMM)
 357                  */
 358                 if (popts->registered_dimm_en)
 359                         tmrd_mclk = 8;
 360                 else
 361                         tmrd_mclk = 4;
 362         }
 363
 364         /* set the turnaround time */
 365
 366         /*
 367          * for single quad-rank DIMM and two-slot DIMMs
 368          * to avoid ODT overlap
 369          */
 370         odt_overlap = avoid_odt_overlap(dimm_params);
 371         switch (odt_overlap) {
 372         case 2:
 373                 twwt_mclk = 2;
 374                 trrt_mclk = 1;
 375                 break;
 376         case 1:
 377                 twwt_mclk = 1;
 378                 trrt_mclk = 0;
 379                 break;
 380         default:
 381                 break;
 382         }
 383
 384         /* for faster clock, need more time for data setup */
 385         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 386
 387         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 388                 twrt_mclk = 1;
 389
 390         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 391                 act_pd_exit_mclk = 1;
 392                 pre_pd_exit_mclk = 1;
 393                 taxpd_mclk = 1;
 394         } else {
 395                 /* act_pd_exit_mclk = tXARD, see above */
 396                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 397                 /* Mode register MR0[A12] is '1' - fast exit */
 398                 pre_pd_exit_mclk = act_pd_exit_mclk;
 399                 taxpd_mclk = 1;
 400         }
 401 #else /* CONFIG_SYS_FSL_DDR2 */
 402         /*
 403          * (tXARD and tXARDS). Empirical?
 404          * tXARD = 2 for DDR2
 405          * tXP=2
 406          * tAXPD=8
 407          */
 408         act_pd_exit_mclk = 2;
 409         pre_pd_exit_mclk = 2;
 410         taxpd_mclk = 8;
 411         tmrd_mclk = 2;
 412 #endif
 413
 414         if (popts->trwt_override)
 415                 trwt_mclk = popts->trwt;
 416
 417         ddr->timing_cfg_0 = (0
 418                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 419                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 420                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 421                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 422                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 423                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 424                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 425                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 426                 );
 427         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 428 }
 429 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 430
 431 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 432 static void set_timing_cfg_3(const unsigned int ctrl_num,
 433                              fsl_ddr_cfg_regs_t *ddr,
 434                              const memctl_options_t *popts,
 435                              const common_timing_params_t *common_dimm,
 436                              unsigned int cas_latency,
 437                              unsigned int additive_latency)
 438 {
 439         /* Extended precharge to activate interval (tRP) */
 440         unsigned int ext_pretoact = 0;
 441         /* Extended Activate to precharge interval (tRAS) */
 442         unsigned int ext_acttopre = 0;
 443         /* Extended activate to read/write interval (tRCD) */
 444         unsigned int ext_acttorw = 0;
 445         /* Extended refresh recovery time (tRFC) */
 446         unsigned int ext_refrec;
 447         /* Extended MCAS latency from READ cmd */
 448         unsigned int ext_caslat = 0;
 449         /* Extended additive latency */
 450         unsigned int ext_add_lat = 0;
 451         /* Extended last data to precharge interval (tWR) */
 452         unsigned int ext_wrrec = 0;
 453         /* Control Adjust */
 454         unsigned int cntl_adj = 0;
 455
 456         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 457         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 458         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 459         ext_caslat = (2 * cas_latency - 1) >> 4;
 460         ext_add_lat = additive_latency >> 4;
 461 #ifdef CONFIG_SYS_FSL_DDR4
 462         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 463 #else
 464         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 465         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 466 #endif
 467         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 468                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 469
 470         ddr->timing_cfg_3 = (0
 471                 | ((ext_pretoact & 0x1) << 28)
 472                 | ((ext_acttopre & 0x3) << 24)
 473                 | ((ext_acttorw & 0x1) << 22)
 474                 | ((ext_refrec & 0x1F) << 16)
 475                 | ((ext_caslat & 0x3) << 12)
 476                 | ((ext_add_lat & 0x1) << 10)
 477                 | ((ext_wrrec & 0x1) << 8)
 478                 | ((cntl_adj & 0x7) << 0)
 479                 );
 480         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 481 }
 482
 483 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 484 static void set_timing_cfg_1(const unsigned int ctrl_num,
 485                              fsl_ddr_cfg_regs_t *ddr,
 486                              const memctl_options_t *popts,
 487                              const common_timing_params_t *common_dimm,
 488                              unsigned int cas_latency)
 489 {
 490         /* Precharge-to-activate interval (tRP) */
 491         unsigned char pretoact_mclk;
 492         /* Activate to precharge interval (tRAS) */
 493         unsigned char acttopre_mclk;
 494         /*  Activate to read/write interval (tRCD) */
 495         unsigned char acttorw_mclk;
 496         /* CASLAT */
 497         unsigned char caslat_ctrl;
 498         /*  Refresh recovery time (tRFC) ; trfc_low */
 499         unsigned char refrec_ctrl;
 500         /* Last data to precharge minimum interval (tWR) */
 501         unsigned char wrrec_mclk;
 502         /* Activate-to-activate interval (tRRD) */
 503         unsigned char acttoact_mclk;
 504         /* Last write data pair to read command issue interval (tWTR) */
 505         unsigned char wrtord_mclk;
 506 #ifdef CONFIG_SYS_FSL_DDR4
 507         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 508         static const u8 wrrec_table[] = {
 509                 10, 10, 10, 10, 10,
 510                 10, 10, 10, 10, 10,
 511                 12, 12, 14, 14, 16,
 512                 16, 18, 18, 20, 20,
 513                 24, 24, 24, 24};
 514 #else
 515         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 516         static const u8 wrrec_table[] = {
 517                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 518 #endif
 519
 520         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 521         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 522         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 523
 524         /*
 525          * Translate CAS Latency to a DDR controller field value:
 526          *
 527          *      CAS Lat DDR I   DDR II  Ctrl
 528          *      Clocks  SPD Bit SPD Bit Value
 529          *      ------- ------- ------- -----
 530          *      1.0     0               0001
 531          *      1.5     1               0010
 532          *      2.0     2       2       0011
 533          *      2.5     3               0100
 534          *      3.0     4       3       0101
 535          *      3.5     5               0110
 536          *      4.0             4       0111
 537          *      4.5                     1000
 538          *      5.0             5       1001
 539          */
 540 #if defined(CONFIG_SYS_FSL_DDR1)
 541         caslat_ctrl = (cas_latency + 1) & 0x07;
 542 #elif defined(CONFIG_SYS_FSL_DDR2)
 543         caslat_ctrl = 2 * cas_latency - 1;
 544 #else
 545         /*
 546          * if the CAS latency more than 8 cycle,
 547          * we need set extend bit for it at
 548          * TIMING_CFG_3[EXT_CASLAT]
 549          */
 550         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 551                 caslat_ctrl = 2 * cas_latency - 1;
 552         else
 553                 caslat_ctrl = (cas_latency - 1) << 1;
 554 #endif
 555
 556 #ifdef CONFIG_SYS_FSL_DDR4
 557         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 558         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 559         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 560         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 561         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 562                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 563         else
 564                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 565 #else
 566         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 567         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 568         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 569         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 570         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 571                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 572         else
 573                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 574 #endif
 575         if (popts->otf_burst_chop_en)
 576                 wrrec_mclk += 2;
 577
 578         /*
 579          * JEDEC has min requirement for tRRD
 580          */
 581 #if defined(CONFIG_SYS_FSL_DDR3)
 582         if (acttoact_mclk < 4)
 583                 acttoact_mclk = 4;
 584 #endif
 585         /*
 586          * JEDEC has some min requirements for tWTR
 587          */
 588 #if defined(CONFIG_SYS_FSL_DDR2)
 589         if (wrtord_mclk < 2)
 590                 wrtord_mclk = 2;
 591 #elif defined(CONFIG_SYS_FSL_DDR3)
 592         if (wrtord_mclk < 4)
 593                 wrtord_mclk = 4;
 594 #endif
 595         if (popts->otf_burst_chop_en)
 596                 wrtord_mclk += 2;
 597
 598         ddr->timing_cfg_1 = (0
 599                 | ((pretoact_mclk & 0x0F) << 28)
 600                 | ((acttopre_mclk & 0x0F) << 24)
 601                 | ((acttorw_mclk & 0xF) << 20)
 602                 | ((caslat_ctrl & 0xF) << 16)
 603                 | ((refrec_ctrl & 0xF) << 12)
 604                 | ((wrrec_mclk & 0x0F) << 8)
 605                 | ((acttoact_mclk & 0x0F) << 4)
 606                 | ((wrtord_mclk & 0x0F) << 0)
 607                 );
 608         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 609 }
 610
 611 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 612 static void set_timing_cfg_2(const unsigned int ctrl_num,
 613                              fsl_ddr_cfg_regs_t *ddr,
 614                              const memctl_options_t *popts,
 615                              const common_timing_params_t *common_dimm,
 616                              unsigned int cas_latency,
 617                              unsigned int additive_latency)
 618 {
 619         /* Additive latency */
 620         unsigned char add_lat_mclk;
 621         /* CAS-to-preamble override */
 622         unsigned short cpo;
 623         /* Write latency */
 624         unsigned char wr_lat;
 625         /*  Read to precharge (tRTP) */
 626         unsigned char rd_to_pre;
 627         /* Write command to write data strobe timing adjustment */
 628         unsigned char wr_data_delay;
 629         /* Minimum CKE pulse width (tCKE) */
 630         unsigned char cke_pls;
 631         /* Window for four activates (tFAW) */
 632         unsigned short four_act;
 633 #ifdef CONFIG_SYS_FSL_DDR3
 634         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 635 #endif
 636
 637         /* FIXME add check that this must be less than acttorw_mclk */
 638         add_lat_mclk = additive_latency;
 639         cpo = popts->cpo_override;
 640
 641 #if defined(CONFIG_SYS_FSL_DDR1)
 642         /*
 643          * This is a lie.  It should really be 1, but if it is
 644          * set to 1, bits overlap into the old controller's
 645          * otherwise unused ACSM field.  If we leave it 0, then
 646          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 647          */
 648         wr_lat = 0;
 649 #elif defined(CONFIG_SYS_FSL_DDR2)
 650         wr_lat = cas_latency - 1;
 651 #else
 652         wr_lat = compute_cas_write_latency(ctrl_num);
 653 #endif
 654
 655 #ifdef CONFIG_SYS_FSL_DDR4
 656         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 657 #else
 658         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 659 #endif
 660         /*
 661          * JEDEC has some min requirements for tRTP
 662          */
 663 #if defined(CONFIG_SYS_FSL_DDR2)
 664         if (rd_to_pre  < 2)
 665                 rd_to_pre  = 2;
 666 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 667         if (rd_to_pre < 4)
 668                 rd_to_pre = 4;
 669 #endif
 670         if (popts->otf_burst_chop_en)
 671                 rd_to_pre += 2; /* according to UM */
 672
 673         wr_data_delay = popts->write_data_delay;
 674 #ifdef CONFIG_SYS_FSL_DDR4
 675         cpo = 0;
 676         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 677 #elif defined(CONFIG_SYS_FSL_DDR3)
 678         /*
 679          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 680          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 681          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 682          */
 683         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 684                                         (mclk_ps > 1245 ? 5625 : 5000)));
 685 #else
 686         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 687 #endif
 688         four_act = picos_to_mclk(ctrl_num,
 689                                  popts->tfaw_window_four_activates_ps);
 690
 691         ddr->timing_cfg_2 = (0
 692                 | ((add_lat_mclk & 0xf) << 28)
 693                 | ((cpo & 0x1f) << 23)
 694                 | ((wr_lat & 0xf) << 19)
 695                 | ((wr_lat & 0x10) << 14)
 696                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 697                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 698                 | ((cke_pls & 0x7) << 6)
 699                 | ((four_act & 0x3f) << 0)
 700                 );
 701         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 702 }
 703
 704 /* DDR SDRAM Register Control Word */
 705 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 706                                const memctl_options_t *popts,
 707                                const common_timing_params_t *common_dimm)
 708 {
 709         if (common_dimm->all_dimms_registered &&
 710             !common_dimm->all_dimms_unbuffered) {
 711                 if (popts->rcw_override) {
 712                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 713                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 714                 } else {
 715                         ddr->ddr_sdram_rcw_1 =
 716                                 common_dimm->rcw[0] << 28 | \
 717                                 common_dimm->rcw[1] << 24 | \
 718                                 common_dimm->rcw[2] << 20 | \
 719                                 common_dimm->rcw[3] << 16 | \
 720                                 common_dimm->rcw[4] << 12 | \
 721                                 common_dimm->rcw[5] << 8 | \
 722                                 common_dimm->rcw[6] << 4 | \
 723                                 common_dimm->rcw[7];
 724                         ddr->ddr_sdram_rcw_2 =
 725                                 common_dimm->rcw[8] << 28 | \
 726                                 common_dimm->rcw[9] << 24 | \
 727                                 common_dimm->rcw[10] << 20 | \
 728                                 common_dimm->rcw[11] << 16 | \
 729                                 common_dimm->rcw[12] << 12 | \
 730                                 common_dimm->rcw[13] << 8 | \
 731                                 common_dimm->rcw[14] << 4 | \
 732                                 common_dimm->rcw[15];
 733                 }
 734                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 735                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 736         }
 737 }
 738
 739 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 740 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 741                                const memctl_options_t *popts,
 742                                const common_timing_params_t *common_dimm)
 743 {
 744         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 745         unsigned int sren;              /* Self refresh enable (during sleep) */
 746         unsigned int ecc_en;            /* ECC enable. */
 747         unsigned int rd_en;             /* Registered DIMM enable */
 748         unsigned int sdram_type;        /* Type of SDRAM */
 749         unsigned int dyn_pwr;           /* Dynamic power management mode */
 750         unsigned int dbw;               /* DRAM dta bus width */
 751         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 752         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 753         unsigned int threet_en;         /* Enable 3T timing */
 754         unsigned int twot_en;           /* Enable 2T timing */
 755         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 756         unsigned int x32_en = 0;        /* x32 enable */
 757         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 758         unsigned int hse;               /* Global half strength override */
 759         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 760         unsigned int mem_halt = 0;      /* memory controller halt */
 761         unsigned int bi = 0;            /* Bypass initialization */
 762
 763         mem_en = 1;
 764         sren = popts->self_refresh_in_sleep;
 765         if (common_dimm->all_dimms_ecc_capable) {
 766                 /* Allow setting of ECC only if all DIMMs are ECC. */
 767                 ecc_en = popts->ecc_mode;
 768         } else {
 769                 ecc_en = 0;
 770         }
 771
 772         if (common_dimm->all_dimms_registered &&
 773             !common_dimm->all_dimms_unbuffered) {
 774                 rd_en = 1;
 775                 twot_en = 0;
 776         } else {
 777                 rd_en = 0;
 778                 twot_en = popts->twot_en;
 779         }
 780
 781         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 782
 783         dyn_pwr = popts->dynamic_power;
 784         dbw = popts->data_bus_width;
 785         /* 8-beat burst enable DDR-III case
 786          * we must clear it when use the on-the-fly mode,
 787          * must set it when use the 32-bits bus mode.
 788          */
 789         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 790             (sdram_type == SDRAM_TYPE_DDR4)) {
 791                 if (popts->burst_length == DDR_BL8)
 792                         eight_be = 1;
 793                 if (popts->burst_length == DDR_OTF)
 794                         eight_be = 0;
 795                 if (dbw == 0x1)
 796                         eight_be = 1;
 797         }
 798
 799         threet_en = popts->threet_en;
 800         ba_intlv_ctl = popts->ba_intlv_ctl;
 801         hse = popts->half_strength_driver_enable;
 802
 803         /* set when ddr bus width < 64 */
 804         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 805
 806         ddr->ddr_sdram_cfg = (0
 807                         | ((mem_en & 0x1) << 31)
 808                         | ((sren & 0x1) << 30)
 809                         | ((ecc_en & 0x1) << 29)
 810                         | ((rd_en & 0x1) << 28)
 811                         | ((sdram_type & 0x7) << 24)
 812                         | ((dyn_pwr & 0x1) << 21)
 813                         | ((dbw & 0x3) << 19)
 814                         | ((eight_be & 0x1) << 18)
 815                         | ((ncap & 0x1) << 17)
 816                         | ((threet_en & 0x1) << 16)
 817                         | ((twot_en & 0x1) << 15)
 818                         | ((ba_intlv_ctl & 0x7F) << 8)
 819                         | ((x32_en & 0x1) << 5)
 820                         | ((pchb8 & 0x1) << 4)
 821                         | ((hse & 0x1) << 3)
 822                         | ((acc_ecc_en & 0x1) << 2)
 823                         | ((mem_halt & 0x1) << 1)
 824                         | ((bi & 0x1) << 0)
 825                         );
 826         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 827 }
 828
 829 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 830 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 831                                fsl_ddr_cfg_regs_t *ddr,
 832                                const memctl_options_t *popts,
 833                                const unsigned int unq_mrs_en)
 834 {
 835         unsigned int frc_sr = 0;        /* Force self refresh */
 836         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 837         unsigned int odt_cfg = 0;       /* ODT configuration */
 838         unsigned int num_pr;            /* Number of posted refreshes */
 839         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 840         unsigned int x4_en = 0;         /* x4 DRAM enable */
 841         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 842         unsigned int ap_en;             /* Address Parity Enable */
 843         unsigned int d_init;            /* DRAM data initialization */
 844         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 845         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 846         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 847         int i;
 848 #ifndef CONFIG_SYS_FSL_DDR4
 849         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 850         unsigned int dqs_cfg;           /* DQS configuration */
 851
 852         dqs_cfg = popts->dqs_config;
 853 #endif
 854         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 855                 if (popts->cs_local_opts[i].odt_rd_cfg
 856                         || popts->cs_local_opts[i].odt_wr_cfg) {
 857                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 858                         break;
 859                 }
 860         }
 861
 862         num_pr = 1;     /* Make this configurable */
 863
 864         /*
 865          * 8572 manual says
 866          *     {TIMING_CFG_1[PRETOACT]
 867          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 868          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 869          *      << DDR_SDRAM_INTERVAL[REFINT]
 870          */
 871 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 872         obc_cfg = popts->otf_burst_chop_en;
 873 #else
 874         obc_cfg = 0;
 875 #endif
 876
 877 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 878         slow = get_ddr_freq(ctrl_num) < 1249000000;
 879 #endif
 880
 881         if (popts->registered_dimm_en) {
 882                 rcw_en = 1;
 883                 ap_en = popts->ap_en;
 884         } else {
 885                 ap_en = 0;
 886         }
 887
 888         x4_en = popts->x4_en ? 1 : 0;
 889
 890 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 891         /* Use the DDR controller to auto initialize memory. */
 892         d_init = popts->ecc_init_using_memctl;
 893         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 894         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 895 #else
 896         /* Memory will be initialized via DMA, or not at all. */
 897         d_init = 0;
 898 #endif
 899
 900 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 901         md_en = popts->mirrored_dimm;
 902 #endif
 903         qd_en = popts->quad_rank_present ? 1 : 0;
 904         ddr->ddr_sdram_cfg_2 = (0
 905                 | ((frc_sr & 0x1) << 31)
 906                 | ((sr_ie & 0x1) << 30)
 907 #ifndef CONFIG_SYS_FSL_DDR4
 908                 | ((dll_rst_dis & 0x1) << 29)
 909                 | ((dqs_cfg & 0x3) << 26)
 910 #endif
 911                 | ((odt_cfg & 0x3) << 21)
 912                 | ((num_pr & 0xf) << 12)
 913                 | ((slow & 1) << 11)
 914                 | (x4_en << 10)
 915                 | (qd_en << 9)
 916                 | (unq_mrs_en << 8)
 917                 | ((obc_cfg & 0x1) << 6)
 918                 | ((ap_en & 0x1) << 5)
 919                 | ((d_init & 0x1) << 4)
 920                 | ((rcw_en & 0x1) << 2)
 921                 | ((md_en & 0x1) << 0)
 922                 );
 923         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 924 }
 925
 926 #ifdef CONFIG_SYS_FSL_DDR4
 927 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 928 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 929                                 fsl_ddr_cfg_regs_t *ddr,
 930                                 const memctl_options_t *popts,
 931                                 const common_timing_params_t *common_dimm,
 932                                 const unsigned int unq_mrs_en)
 933 {
 934         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 935         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 936         int i;
 937         unsigned int wr_crc = 0;        /* Disable */
 938         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 939         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 940         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 941         unsigned int mpr = 0;   /* serial */
 942         unsigned int wc_lat;
 943         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 944
 945         if (popts->rtt_override)
 946                 rtt_wr = popts->rtt_wr_override_value;
 947         else
 948                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 949
 950         if (common_dimm->extended_op_srt)
 951                 srt = common_dimm->extended_op_srt;
 952
 953         esdmode2 = (0
 954                 | ((wr_crc & 0x1) << 12)
 955                 | ((rtt_wr & 0x3) << 9)
 956                 | ((srt & 0x3) << 6)
 957                 | ((cwl & 0x7) << 3));
 958
 959         if (mclk_ps >= 1250)
 960                 wc_lat = 0;
 961         else if (mclk_ps >= 833)
 962                 wc_lat = 1;
 963         else
 964                 wc_lat = 2;
 965
 966         esdmode3 = (0
 967                 | ((mpr & 0x3) << 11)
 968                 | ((wc_lat & 0x3) << 9));
 969
 970         ddr->ddr_sdram_mode_2 = (0
 971                                  | ((esdmode2 & 0xFFFF) << 16)
 972                                  | ((esdmode3 & 0xFFFF) << 0)
 973                                  );
 974         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 975
 976         if (unq_mrs_en) {       /* unique mode registers are supported */
 977                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 978                         if (popts->rtt_override)
 979                                 rtt_wr = popts->rtt_wr_override_value;
 980                         else
 981                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 982
 983                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
 984                         esdmode2 |= (rtt_wr & 0x3) << 9;
 985                         switch (i) {
 986                         case 1:
 987                                 ddr->ddr_sdram_mode_4 = (0
 988                                         | ((esdmode2 & 0xFFFF) << 16)
 989                                         | ((esdmode3 & 0xFFFF) << 0)
 990                                         );
 991                                 break;
 992                         case 2:
 993                                 ddr->ddr_sdram_mode_6 = (0
 994                                         | ((esdmode2 & 0xFFFF) << 16)
 995                                         | ((esdmode3 & 0xFFFF) << 0)
 996                                         );
 997                                 break;
 998                         case 3:
 999                                 ddr->ddr_sdram_mode_8 = (0
1000                                         | ((esdmode2 & 0xFFFF) << 16)
1001                                         | ((esdmode3 & 0xFFFF) << 0)
1002                                         );
1003                                 break;
1004                         }
1005                 }
1006                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1007                       ddr->ddr_sdram_mode_4);
1008                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1009                       ddr->ddr_sdram_mode_6);
1010                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1011                       ddr->ddr_sdram_mode_8);
1012         }
1013 }
1014 #elif defined(CONFIG_SYS_FSL_DDR3)
1015 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1016 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1017                                 fsl_ddr_cfg_regs_t *ddr,
1018                                 const memctl_options_t *popts,
1019                                 const common_timing_params_t *common_dimm,
1020                                 const unsigned int unq_mrs_en)
1021 {
1022         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1023         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1024         int i;
1025         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1026         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1027         unsigned int asr = 0;   /* auto self-refresh disable */
1028         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1029         unsigned int pasr = 0;  /* partial array self refresh disable */
1030
1031         if (popts->rtt_override)
1032                 rtt_wr = popts->rtt_wr_override_value;
1033         else
1034                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1035
1036         if (common_dimm->extended_op_srt)
1037                 srt = common_dimm->extended_op_srt;
1038
1039         esdmode2 = (0
1040                 | ((rtt_wr & 0x3) << 9)
1041                 | ((srt & 0x1) << 7)
1042                 | ((asr & 0x1) << 6)
1043                 | ((cwl & 0x7) << 3)
1044                 | ((pasr & 0x7) << 0));
1045         ddr->ddr_sdram_mode_2 = (0
1046                                  | ((esdmode2 & 0xFFFF) << 16)
1047                                  | ((esdmode3 & 0xFFFF) << 0)
1048                                  );
1049         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1050
1051         if (unq_mrs_en) {       /* unique mode registers are supported */
1052                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1053                         if (popts->rtt_override)
1054                                 rtt_wr = popts->rtt_wr_override_value;
1055                         else
1056                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1057
1058                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1059                         esdmode2 |= (rtt_wr & 0x3) << 9;
1060                         switch (i) {
1061                         case 1:
1062                                 ddr->ddr_sdram_mode_4 = (0
1063                                         | ((esdmode2 & 0xFFFF) << 16)
1064                                         | ((esdmode3 & 0xFFFF) << 0)
1065                                         );
1066                                 break;
1067                         case 2:
1068                                 ddr->ddr_sdram_mode_6 = (0
1069                                         | ((esdmode2 & 0xFFFF) << 16)
1070                                         | ((esdmode3 & 0xFFFF) << 0)
1071                                         );
1072                                 break;
1073                         case 3:
1074                                 ddr->ddr_sdram_mode_8 = (0
1075                                         | ((esdmode2 & 0xFFFF) << 16)
1076                                         | ((esdmode3 & 0xFFFF) << 0)
1077                                         );
1078                                 break;
1079                         }
1080                 }
1081                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1082                         ddr->ddr_sdram_mode_4);
1083                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1084                         ddr->ddr_sdram_mode_6);
1085                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1086                         ddr->ddr_sdram_mode_8);
1087         }
1088 }
1089
1090 #else /* for DDR2 and DDR1 */
1091 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1092 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1093                                 fsl_ddr_cfg_regs_t *ddr,
1094                                 const memctl_options_t *popts,
1095                                 const common_timing_params_t *common_dimm,
1096                                 const unsigned int unq_mrs_en)
1097 {
1098         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1099         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1100
1101         ddr->ddr_sdram_mode_2 = (0
1102                                  | ((esdmode2 & 0xFFFF) << 16)
1103                                  | ((esdmode3 & 0xFFFF) << 0)
1104                                  );
1105         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1106 }
1107 #endif
1108
1109 #ifdef CONFIG_SYS_FSL_DDR4
1110 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1111 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1112                                 const memctl_options_t *popts,
1113                                 const common_timing_params_t *common_dimm,
1114                                 const unsigned int unq_mrs_en)
1115 {
1116         int i;
1117         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1118         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1119
1120         esdmode5 = 0x00000500;          /* Data mask enabled */
1121
1122         ddr->ddr_sdram_mode_9 = (0
1123                                  | ((esdmode4 & 0xffff) << 16)
1124                                  | ((esdmode5 & 0xffff) << 0)
1125                                 );
1126
1127         /* only mode_9 use 0x500, others use 0x400 */
1128         esdmode5 = 0x00000400;          /* Data mask enabled */
1129
1130         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1131         if (unq_mrs_en) {       /* unique mode registers are supported */
1132                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1133                         switch (i) {
1134                         case 1:
1135                                 ddr->ddr_sdram_mode_11 = (0
1136                                         | ((esdmode4 & 0xFFFF) << 16)
1137                                         | ((esdmode5 & 0xFFFF) << 0)
1138                                         );
1139                                 break;
1140                         case 2:
1141                                 ddr->ddr_sdram_mode_13 = (0
1142                                         | ((esdmode4 & 0xFFFF) << 16)
1143                                         | ((esdmode5 & 0xFFFF) << 0)
1144                                         );
1145                                 break;
1146                         case 3:
1147                                 ddr->ddr_sdram_mode_15 = (0
1148                                         | ((esdmode4 & 0xFFFF) << 16)
1149                                         | ((esdmode5 & 0xFFFF) << 0)
1150                                         );
1151                                 break;
1152                         }
1153                 }
1154                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1155                       ddr->ddr_sdram_mode_11);
1156                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1157                       ddr->ddr_sdram_mode_13);
1158                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1159                       ddr->ddr_sdram_mode_15);
1160         }
1161 }
1162
1163 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1164 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1165                                 fsl_ddr_cfg_regs_t *ddr,
1166                                 const memctl_options_t *popts,
1167                                 const common_timing_params_t *common_dimm,
1168                                 const unsigned int unq_mrs_en)
1169 {
1170         int i;
1171         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1172         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1173         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1174
1175         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1176
1177         ddr->ddr_sdram_mode_10 = (0
1178                                  | ((esdmode6 & 0xffff) << 16)
1179                                  | ((esdmode7 & 0xffff) << 0)
1180                                 );
1181         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1182         if (unq_mrs_en) {       /* unique mode registers are supported */
1183                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1184                         switch (i) {
1185                         case 1:
1186                                 ddr->ddr_sdram_mode_12 = (0
1187                                         | ((esdmode6 & 0xFFFF) << 16)
1188                                         | ((esdmode7 & 0xFFFF) << 0)
1189                                         );
1190                                 break;
1191                         case 2:
1192                                 ddr->ddr_sdram_mode_14 = (0
1193                                         | ((esdmode6 & 0xFFFF) << 16)
1194                                         | ((esdmode7 & 0xFFFF) << 0)
1195                                         );
1196                                 break;
1197                         case 3:
1198                                 ddr->ddr_sdram_mode_16 = (0
1199                                         | ((esdmode6 & 0xFFFF) << 16)
1200                                         | ((esdmode7 & 0xFFFF) << 0)
1201                                         );
1202                                 break;
1203                         }
1204                 }
1205                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1206                       ddr->ddr_sdram_mode_12);
1207                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1208                       ddr->ddr_sdram_mode_14);
1209                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1210                       ddr->ddr_sdram_mode_16);
1211         }
1212 }
1213
1214 #endif
1215
1216 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1217 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1218                                 fsl_ddr_cfg_regs_t *ddr,
1219                                 const memctl_options_t *popts,
1220                                 const common_timing_params_t *common_dimm)
1221 {
1222         unsigned int refint;    /* Refresh interval */
1223         unsigned int bstopre;   /* Precharge interval */
1224
1225         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1226
1227         bstopre = popts->bstopre;
1228
1229         /* refint field used 0x3FFF in earlier controllers */
1230         ddr->ddr_sdram_interval = (0
1231                                    | ((refint & 0xFFFF) << 16)
1232                                    | ((bstopre & 0x3FFF) << 0)
1233                                    );
1234         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1235 }
1236
1237 #ifdef CONFIG_SYS_FSL_DDR4
1238 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1239 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1240                                fsl_ddr_cfg_regs_t *ddr,
1241                                const memctl_options_t *popts,
1242                                const common_timing_params_t *common_dimm,
1243                                unsigned int cas_latency,
1244                                unsigned int additive_latency,
1245                                const unsigned int unq_mrs_en)
1246 {
1247         int i;
1248         unsigned short esdmode;         /* Extended SDRAM mode */
1249         unsigned short sdmode;          /* SDRAM mode */
1250
1251         /* Mode Register - MR1 */
1252         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1253         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1254         unsigned int rtt;
1255         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1256         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1257         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1258         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1259                                                        0=Disable (Test/Debug) */
1260
1261         /* Mode Register - MR0 */
1262         unsigned int wr = 0;    /* Write Recovery */
1263         unsigned int dll_rst;   /* DLL Reset */
1264         unsigned int mode;      /* Normal=0 or Test=1 */
1265         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1266         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1267         unsigned int bt;
1268         unsigned int bl;        /* BL: Burst Length */
1269
1270         unsigned int wr_mclk;
1271         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1272         static const u8 wr_table[] = {
1273                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1274         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1275         static const u8 cas_latency_table[] = {
1276                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1277                 9, 9, 10, 10, 11, 11};
1278
1279         if (popts->rtt_override)
1280                 rtt = popts->rtt_override_value;
1281         else
1282                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1283
1284         if (additive_latency == (cas_latency - 1))
1285                 al = 1;
1286         if (additive_latency == (cas_latency - 2))
1287                 al = 2;
1288
1289         if (popts->quad_rank_present)
1290                 dic = 1;        /* output driver impedance 240/7 ohm */
1291
1292         /*
1293          * The esdmode value will also be used for writing
1294          * MR1 during write leveling for DDR3, although the
1295          * bits specifically related to the write leveling
1296          * scheme will be handled automatically by the DDR
1297          * controller. so we set the wrlvl_en = 0 here.
1298          */
1299         esdmode = (0
1300                 | ((qoff & 0x1) << 12)
1301                 | ((tdqs_en & 0x1) << 11)
1302                 | ((rtt & 0x7) << 8)
1303                 | ((wrlvl_en & 0x1) << 7)
1304                 | ((al & 0x3) << 3)
1305                 | ((dic & 0x3) << 1)   /* DIC field is split */
1306                 | ((dll_en & 0x1) << 0)
1307                 );
1308
1309         /*
1310          * DLL control for precharge PD
1311          * 0=slow exit DLL off (tXPDLL)
1312          * 1=fast exit DLL on (tXP)
1313          */
1314
1315         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1316         if (wr_mclk <= 24) {
1317                 wr = wr_table[wr_mclk - 10];
1318         } else {
1319                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1320                        wr_mclk);
1321         }
1322
1323         dll_rst = 0;    /* dll no reset */
1324         mode = 0;       /* normal mode */
1325
1326         /* look up table to get the cas latency bits */
1327         if (cas_latency >= 9 && cas_latency <= 24)
1328                 caslat = cas_latency_table[cas_latency - 9];
1329         else
1330                 printf("Error: unsupported cas latency for mode register\n");
1331
1332         bt = 0; /* Nibble sequential */
1333
1334         switch (popts->burst_length) {
1335         case DDR_BL8:
1336                 bl = 0;
1337                 break;
1338         case DDR_OTF:
1339                 bl = 1;
1340                 break;
1341         case DDR_BC4:
1342                 bl = 2;
1343                 break;
1344         default:
1345                 printf("Error: invalid burst length of %u specified. ",
1346                        popts->burst_length);
1347                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1348                 bl = 1;
1349                 break;
1350         }
1351
1352         sdmode = (0
1353                   | ((wr & 0x7) << 9)
1354                   | ((dll_rst & 0x1) << 8)
1355                   | ((mode & 0x1) << 7)
1356                   | (((caslat >> 1) & 0x7) << 4)
1357                   | ((bt & 0x1) << 3)
1358                   | ((caslat & 1) << 2)
1359                   | ((bl & 0x3) << 0)
1360                   );
1361
1362         ddr->ddr_sdram_mode = (0
1363                                | ((esdmode & 0xFFFF) << 16)
1364                                | ((sdmode & 0xFFFF) << 0)
1365                                );
1366
1367         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1368
1369         if (unq_mrs_en) {       /* unique mode registers are supported */
1370                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1371                         if (popts->rtt_override)
1372                                 rtt = popts->rtt_override_value;
1373                         else
1374                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1375
1376                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1377                         esdmode |= (rtt & 0x7) << 8;
1378                         switch (i) {
1379                         case 1:
1380                                 ddr->ddr_sdram_mode_3 = (0
1381                                        | ((esdmode & 0xFFFF) << 16)
1382                                        | ((sdmode & 0xFFFF) << 0)
1383                                        );
1384                                 break;
1385                         case 2:
1386                                 ddr->ddr_sdram_mode_5 = (0
1387                                        | ((esdmode & 0xFFFF) << 16)
1388                                        | ((sdmode & 0xFFFF) << 0)
1389                                        );
1390                                 break;
1391                         case 3:
1392                                 ddr->ddr_sdram_mode_7 = (0
1393                                        | ((esdmode & 0xFFFF) << 16)
1394                                        | ((sdmode & 0xFFFF) << 0)
1395                                        );
1396                                 break;
1397                         }
1398                 }
1399                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1400                       ddr->ddr_sdram_mode_3);
1401                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1402                       ddr->ddr_sdram_mode_5);
1403                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1404                       ddr->ddr_sdram_mode_5);
1405         }
1406 }
1407
1408 #elif defined(CONFIG_SYS_FSL_DDR3)
1409 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1410 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1411                                fsl_ddr_cfg_regs_t *ddr,
1412                                const memctl_options_t *popts,
1413                                const common_timing_params_t *common_dimm,
1414                                unsigned int cas_latency,
1415                                unsigned int additive_latency,
1416                                const unsigned int unq_mrs_en)
1417 {
1418         int i;
1419         unsigned short esdmode;         /* Extended SDRAM mode */
1420         unsigned short sdmode;          /* SDRAM mode */
1421
1422         /* Mode Register - MR1 */
1423         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1424         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1425         unsigned int rtt;
1426         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1427         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1428         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1429         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1430                                                        1=Disable (Test/Debug) */
1431
1432         /* Mode Register - MR0 */
1433         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1434         unsigned int wr = 0;    /* Write Recovery */
1435         unsigned int dll_rst;   /* DLL Reset */
1436         unsigned int mode;      /* Normal=0 or Test=1 */
1437         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1438         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1439         unsigned int bt;
1440         unsigned int bl;        /* BL: Burst Length */
1441
1442         unsigned int wr_mclk;
1443         /*
1444          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1445          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1446          * for this table
1447          */
1448         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1449
1450         if (popts->rtt_override)
1451                 rtt = popts->rtt_override_value;
1452         else
1453                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1454
1455         if (additive_latency == (cas_latency - 1))
1456                 al = 1;
1457         if (additive_latency == (cas_latency - 2))
1458                 al = 2;
1459
1460         if (popts->quad_rank_present)
1461                 dic = 1;        /* output driver impedance 240/7 ohm */
1462
1463         /*
1464          * The esdmode value will also be used for writing
1465          * MR1 during write leveling for DDR3, although the
1466          * bits specifically related to the write leveling
1467          * scheme will be handled automatically by the DDR
1468          * controller. so we set the wrlvl_en = 0 here.
1469          */
1470         esdmode = (0
1471                 | ((qoff & 0x1) << 12)
1472                 | ((tdqs_en & 0x1) << 11)
1473                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1474                 | ((wrlvl_en & 0x1) << 7)
1475                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1476                 | ((dic & 0x2) << 4)   /* DIC field is split */
1477                 | ((al & 0x3) << 3)
1478                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1479                 | ((dic & 0x1) << 1)   /* DIC field is split */
1480                 | ((dll_en & 0x1) << 0)
1481                 );
1482
1483         /*
1484          * DLL control for precharge PD
1485          * 0=slow exit DLL off (tXPDLL)
1486          * 1=fast exit DLL on (tXP)
1487          */
1488         dll_on = 1;
1489
1490         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1491         if (wr_mclk <= 16) {
1492                 wr = wr_table[wr_mclk - 5];
1493         } else {
1494                 printf("Error: unsupported write recovery for mode register "
1495                        "wr_mclk = %d\n", wr_mclk);
1496         }
1497
1498         dll_rst = 0;    /* dll no reset */
1499         mode = 0;       /* normal mode */
1500
1501         /* look up table to get the cas latency bits */
1502         if (cas_latency >= 5 && cas_latency <= 16) {
1503                 unsigned char cas_latency_table[] = {
1504                         0x2,    /* 5 clocks */
1505                         0x4,    /* 6 clocks */
1506                         0x6,    /* 7 clocks */
1507                         0x8,    /* 8 clocks */
1508                         0xa,    /* 9 clocks */
1509                         0xc,    /* 10 clocks */
1510                         0xe,    /* 11 clocks */
1511                         0x1,    /* 12 clocks */
1512                         0x3,    /* 13 clocks */
1513                         0x5,    /* 14 clocks */
1514                         0x7,    /* 15 clocks */
1515                         0x9,    /* 16 clocks */
1516                 };
1517                 caslat = cas_latency_table[cas_latency - 5];
1518         } else {
1519                 printf("Error: unsupported cas latency for mode register\n");
1520         }
1521
1522         bt = 0; /* Nibble sequential */
1523
1524         switch (popts->burst_length) {
1525         case DDR_BL8:
1526                 bl = 0;
1527                 break;
1528         case DDR_OTF:
1529                 bl = 1;
1530                 break;
1531         case DDR_BC4:
1532                 bl = 2;
1533                 break;
1534         default:
1535                 printf("Error: invalid burst length of %u specified. "
1536                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1537                         popts->burst_length);
1538                 bl = 1;
1539                 break;
1540         }
1541
1542         sdmode = (0
1543                   | ((dll_on & 0x1) << 12)
1544                   | ((wr & 0x7) << 9)
1545                   | ((dll_rst & 0x1) << 8)
1546                   | ((mode & 0x1) << 7)
1547                   | (((caslat >> 1) & 0x7) << 4)
1548                   | ((bt & 0x1) << 3)
1549                   | ((caslat & 1) << 2)
1550                   | ((bl & 0x3) << 0)
1551                   );
1552
1553         ddr->ddr_sdram_mode = (0
1554                                | ((esdmode & 0xFFFF) << 16)
1555                                | ((sdmode & 0xFFFF) << 0)
1556                                );
1557
1558         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1559
1560         if (unq_mrs_en) {       /* unique mode registers are supported */
1561                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1562                         if (popts->rtt_override)
1563                                 rtt = popts->rtt_override_value;
1564                         else
1565                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1566
1567                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1568                         esdmode |= (0
1569                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1570                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1571                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1572                                 );
1573                         switch (i) {
1574                         case 1:
1575                                 ddr->ddr_sdram_mode_3 = (0
1576                                        | ((esdmode & 0xFFFF) << 16)
1577                                        | ((sdmode & 0xFFFF) << 0)
1578                                        );
1579                                 break;
1580                         case 2:
1581                                 ddr->ddr_sdram_mode_5 = (0
1582                                        | ((esdmode & 0xFFFF) << 16)
1583                                        | ((sdmode & 0xFFFF) << 0)
1584                                        );
1585                                 break;
1586                         case 3:
1587                                 ddr->ddr_sdram_mode_7 = (0
1588                                        | ((esdmode & 0xFFFF) << 16)
1589                                        | ((sdmode & 0xFFFF) << 0)
1590                                        );
1591                                 break;
1592                         }
1593                 }
1594                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1595                         ddr->ddr_sdram_mode_3);
1596                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1597                         ddr->ddr_sdram_mode_5);
1598                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1599                         ddr->ddr_sdram_mode_5);
1600         }
1601 }
1602
1603 #else /* !CONFIG_SYS_FSL_DDR3 */
1604
1605 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1606 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1607                                fsl_ddr_cfg_regs_t *ddr,
1608                                const memctl_options_t *popts,
1609                                const common_timing_params_t *common_dimm,
1610                                unsigned int cas_latency,
1611                                unsigned int additive_latency,
1612                                const unsigned int unq_mrs_en)
1613 {
1614         unsigned short esdmode;         /* Extended SDRAM mode */
1615         unsigned short sdmode;          /* SDRAM mode */
1616
1617         /*
1618          * FIXME: This ought to be pre-calculated in a
1619          * technology-specific routine,
1620          * e.g. compute_DDR2_mode_register(), and then the
1621          * sdmode and esdmode passed in as part of common_dimm.
1622          */
1623
1624         /* Extended Mode Register */
1625         unsigned int mrs = 0;           /* Mode Register Set */
1626         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1627         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1628         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1629         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1630                                            0x7=OCD default state */
1631         unsigned int rtt;
1632         unsigned int al;                /* Posted CAS# additive latency (AL) */
1633         unsigned int ods = 0;           /* Output Drive Strength:
1634                                                 0 = Full strength (18ohm)
1635                                                 1 = Reduced strength (4ohm) */
1636         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1637                                                        1=Disable (Test/Debug) */
1638
1639         /* Mode Register (MR) */
1640         unsigned int mr;        /* Mode Register Definition */
1641         unsigned int pd;        /* Power-Down Mode */
1642         unsigned int wr;        /* Write Recovery */
1643         unsigned int dll_res;   /* DLL Reset */
1644         unsigned int mode;      /* Normal=0 or Test=1 */
1645         unsigned int caslat = 0;/* CAS# latency */
1646         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1647         unsigned int bt;
1648         unsigned int bl;        /* BL: Burst Length */
1649
1650         dqs_en = !popts->dqs_config;
1651         rtt = fsl_ddr_get_rtt();
1652
1653         al = additive_latency;
1654
1655         esdmode = (0
1656                 | ((mrs & 0x3) << 14)
1657                 | ((outputs & 0x1) << 12)
1658                 | ((rdqs_en & 0x1) << 11)
1659                 | ((dqs_en & 0x1) << 10)
1660                 | ((ocd & 0x7) << 7)
1661                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1662                 | ((al & 0x7) << 3)
1663                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1664                 | ((ods & 0x1) << 1)
1665                 | ((dll_en & 0x1) << 0)
1666                 );
1667
1668         mr = 0;          /* FIXME: CHECKME */
1669
1670         /*
1671          * 0 = Fast Exit (Normal)
1672          * 1 = Slow Exit (Low Power)
1673          */
1674         pd = 0;
1675
1676 #if defined(CONFIG_SYS_FSL_DDR1)
1677         wr = 0;       /* Historical */
1678 #elif defined(CONFIG_SYS_FSL_DDR2)
1679         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1680 #endif
1681         dll_res = 0;
1682         mode = 0;
1683
1684 #if defined(CONFIG_SYS_FSL_DDR1)
1685         if (1 <= cas_latency && cas_latency <= 4) {
1686                 unsigned char mode_caslat_table[4] = {
1687                         0x5,    /* 1.5 clocks */
1688                         0x2,    /* 2.0 clocks */
1689                         0x6,    /* 2.5 clocks */
1690                         0x3     /* 3.0 clocks */
1691                 };
1692                 caslat = mode_caslat_table[cas_latency - 1];
1693         } else {
1694                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1695         }
1696 #elif defined(CONFIG_SYS_FSL_DDR2)
1697         caslat = cas_latency;
1698 #endif
1699         bt = 0;
1700
1701         switch (popts->burst_length) {
1702         case DDR_BL4:
1703                 bl = 2;
1704                 break;
1705         case DDR_BL8:
1706                 bl = 3;
1707                 break;
1708         default:
1709                 printf("Error: invalid burst length of %u specified. "
1710                         " Defaulting to 4 beats.\n",
1711                         popts->burst_length);
1712                 bl = 2;
1713                 break;
1714         }
1715
1716         sdmode = (0
1717                   | ((mr & 0x3) << 14)
1718                   | ((pd & 0x1) << 12)
1719                   | ((wr & 0x7) << 9)
1720                   | ((dll_res & 0x1) << 8)
1721                   | ((mode & 0x1) << 7)
1722                   | ((caslat & 0x7) << 4)
1723                   | ((bt & 0x1) << 3)
1724                   | ((bl & 0x7) << 0)
1725                   );
1726
1727         ddr->ddr_sdram_mode = (0
1728                                | ((esdmode & 0xFFFF) << 16)
1729                                | ((sdmode & 0xFFFF) << 0)
1730                                );
1731         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1732 }
1733 #endif
1734
1735 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1736 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1737 {
1738         unsigned int init_value;        /* Initialization value */
1739
1740 #ifdef CONFIG_MEM_INIT_VALUE
1741         init_value = CONFIG_MEM_INIT_VALUE;
1742 #else
1743         init_value = 0xDEADBEEF;
1744 #endif
1745         ddr->ddr_data_init = init_value;
1746 }
1747
1748 /*
1749  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1750  * The old controller on the 8540/60 doesn't have this register.
1751  * Hope it's OK to set it (to 0) anyway.
1752  */
1753 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1754                                          const memctl_options_t *popts)
1755 {
1756         unsigned int clk_adjust;        /* Clock adjust */
1757         unsigned int ss_en = 0;         /* Source synchronous enable */
1758
1759 #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1760         /* Per FSL Application Note: AN2805 */
1761         ss_en = 1;
1762 #endif
1763         clk_adjust = popts->clk_adjust;
1764         ddr->ddr_sdram_clk_cntl = (0
1765                                    | ((ss_en & 0x1) << 31)
1766                                    | ((clk_adjust & 0xF) << 23)
1767                                    );
1768         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1769 }
1770
1771 /* DDR Initialization Address (DDR_INIT_ADDR) */
1772 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1773 {
1774         unsigned int init_addr = 0;     /* Initialization address */
1775
1776         ddr->ddr_init_addr = init_addr;
1777 }
1778
1779 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1780 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1781 {
1782         unsigned int uia = 0;   /* Use initialization address */
1783         unsigned int init_ext_addr = 0; /* Initialization address */
1784
1785         ddr->ddr_init_ext_addr = (0
1786                                   | ((uia & 0x1) << 31)
1787                                   | (init_ext_addr & 0xF)
1788                                   );
1789 }
1790
1791 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1792 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1793                                 const memctl_options_t *popts)
1794 {
1795         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1796         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1797         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1798         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1799         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1800
1801 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1802         if (popts->burst_length == DDR_BL8) {
1803                 /* We set BL/2 for fixed BL8 */
1804                 rrt = 0;        /* BL/2 clocks */
1805                 wwt = 0;        /* BL/2 clocks */
1806         } else {
1807                 /* We need to set BL/2 + 2 to BC4 and OTF */
1808                 rrt = 2;        /* BL/2 + 2 clocks */
1809                 wwt = 2;        /* BL/2 + 2 clocks */
1810         }
1811 #endif
1812
1813 #ifdef CONFIG_SYS_FSL_DDR4
1814         dll_lock = 2;   /* tDLLK = 1024 clocks */
1815 #elif defined(CONFIG_SYS_FSL_DDR3)
1816         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1817 #endif
1818         ddr->timing_cfg_4 = (0
1819                              | ((rwt & 0xf) << 28)
1820                              | ((wrt & 0xf) << 24)
1821                              | ((rrt & 0xf) << 20)
1822                              | ((wwt & 0xf) << 16)
1823                              | (dll_lock & 0x3)
1824                              );
1825         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1826 }
1827
1828 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1829 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1830 {
1831         unsigned int rodt_on = 0;       /* Read to ODT on */
1832         unsigned int rodt_off = 0;      /* Read to ODT off */
1833         unsigned int wodt_on = 0;       /* Write to ODT on */
1834         unsigned int wodt_off = 0;      /* Write to ODT off */
1835
1836 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1837         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1838                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1839         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1840         if (cas_latency >= wr_lat)
1841                 rodt_on = cas_latency - wr_lat + 1;
1842         rodt_off = 4;   /*  4 clocks */
1843         wodt_on = 1;    /*  1 clocks */
1844         wodt_off = 4;   /*  4 clocks */
1845 #endif
1846
1847         ddr->timing_cfg_5 = (0
1848                              | ((rodt_on & 0x1f) << 24)
1849                              | ((rodt_off & 0x7) << 20)
1850                              | ((wodt_on & 0x1f) << 12)
1851                              | ((wodt_off & 0x7) << 8)
1852                              );
1853         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1854 }
1855
1856 #ifdef CONFIG_SYS_FSL_DDR4
1857 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1858 {
1859         unsigned int hs_caslat = 0;
1860         unsigned int hs_wrlat = 0;
1861         unsigned int hs_wrrec = 0;
1862         unsigned int hs_clkadj = 0;
1863         unsigned int hs_wrlvl_start = 0;
1864
1865         ddr->timing_cfg_6 = (0
1866                              | ((hs_caslat & 0x1f) << 24)
1867                              | ((hs_wrlat & 0x1f) << 19)
1868                              | ((hs_wrrec & 0x1f) << 12)
1869                              | ((hs_clkadj & 0x1f) << 6)
1870                              | ((hs_wrlvl_start & 0x1f) << 0)
1871                             );
1872         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1873 }
1874
1875 static void set_timing_cfg_7(const unsigned int ctrl_num,
1876                              fsl_ddr_cfg_regs_t *ddr,
1877                              const common_timing_params_t *common_dimm)
1878 {
1879         unsigned int txpr, tcksre, tcksrx;
1880         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1881
1882         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1883         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1884         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1885         par_lat = 0;
1886         cs_to_cmd = 0;
1887
1888         if (txpr <= 200)
1889                 cke_rst = 0;
1890         else if (txpr <= 256)
1891                 cke_rst = 1;
1892         else if (txpr <= 512)
1893                 cke_rst = 2;
1894         else
1895                 cke_rst = 3;
1896
1897         if (tcksre <= 19)
1898                 cksre = tcksre - 5;
1899         else
1900                 cksre = 15;
1901
1902         if (tcksrx <= 19)
1903                 cksrx = tcksrx - 5;
1904         else
1905                 cksrx = 15;
1906
1907         ddr->timing_cfg_7 = (0
1908                              | ((cke_rst & 0x3) << 28)
1909                              | ((cksre & 0xf) << 24)
1910                              | ((cksrx & 0xf) << 20)
1911                              | ((par_lat & 0xf) << 16)
1912                              | ((cs_to_cmd & 0xf) << 4)
1913                             );
1914         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1915 }
1916
1917 static void set_timing_cfg_8(const unsigned int ctrl_num,
1918                              fsl_ddr_cfg_regs_t *ddr,
1919                              const memctl_options_t *popts,
1920                              const common_timing_params_t *common_dimm,
1921                              unsigned int cas_latency)
1922 {
1923         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1924         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1925         unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1926         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1927                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1928
1929         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1930         if (rwt_bg < tccdl)
1931                 rwt_bg = tccdl - rwt_bg;
1932         else
1933                 rwt_bg = 0;
1934
1935         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1936         if (wrt_bg < tccdl)
1937                 wrt_bg = tccdl - wrt_bg;
1938         else
1939                 wrt_bg = 0;
1940
1941         if (popts->burst_length == DDR_BL8) {
1942                 rrt_bg = tccdl - 4;
1943                 wwt_bg = tccdl - 4;
1944         } else {
1945                 rrt_bg = tccdl - 2;
1946                 wwt_bg = tccdl - 2;
1947         }
1948
1949         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1950         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
1951         if (popts->otf_burst_chop_en)
1952                 wrtord_bg += 2;
1953
1954         pre_all_rec = 0;
1955
1956         ddr->timing_cfg_8 = (0
1957                              | ((rwt_bg & 0xf) << 28)
1958                              | ((wrt_bg & 0xf) << 24)
1959                              | ((rrt_bg & 0xf) << 20)
1960                              | ((wwt_bg & 0xf) << 16)
1961                              | ((acttoact_bg & 0xf) << 12)
1962                              | ((wrtord_bg & 0xf) << 8)
1963                              | ((pre_all_rec & 0x1f) << 0)
1964                             );
1965
1966         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
1967 }
1968
1969 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
1970 {
1971         ddr->timing_cfg_9 = 0;
1972         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
1973 }
1974
1975 /* This function needs to be called after set_ddr_sdram_cfg() is called */
1976 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
1977                                const dimm_params_t *dimm_params)
1978 {
1979         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
1980
1981         ddr->dq_map_0 = ((dimm_params->dq_mapping[0] & 0x3F) << 26) |
1982                         ((dimm_params->dq_mapping[1] & 0x3F) << 20) |
1983                         ((dimm_params->dq_mapping[2] & 0x3F) << 14) |
1984                         ((dimm_params->dq_mapping[3] & 0x3F) << 8) |
1985                         ((dimm_params->dq_mapping[4] & 0x3F) << 2);
1986
1987         ddr->dq_map_1 = ((dimm_params->dq_mapping[5] & 0x3F) << 26) |
1988                         ((dimm_params->dq_mapping[6] & 0x3F) << 20) |
1989                         ((dimm_params->dq_mapping[7] & 0x3F) << 14) |
1990                         ((dimm_params->dq_mapping[10] & 0x3F) << 8) |
1991                         ((dimm_params->dq_mapping[11] & 0x3F) << 2);
1992
1993         ddr->dq_map_2 = ((dimm_params->dq_mapping[12] & 0x3F) << 26) |
1994                         ((dimm_params->dq_mapping[13] & 0x3F) << 20) |
1995                         ((dimm_params->dq_mapping[14] & 0x3F) << 14) |
1996                         ((dimm_params->dq_mapping[15] & 0x3F) << 8) |
1997                         ((dimm_params->dq_mapping[16] & 0x3F) << 2);
1998
1999         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2000         ddr->dq_map_3 = ((dimm_params->dq_mapping[17] & 0x3F) << 26) |
2001                         ((dimm_params->dq_mapping[8] & 0x3F) << 20) |
2002                         (acc_ecc_en ? 0 :
2003                          (dimm_params->dq_mapping[9] & 0x3F) << 14) |
2004                         dimm_params->dq_mapping_ors;
2005
2006         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2007         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2008         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2009         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2010 }
2011 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2012                                const memctl_options_t *popts)
2013 {
2014         int rd_pre;
2015
2016         rd_pre = popts->quad_rank_present ? 1 : 0;
2017
2018         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2019
2020         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2021 }
2022 #endif  /* CONFIG_SYS_FSL_DDR4 */
2023
2024 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2025 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2026 {
2027         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2028         /* Normal Operation Full Calibration Time (tZQoper) */
2029         unsigned int zqoper = 0;
2030         /* Normal Operation Short Calibration Time (tZQCS) */
2031         unsigned int zqcs = 0;
2032 #ifdef CONFIG_SYS_FSL_DDR4
2033         unsigned int zqcs_init;
2034 #endif
2035
2036         if (zq_en) {
2037 #ifdef CONFIG_SYS_FSL_DDR4
2038                 zqinit = 10;    /* 1024 clocks */
2039                 zqoper = 9;     /* 512 clocks */
2040                 zqcs = 7;       /* 128 clocks */
2041                 zqcs_init = 5;  /* 1024 refresh sequences */
2042 #else
2043                 zqinit = 9;     /* 512 clocks */
2044                 zqoper = 8;     /* 256 clocks */
2045                 zqcs = 6;       /* 64 clocks */
2046 #endif
2047         }
2048
2049         ddr->ddr_zq_cntl = (0
2050                             | ((zq_en & 0x1) << 31)
2051                             | ((zqinit & 0xF) << 24)
2052                             | ((zqoper & 0xF) << 16)
2053                             | ((zqcs & 0xF) << 8)
2054 #ifdef CONFIG_SYS_FSL_DDR4
2055                             | ((zqcs_init & 0xF) << 0)
2056 #endif
2057                             );
2058         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2059 }
2060
2061 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2062 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2063                                 const memctl_options_t *popts)
2064 {
2065         /*
2066          * First DQS pulse rising edge after margining mode
2067          * is programmed (tWL_MRD)
2068          */
2069         unsigned int wrlvl_mrd = 0;
2070         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2071         unsigned int wrlvl_odten = 0;
2072         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2073         unsigned int wrlvl_dqsen = 0;
2074         /* WRLVL_SMPL: Write leveling sample time */
2075         unsigned int wrlvl_smpl = 0;
2076         /* WRLVL_WLR: Write leveling repeition time */
2077         unsigned int wrlvl_wlr = 0;
2078         /* WRLVL_START: Write leveling start time */
2079         unsigned int wrlvl_start = 0;
2080
2081         /* suggest enable write leveling for DDR3 due to fly-by topology */
2082         if (wrlvl_en) {
2083                 /* tWL_MRD min = 40 nCK, we set it 64 */
2084                 wrlvl_mrd = 0x6;
2085                 /* tWL_ODTEN 128 */
2086                 wrlvl_odten = 0x7;
2087                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2088                 wrlvl_dqsen = 0x5;
2089                 /*
2090                  * Write leveling sample time at least need 6 clocks
2091                  * higher than tWLO to allow enough time for progagation
2092                  * delay and sampling the prime data bits.
2093                  */
2094                 wrlvl_smpl = 0xf;
2095                 /*
2096                  * Write leveling repetition time
2097                  * at least tWLO + 6 clocks clocks
2098                  * we set it 64
2099                  */
2100                 wrlvl_wlr = 0x6;
2101                 /*
2102                  * Write leveling start time
2103                  * The value use for the DQS_ADJUST for the first sample
2104                  * when write leveling is enabled. It probably needs to be
2105                  * overriden per platform.
2106                  */
2107                 wrlvl_start = 0x8;
2108                 /*
2109                  * Override the write leveling sample and start time
2110                  * according to specific board
2111                  */
2112                 if (popts->wrlvl_override) {
2113                         wrlvl_smpl = popts->wrlvl_sample;
2114                         wrlvl_start = popts->wrlvl_start;
2115                 }
2116         }
2117
2118         ddr->ddr_wrlvl_cntl = (0
2119                                | ((wrlvl_en & 0x1) << 31)
2120                                | ((wrlvl_mrd & 0x7) << 24)
2121                                | ((wrlvl_odten & 0x7) << 20)
2122                                | ((wrlvl_dqsen & 0x7) << 16)
2123                                | ((wrlvl_smpl & 0xf) << 12)
2124                                | ((wrlvl_wlr & 0x7) << 8)
2125                                | ((wrlvl_start & 0x1F) << 0)
2126                                );
2127         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2128         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2129         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2130         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2131         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2132
2133 }
2134
2135 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2136 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2137 {
2138         /* Self Refresh Idle Threshold */
2139         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2140 }
2141
2142 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2143 {
2144         if (popts->addr_hash) {
2145                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2146                 puts("Address hashing enabled.\n");
2147         }
2148 }
2149
2150 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2151 {
2152         ddr->ddr_cdr1 = popts->ddr_cdr1;
2153         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2154 }
2155
2156 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2157 {
2158         ddr->ddr_cdr2 = popts->ddr_cdr2;
2159         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2160 }
2161
2162 unsigned int
2163 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2164 {
2165         unsigned int res = 0;
2166
2167         /*
2168          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2169          * not set at the same time.
2170          */
2171         if (ddr->ddr_sdram_cfg & 0x10000000
2172             && ddr->ddr_sdram_cfg & 0x00008000) {
2173                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2174                                 " should not be set at the same time.\n");
2175                 res++;
2176         }
2177
2178         return res;
2179 }
2180
2181 unsigned int
2182 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2183                                const memctl_options_t *popts,
2184                                fsl_ddr_cfg_regs_t *ddr,
2185                                const common_timing_params_t *common_dimm,
2186                                const dimm_params_t *dimm_params,
2187                                unsigned int dbw_cap_adj,
2188                                unsigned int size_only)
2189 {
2190         unsigned int i;
2191         unsigned int cas_latency;
2192         unsigned int additive_latency;
2193         unsigned int sr_it;
2194         unsigned int zq_en;
2195         unsigned int wrlvl_en;
2196         unsigned int ip_rev = 0;
2197         unsigned int unq_mrs_en = 0;
2198         int cs_en = 1;
2199
2200         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2201
2202         if (common_dimm == NULL) {
2203                 printf("Error: subset DIMM params struct null pointer\n");
2204                 return 1;
2205         }
2206
2207         /*
2208          * Process overrides first.
2209          *
2210          * FIXME: somehow add dereated caslat to this
2211          */
2212         cas_latency = (popts->cas_latency_override)
2213                 ? popts->cas_latency_override_value
2214                 : common_dimm->lowest_common_spd_caslat;
2215
2216         additive_latency = (popts->additive_latency_override)
2217                 ? popts->additive_latency_override_value
2218                 : common_dimm->additive_latency;
2219
2220         sr_it = (popts->auto_self_refresh_en)
2221                 ? popts->sr_it
2222                 : 0;
2223         /* ZQ calibration */
2224         zq_en = (popts->zq_en) ? 1 : 0;
2225         /* write leveling */
2226         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2227
2228         /* Chip Select Memory Bounds (CSn_BNDS) */
2229         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2230                 unsigned long long ea, sa;
2231                 unsigned int cs_per_dimm
2232                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2233                 unsigned int dimm_number
2234                         = i / cs_per_dimm;
2235                 unsigned long long rank_density
2236                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2237
2238                 if (dimm_params[dimm_number].n_ranks == 0) {
2239                         debug("Skipping setup of CS%u "
2240                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2241                         continue;
2242                 }
2243                 if (popts->memctl_interleaving) {
2244                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2245                         case FSL_DDR_CS0_CS1_CS2_CS3:
2246                                 break;
2247                         case FSL_DDR_CS0_CS1:
2248                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2249                                 if (i > 1)
2250                                         cs_en = 0;
2251                                 break;
2252                         case FSL_DDR_CS2_CS3:
2253                         default:
2254                                 if (i > 0)
2255                                         cs_en = 0;
2256                                 break;
2257                         }
2258                         sa = common_dimm->base_address;
2259                         ea = sa + common_dimm->total_mem - 1;
2260                 } else if (!popts->memctl_interleaving) {
2261                         /*
2262                          * If memory interleaving between controllers is NOT
2263                          * enabled, the starting address for each memory
2264                          * controller is distinct.  However, because rank
2265                          * interleaving is enabled, the starting and ending
2266                          * addresses of the total memory on that memory
2267                          * controller needs to be programmed into its
2268                          * respective CS0_BNDS.
2269                          */
2270                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2271                         case FSL_DDR_CS0_CS1_CS2_CS3:
2272                                 sa = common_dimm->base_address;
2273                                 ea = sa + common_dimm->total_mem - 1;
2274                                 break;
2275                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2276                                 if ((i >= 2) && (dimm_number == 0)) {
2277                                         sa = dimm_params[dimm_number].base_address +
2278                                               2 * rank_density;
2279                                         ea = sa + 2 * rank_density - 1;
2280                                 } else {
2281                                         sa = dimm_params[dimm_number].base_address;
2282                                         ea = sa + 2 * rank_density - 1;
2283                                 }
2284                                 break;
2285                         case FSL_DDR_CS0_CS1:
2286                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2287                                         sa = dimm_params[dimm_number].base_address;
2288                                         ea = sa + rank_density - 1;
2289                                         if (i != 1)
2290                                                 sa += (i % cs_per_dimm) * rank_density;
2291                                         ea += (i % cs_per_dimm) * rank_density;
2292                                 } else {
2293                                         sa = 0;
2294                                         ea = 0;
2295                                 }
2296                                 if (i == 0)
2297                                         ea += rank_density;
2298                                 break;
2299                         case FSL_DDR_CS2_CS3:
2300                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2301                                         sa = dimm_params[dimm_number].base_address;
2302                                         ea = sa + rank_density - 1;
2303                                         if (i != 3)
2304                                                 sa += (i % cs_per_dimm) * rank_density;
2305                                         ea += (i % cs_per_dimm) * rank_density;
2306                                 } else {
2307                                         sa = 0;
2308                                         ea = 0;
2309                                 }
2310                                 if (i == 2)
2311                                         ea += (rank_density >> dbw_cap_adj);
2312                                 break;
2313                         default:  /* No bank(chip-select) interleaving */
2314                                 sa = dimm_params[dimm_number].base_address;
2315                                 ea = sa + rank_density - 1;
2316                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2317                                         sa += (i % cs_per_dimm) * rank_density;
2318                                         ea += (i % cs_per_dimm) * rank_density;
2319                                 } else {
2320                                         sa = 0;
2321                                         ea = 0;
2322                                 }
2323                                 break;
2324                         }
2325                 }
2326
2327                 sa >>= 24;
2328                 ea >>= 24;
2329
2330                 if (cs_en) {
2331                         ddr->cs[i].bnds = (0
2332                                 | ((sa & 0xffff) << 16) /* starting address */
2333                                 | ((ea & 0xffff) << 0)  /* ending address */
2334                                 );
2335                 } else {
2336                         /* setting bnds to 0xffffffff for inactive CS */
2337                         ddr->cs[i].bnds = 0xffffffff;
2338                 }
2339
2340                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2341                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2342                 set_csn_config_2(i, ddr);
2343         }
2344
2345         /*
2346          * In the case we only need to compute the ddr sdram size, we only need
2347          * to set csn registers, so return from here.
2348          */
2349         if (size_only)
2350                 return 0;
2351
2352         set_ddr_eor(ddr, popts);
2353
2354 #if !defined(CONFIG_SYS_FSL_DDR1)
2355         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2356 #endif
2357
2358         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2359                          additive_latency);
2360         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2361         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2362                          cas_latency, additive_latency);
2363
2364         set_ddr_cdr1(ddr, popts);
2365         set_ddr_cdr2(ddr, popts);
2366         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2367         ip_rev = fsl_ddr_get_version(ctrl_num);
2368         if (ip_rev > 0x40400)
2369                 unq_mrs_en = 1;
2370
2371         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2372                 ddr->debug[18] = popts->cswl_override;
2373
2374         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2375         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2376                            cas_latency, additive_latency, unq_mrs_en);
2377         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2378 #ifdef CONFIG_SYS_FSL_DDR4
2379         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2380         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2381 #endif
2382         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2383         set_ddr_data_init(ddr);
2384         set_ddr_sdram_clk_cntl(ddr, popts);
2385         set_ddr_init_addr(ddr);
2386         set_ddr_init_ext_addr(ddr);
2387         set_timing_cfg_4(ddr, popts);
2388         set_timing_cfg_5(ddr, cas_latency);
2389 #ifdef CONFIG_SYS_FSL_DDR4
2390         set_ddr_sdram_cfg_3(ddr, popts);
2391         set_timing_cfg_6(ddr);
2392         set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2393         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2394         set_timing_cfg_9(ddr);
2395         set_ddr_dq_mapping(ddr, dimm_params);
2396 #endif
2397
2398         set_ddr_zq_cntl(ddr, zq_en);
2399         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2400
2401         set_ddr_sr_cntr(ddr, sr_it);
2402
2403         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2404
2405 #ifdef CONFIG_SYS_FSL_DDR_EMU
2406         /* disble DDR training for emulator */
2407         ddr->debug[2] = 0x00000400;
2408         ddr->debug[4] = 0xff800800;
2409         ddr->debug[5] = 0x08000800;
2410         ddr->debug[6] = 0x08000800;
2411         ddr->debug[7] = 0x08000800;
2412         ddr->debug[8] = 0x08000800;
2413 #endif
2414 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2415         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2416                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2417 #endif
2418
2419         return check_fsl_memctl_config_regs(ddr);
2420 }