drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   9  * Based on code from spd_sdram.c
  10  * Author: James Yang [at freescale.com]
  11  */
  12
  13 #include <common.h>
  14 #include <fsl_ddr_sdram.h>
  15
  16 #include <fsl_ddr.h>
  17 #include <fsl_immap.h>
  18 #include <asm/io.h>
  19
  20 /*
  21  * Determine Rtt value.
  22  *
  23  * This should likely be either board or controller specific.
  24  *
  25  * Rtt(nominal) - DDR2:
  26  *      0 = Rtt disabled
  27  *      1 = 75 ohm
  28  *      2 = 150 ohm
  29  *      3 = 50 ohm
  30  * Rtt(nominal) - DDR3:
  31  *      0 = Rtt disabled
  32  *      1 = 60 ohm
  33  *      2 = 120 ohm
  34  *      3 = 40 ohm
  35  *      4 = 20 ohm
  36  *      5 = 30 ohm
  37  *
  38  * FIXME: Apparently 8641 needs a value of 2
  39  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  40  *
  41  * FIXME: There was some effort down this line earlier:
  42  *
  43  *      unsigned int i;
  44  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  45  *              if (popts->dimmslot[i].num_valid_cs
  46  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  47  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  48  *                      rtt = 2;
  49  *                      break;
  50  *              }
  51  *      }
  52  */
  53 static inline int fsl_ddr_get_rtt(void)
  54 {
  55         int rtt;
  56
  57 #if defined(CONFIG_SYS_FSL_DDR1)
  58         rtt = 0;
  59 #elif defined(CONFIG_SYS_FSL_DDR2)
  60         rtt = 3;
  61 #else
  62         rtt = 0;
  63 #endif
  64
  65         return rtt;
  66 }
  67
  68 #ifdef CONFIG_SYS_FSL_DDR4
  69 /*
  70  * compute CAS write latency according to DDR4 spec
  71  * CWL = 9 for <= 1600MT/s
  72  *       10 for <= 1866MT/s
  73  *       11 for <= 2133MT/s
  74  *       12 for <= 2400MT/s
  75  *       14 for <= 2667MT/s
  76  *       16 for <= 2933MT/s
  77  *       18 for higher
  78  */
  79 static inline unsigned int compute_cas_write_latency(
  80                                 const unsigned int ctrl_num)
  81 {
  82         unsigned int cwl;
  83         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  84         if (mclk_ps >= 1250)
  85                 cwl = 9;
  86         else if (mclk_ps >= 1070)
  87                 cwl = 10;
  88         else if (mclk_ps >= 935)
  89                 cwl = 11;
  90         else if (mclk_ps >= 833)
  91                 cwl = 12;
  92         else if (mclk_ps >= 750)
  93                 cwl = 14;
  94         else if (mclk_ps >= 681)
  95                 cwl = 16;
  96         else
  97                 cwl = 18;
  98
  99         return cwl;
 100 }
 101 #else
 102 /*
 103  * compute the CAS write latency according to DDR3 spec
 104  * CWL = 5 if tCK >= 2.5ns
 105  *       6 if 2.5ns > tCK >= 1.875ns
 106  *       7 if 1.875ns > tCK >= 1.5ns
 107  *       8 if 1.5ns > tCK >= 1.25ns
 108  *       9 if 1.25ns > tCK >= 1.07ns
 109  *       10 if 1.07ns > tCK >= 0.935ns
 110  *       11 if 0.935ns > tCK >= 0.833ns
 111  *       12 if 0.833ns > tCK >= 0.75ns
 112  */
 113 static inline unsigned int compute_cas_write_latency(
 114                                 const unsigned int ctrl_num)
 115 {
 116         unsigned int cwl;
 117         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 118
 119         if (mclk_ps >= 2500)
 120                 cwl = 5;
 121         else if (mclk_ps >= 1875)
 122                 cwl = 6;
 123         else if (mclk_ps >= 1500)
 124                 cwl = 7;
 125         else if (mclk_ps >= 1250)
 126                 cwl = 8;
 127         else if (mclk_ps >= 1070)
 128                 cwl = 9;
 129         else if (mclk_ps >= 935)
 130                 cwl = 10;
 131         else if (mclk_ps >= 833)
 132                 cwl = 11;
 133         else if (mclk_ps >= 750)
 134                 cwl = 12;
 135         else {
 136                 cwl = 12;
 137                 printf("Warning: CWL is out of range\n");
 138         }
 139         return cwl;
 140 }
 141 #endif
 142
 143 /* Chip Select Configuration (CSn_CONFIG) */
 144 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 145                                const memctl_options_t *popts,
 146                                const dimm_params_t *dimm_params)
 147 {
 148         unsigned int cs_n_en = 0; /* Chip Select enable */
 149         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 150         unsigned int intlv_ctl = 0; /* Interleaving control */
 151         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 152         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 153         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 154         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 155         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 156         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 157         int go_config = 0;
 158 #ifdef CONFIG_SYS_FSL_DDR4
 159         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 160 #else
 161         unsigned int n_banks_per_sdram_device;
 162 #endif
 163
 164         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 165         switch (i) {
 166         case 0:
 167                 if (dimm_params[dimm_number].n_ranks > 0) {
 168                         go_config = 1;
 169                         /* These fields only available in CS0_CONFIG */
 170                         if (!popts->memctl_interleaving)
 171                                 break;
 172                         switch (popts->memctl_interleaving_mode) {
 173                         case FSL_DDR_256B_INTERLEAVING:
 174                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 175                         case FSL_DDR_PAGE_INTERLEAVING:
 176                         case FSL_DDR_BANK_INTERLEAVING:
 177                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 178                                 intlv_en = popts->memctl_interleaving;
 179                                 intlv_ctl = popts->memctl_interleaving_mode;
 180                                 break;
 181                         default:
 182                                 break;
 183                         }
 184                 }
 185                 break;
 186         case 1:
 187                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 188                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 189                         go_config = 1;
 190                 break;
 191         case 2:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 193                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 3:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 198                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 199                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 200                         go_config = 1;
 201                 break;
 202         default:
 203                 break;
 204         }
 205         if (go_config) {
 206                 cs_n_en = 1;
 207                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 208                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 209                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 210 #ifdef CONFIG_SYS_FSL_DDR4
 211                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 212                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 213 #else
 214                 n_banks_per_sdram_device
 215                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 216                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 217 #endif
 218                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 219                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 220         }
 221         ddr->cs[i].config = (0
 222                 | ((cs_n_en & 0x1) << 31)
 223                 | ((intlv_en & 0x3) << 29)
 224                 | ((intlv_ctl & 0xf) << 24)
 225                 | ((ap_n_en & 0x1) << 23)
 226
 227                 /* XXX: some implementation only have 1 bit starting at left */
 228                 | ((odt_rd_cfg & 0x7) << 20)
 229
 230                 /* XXX: Some implementation only have 1 bit starting at left */
 231                 | ((odt_wr_cfg & 0x7) << 16)
 232
 233                 | ((ba_bits_cs_n & 0x3) << 14)
 234                 | ((row_bits_cs_n & 0x7) << 8)
 235 #ifdef CONFIG_SYS_FSL_DDR4
 236                 | ((bg_bits_cs_n & 0x3) << 4)
 237 #endif
 238                 | ((col_bits_cs_n & 0x7) << 0)
 239                 );
 240         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 241 }
 242
 243 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 244 /* FIXME: 8572 */
 245 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 246 {
 247         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 248
 249         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 250         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 251 }
 252
 253 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 254
 255 #if !defined(CONFIG_SYS_FSL_DDR1)
 256 /*
 257  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 258  * Return 1 if other two slots configuration. Return 0 if single slot.
 259  */
 260 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 261 {
 262 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 263         if (dimm_params[0].n_ranks == 4)
 264                 return 2;
 265 #endif
 266
 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 268         if ((dimm_params[0].n_ranks == 2) &&
 269                 (dimm_params[1].n_ranks == 2))
 270                 return 2;
 271
 272 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 273         if (dimm_params[0].n_ranks == 4)
 274                 return 2;
 275 #endif
 276
 277         if ((dimm_params[0].n_ranks != 0) &&
 278             (dimm_params[2].n_ranks != 0))
 279                 return 1;
 280 #endif
 281         return 0;
 282 }
 283
 284 /*
 285  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 286  *
 287  * Avoid writing for DDR I.  The new PQ38 DDR controller
 288  * dreams up non-zero default values to be backwards compatible.
 289  */
 290 static void set_timing_cfg_0(const unsigned int ctrl_num,
 291                                 fsl_ddr_cfg_regs_t *ddr,
 292                                 const memctl_options_t *popts,
 293                                 const dimm_params_t *dimm_params)
 294 {
 295         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 296         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 297         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 298         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 299         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 300
 301         /* Active powerdown exit timing (tXARD and tXARDS). */
 302         unsigned char act_pd_exit_mclk;
 303         /* Precharge powerdown exit timing (tXP). */
 304         unsigned char pre_pd_exit_mclk;
 305         /* ODT powerdown exit timing (tAXPD). */
 306         unsigned char taxpd_mclk = 0;
 307         /* Mode register set cycle time (tMRD). */
 308         unsigned char tmrd_mclk;
 309 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 310         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 311 #endif
 312
 313 #ifdef CONFIG_SYS_FSL_DDR4
 314         /* tXP=max(4nCK, 6ns) */
 315         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 316         unsigned int data_rate = get_ddr_freq(ctrl_num);
 317
 318         /* for faster clock, need more time for data setup */
 319         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 320
 321         /*
 322          * for single quad-rank DIMM and two-slot DIMMs
 323          * to avoid ODT overlap
 324          */
 325         switch (avoid_odt_overlap(dimm_params)) {
 326         case 2:
 327                 twrt_mclk = 2;
 328                 twwt_mclk = 2;
 329                 trrt_mclk = 2;
 330                 break;
 331         default:
 332                 twrt_mclk = 1;
 333                 twwt_mclk = 1;
 334                 trrt_mclk = 0;
 335                 break;
 336         }
 337
 338         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 339         pre_pd_exit_mclk = act_pd_exit_mclk;
 340         /*
 341          * MRS_CYC = max(tMRD, tMOD)
 342          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 343          */
 344         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 345 #elif defined(CONFIG_SYS_FSL_DDR3)
 346         unsigned int data_rate = get_ddr_freq(ctrl_num);
 347         int txp;
 348         unsigned int ip_rev;
 349         int odt_overlap;
 350         /*
 351          * (tXARD and tXARDS). Empirical?
 352          * The DDR3 spec has not tXARD,
 353          * we use the tXP instead of it.
 354          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 355          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 356          * spec has not the tAXPD, we use
 357          * tAXPD=1, need design to confirm.
 358          */
 359         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 360
 361         ip_rev = fsl_ddr_get_version(ctrl_num);
 362         if (ip_rev >= 0x40700) {
 363                 /*
 364                  * MRS_CYC = max(tMRD, tMOD)
 365                  * tMRD = 4nCK (8nCK for RDIMM)
 366                  * tMOD = max(12nCK, 15ns)
 367                  */
 368                 tmrd_mclk = max((unsigned int)12,
 369                                 picos_to_mclk(ctrl_num, 15000));
 370         } else {
 371                 /*
 372                  * MRS_CYC = tMRD
 373                  * tMRD = 4nCK (8nCK for RDIMM)
 374                  */
 375                 if (popts->registered_dimm_en)
 376                         tmrd_mclk = 8;
 377                 else
 378                         tmrd_mclk = 4;
 379         }
 380
 381         /* set the turnaround time */
 382
 383         /*
 384          * for single quad-rank DIMM and two-slot DIMMs
 385          * to avoid ODT overlap
 386          */
 387         odt_overlap = avoid_odt_overlap(dimm_params);
 388         switch (odt_overlap) {
 389         case 2:
 390                 twwt_mclk = 2;
 391                 trrt_mclk = 1;
 392                 break;
 393         case 1:
 394                 twwt_mclk = 1;
 395                 trrt_mclk = 0;
 396                 break;
 397         default:
 398                 break;
 399         }
 400
 401         /* for faster clock, need more time for data setup */
 402         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 403
 404         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 405                 twrt_mclk = 1;
 406
 407         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 408                 act_pd_exit_mclk = 1;
 409                 pre_pd_exit_mclk = 1;
 410                 taxpd_mclk = 1;
 411         } else {
 412                 /* act_pd_exit_mclk = tXARD, see above */
 413                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 414                 /* Mode register MR0[A12] is '1' - fast exit */
 415                 pre_pd_exit_mclk = act_pd_exit_mclk;
 416                 taxpd_mclk = 1;
 417         }
 418 #else /* CONFIG_SYS_FSL_DDR2 */
 419         /*
 420          * (tXARD and tXARDS). Empirical?
 421          * tXARD = 2 for DDR2
 422          * tXP=2
 423          * tAXPD=8
 424          */
 425         act_pd_exit_mclk = 2;
 426         pre_pd_exit_mclk = 2;
 427         taxpd_mclk = 8;
 428         tmrd_mclk = 2;
 429 #endif
 430
 431         if (popts->trwt_override)
 432                 trwt_mclk = popts->trwt;
 433
 434         ddr->timing_cfg_0 = (0
 435                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 436                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 437                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 438                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 439                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 440                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 441                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 442                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 443                 );
 444         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 445 }
 446 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 447
 448 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 449 static void set_timing_cfg_3(const unsigned int ctrl_num,
 450                              fsl_ddr_cfg_regs_t *ddr,
 451                              const memctl_options_t *popts,
 452                              const common_timing_params_t *common_dimm,
 453                              unsigned int cas_latency,
 454                              unsigned int additive_latency)
 455 {
 456         /* Extended precharge to activate interval (tRP) */
 457         unsigned int ext_pretoact = 0;
 458         /* Extended Activate to precharge interval (tRAS) */
 459         unsigned int ext_acttopre = 0;
 460         /* Extended activate to read/write interval (tRCD) */
 461         unsigned int ext_acttorw = 0;
 462         /* Extended refresh recovery time (tRFC) */
 463         unsigned int ext_refrec;
 464         /* Extended MCAS latency from READ cmd */
 465         unsigned int ext_caslat = 0;
 466         /* Extended additive latency */
 467         unsigned int ext_add_lat = 0;
 468         /* Extended last data to precharge interval (tWR) */
 469         unsigned int ext_wrrec = 0;
 470         /* Control Adjust */
 471         unsigned int cntl_adj = 0;
 472
 473         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 474         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 475         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 476         ext_caslat = (2 * cas_latency - 1) >> 4;
 477         ext_add_lat = additive_latency >> 4;
 478 #ifdef CONFIG_SYS_FSL_DDR4
 479         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 480 #else
 481         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 482         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 483 #endif
 484         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 485                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 486
 487         ddr->timing_cfg_3 = (0
 488                 | ((ext_pretoact & 0x1) << 28)
 489                 | ((ext_acttopre & 0x3) << 24)
 490                 | ((ext_acttorw & 0x1) << 22)
 491                 | ((ext_refrec & 0x1F) << 16)
 492                 | ((ext_caslat & 0x3) << 12)
 493                 | ((ext_add_lat & 0x1) << 10)
 494                 | ((ext_wrrec & 0x1) << 8)
 495                 | ((cntl_adj & 0x7) << 0)
 496                 );
 497         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 498 }
 499
 500 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 501 static void set_timing_cfg_1(const unsigned int ctrl_num,
 502                              fsl_ddr_cfg_regs_t *ddr,
 503                              const memctl_options_t *popts,
 504                              const common_timing_params_t *common_dimm,
 505                              unsigned int cas_latency)
 506 {
 507         /* Precharge-to-activate interval (tRP) */
 508         unsigned char pretoact_mclk;
 509         /* Activate to precharge interval (tRAS) */
 510         unsigned char acttopre_mclk;
 511         /*  Activate to read/write interval (tRCD) */
 512         unsigned char acttorw_mclk;
 513         /* CASLAT */
 514         unsigned char caslat_ctrl;
 515         /*  Refresh recovery time (tRFC) ; trfc_low */
 516         unsigned char refrec_ctrl;
 517         /* Last data to precharge minimum interval (tWR) */
 518         unsigned char wrrec_mclk;
 519         /* Activate-to-activate interval (tRRD) */
 520         unsigned char acttoact_mclk;
 521         /* Last write data pair to read command issue interval (tWTR) */
 522         unsigned char wrtord_mclk;
 523 #ifdef CONFIG_SYS_FSL_DDR4
 524         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 525         static const u8 wrrec_table[] = {
 526                 10, 10, 10, 10, 10,
 527                 10, 10, 10, 10, 10,
 528                 12, 12, 14, 14, 16,
 529                 16, 18, 18, 20, 20,
 530                 24, 24, 24, 24};
 531 #else
 532         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 533         static const u8 wrrec_table[] = {
 534                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 535 #endif
 536
 537         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 538         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 539         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 540
 541         /*
 542          * Translate CAS Latency to a DDR controller field value:
 543          *
 544          *      CAS Lat DDR I   DDR II  Ctrl
 545          *      Clocks  SPD Bit SPD Bit Value
 546          *      ------- ------- ------- -----
 547          *      1.0     0               0001
 548          *      1.5     1               0010
 549          *      2.0     2       2       0011
 550          *      2.5     3               0100
 551          *      3.0     4       3       0101
 552          *      3.5     5               0110
 553          *      4.0             4       0111
 554          *      4.5                     1000
 555          *      5.0             5       1001
 556          */
 557 #if defined(CONFIG_SYS_FSL_DDR1)
 558         caslat_ctrl = (cas_latency + 1) & 0x07;
 559 #elif defined(CONFIG_SYS_FSL_DDR2)
 560         caslat_ctrl = 2 * cas_latency - 1;
 561 #else
 562         /*
 563          * if the CAS latency more than 8 cycle,
 564          * we need set extend bit for it at
 565          * TIMING_CFG_3[EXT_CASLAT]
 566          */
 567         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 568                 caslat_ctrl = 2 * cas_latency - 1;
 569         else
 570                 caslat_ctrl = (cas_latency - 1) << 1;
 571 #endif
 572
 573 #ifdef CONFIG_SYS_FSL_DDR4
 574         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 575         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 576         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 577         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 578         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 579                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 580         else
 581                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 582 #else
 583         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 584         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 585         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 586         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 587         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 588                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 589         else
 590                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 591 #endif
 592         if (popts->otf_burst_chop_en)
 593                 wrrec_mclk += 2;
 594
 595         /*
 596          * JEDEC has min requirement for tRRD
 597          */
 598 #if defined(CONFIG_SYS_FSL_DDR3)
 599         if (acttoact_mclk < 4)
 600                 acttoact_mclk = 4;
 601 #endif
 602         /*
 603          * JEDEC has some min requirements for tWTR
 604          */
 605 #if defined(CONFIG_SYS_FSL_DDR2)
 606         if (wrtord_mclk < 2)
 607                 wrtord_mclk = 2;
 608 #elif defined(CONFIG_SYS_FSL_DDR3)
 609         if (wrtord_mclk < 4)
 610                 wrtord_mclk = 4;
 611 #endif
 612         if (popts->otf_burst_chop_en)
 613                 wrtord_mclk += 2;
 614
 615         ddr->timing_cfg_1 = (0
 616                 | ((pretoact_mclk & 0x0F) << 28)
 617                 | ((acttopre_mclk & 0x0F) << 24)
 618                 | ((acttorw_mclk & 0xF) << 20)
 619                 | ((caslat_ctrl & 0xF) << 16)
 620                 | ((refrec_ctrl & 0xF) << 12)
 621                 | ((wrrec_mclk & 0x0F) << 8)
 622                 | ((acttoact_mclk & 0x0F) << 4)
 623                 | ((wrtord_mclk & 0x0F) << 0)
 624                 );
 625         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 626 }
 627
 628 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 629 static void set_timing_cfg_2(const unsigned int ctrl_num,
 630                              fsl_ddr_cfg_regs_t *ddr,
 631                              const memctl_options_t *popts,
 632                              const common_timing_params_t *common_dimm,
 633                              unsigned int cas_latency,
 634                              unsigned int additive_latency)
 635 {
 636         /* Additive latency */
 637         unsigned char add_lat_mclk;
 638         /* CAS-to-preamble override */
 639         unsigned short cpo;
 640         /* Write latency */
 641         unsigned char wr_lat;
 642         /*  Read to precharge (tRTP) */
 643         unsigned char rd_to_pre;
 644         /* Write command to write data strobe timing adjustment */
 645         unsigned char wr_data_delay;
 646         /* Minimum CKE pulse width (tCKE) */
 647         unsigned char cke_pls;
 648         /* Window for four activates (tFAW) */
 649         unsigned short four_act;
 650 #ifdef CONFIG_SYS_FSL_DDR3
 651         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 652 #endif
 653
 654         /* FIXME add check that this must be less than acttorw_mclk */
 655         add_lat_mclk = additive_latency;
 656         cpo = popts->cpo_override;
 657
 658 #if defined(CONFIG_SYS_FSL_DDR1)
 659         /*
 660          * This is a lie.  It should really be 1, but if it is
 661          * set to 1, bits overlap into the old controller's
 662          * otherwise unused ACSM field.  If we leave it 0, then
 663          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 664          */
 665         wr_lat = 0;
 666 #elif defined(CONFIG_SYS_FSL_DDR2)
 667         wr_lat = cas_latency - 1;
 668 #else
 669         wr_lat = compute_cas_write_latency(ctrl_num);
 670 #endif
 671
 672 #ifdef CONFIG_SYS_FSL_DDR4
 673         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 674 #else
 675         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 676 #endif
 677         /*
 678          * JEDEC has some min requirements for tRTP
 679          */
 680 #if defined(CONFIG_SYS_FSL_DDR2)
 681         if (rd_to_pre  < 2)
 682                 rd_to_pre  = 2;
 683 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 684         if (rd_to_pre < 4)
 685                 rd_to_pre = 4;
 686 #endif
 687         if (popts->otf_burst_chop_en)
 688                 rd_to_pre += 2; /* according to UM */
 689
 690         wr_data_delay = popts->write_data_delay;
 691 #ifdef CONFIG_SYS_FSL_DDR4
 692         cpo = 0;
 693         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 694 #elif defined(CONFIG_SYS_FSL_DDR3)
 695         /*
 696          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 697          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 698          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 699          */
 700         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 701                                         (mclk_ps > 1245 ? 5625 : 5000)));
 702 #else
 703         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 704 #endif
 705         four_act = picos_to_mclk(ctrl_num,
 706                                  popts->tfaw_window_four_activates_ps);
 707
 708         ddr->timing_cfg_2 = (0
 709                 | ((add_lat_mclk & 0xf) << 28)
 710                 | ((cpo & 0x1f) << 23)
 711                 | ((wr_lat & 0xf) << 19)
 712                 | ((wr_lat & 0x10) << 14)
 713                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 714                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 715                 | ((cke_pls & 0x7) << 6)
 716                 | ((four_act & 0x3f) << 0)
 717                 );
 718         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 719 }
 720
 721 /* DDR SDRAM Register Control Word */
 722 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 723                                const memctl_options_t *popts,
 724                                const common_timing_params_t *common_dimm)
 725 {
 726         if (common_dimm->all_dimms_registered &&
 727             !common_dimm->all_dimms_unbuffered) {
 728                 if (popts->rcw_override) {
 729                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 730                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 731                 } else {
 732                         ddr->ddr_sdram_rcw_1 =
 733                                 common_dimm->rcw[0] << 28 | \
 734                                 common_dimm->rcw[1] << 24 | \
 735                                 common_dimm->rcw[2] << 20 | \
 736                                 common_dimm->rcw[3] << 16 | \
 737                                 common_dimm->rcw[4] << 12 | \
 738                                 common_dimm->rcw[5] << 8 | \
 739                                 common_dimm->rcw[6] << 4 | \
 740                                 common_dimm->rcw[7];
 741                         ddr->ddr_sdram_rcw_2 =
 742                                 common_dimm->rcw[8] << 28 | \
 743                                 common_dimm->rcw[9] << 24 | \
 744                                 common_dimm->rcw[10] << 20 | \
 745                                 common_dimm->rcw[11] << 16 | \
 746                                 common_dimm->rcw[12] << 12 | \
 747                                 common_dimm->rcw[13] << 8 | \
 748                                 common_dimm->rcw[14] << 4 | \
 749                                 common_dimm->rcw[15];
 750                 }
 751                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n", ddr->ddr_sdram_rcw_1);
 752                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n", ddr->ddr_sdram_rcw_2);
 753         }
 754 }
 755
 756 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 757 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 758                                const memctl_options_t *popts,
 759                                const common_timing_params_t *common_dimm)
 760 {
 761         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 762         unsigned int sren;              /* Self refresh enable (during sleep) */
 763         unsigned int ecc_en;            /* ECC enable. */
 764         unsigned int rd_en;             /* Registered DIMM enable */
 765         unsigned int sdram_type;        /* Type of SDRAM */
 766         unsigned int dyn_pwr;           /* Dynamic power management mode */
 767         unsigned int dbw;               /* DRAM dta bus width */
 768         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 769         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 770         unsigned int threet_en;         /* Enable 3T timing */
 771         unsigned int twot_en;           /* Enable 2T timing */
 772         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 773         unsigned int x32_en = 0;        /* x32 enable */
 774         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 775         unsigned int hse;               /* Global half strength override */
 776         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 777         unsigned int mem_halt = 0;      /* memory controller halt */
 778         unsigned int bi = 0;            /* Bypass initialization */
 779
 780         mem_en = 1;
 781         sren = popts->self_refresh_in_sleep;
 782         if (common_dimm->all_dimms_ecc_capable) {
 783                 /* Allow setting of ECC only if all DIMMs are ECC. */
 784                 ecc_en = popts->ecc_mode;
 785         } else {
 786                 ecc_en = 0;
 787         }
 788
 789         if (common_dimm->all_dimms_registered &&
 790             !common_dimm->all_dimms_unbuffered) {
 791                 rd_en = 1;
 792                 twot_en = 0;
 793         } else {
 794                 rd_en = 0;
 795                 twot_en = popts->twot_en;
 796         }
 797
 798         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 799
 800         dyn_pwr = popts->dynamic_power;
 801         dbw = popts->data_bus_width;
 802         /* 8-beat burst enable DDR-III case
 803          * we must clear it when use the on-the-fly mode,
 804          * must set it when use the 32-bits bus mode.
 805          */
 806         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 807             (sdram_type == SDRAM_TYPE_DDR4)) {
 808                 if (popts->burst_length == DDR_BL8)
 809                         eight_be = 1;
 810                 if (popts->burst_length == DDR_OTF)
 811                         eight_be = 0;
 812                 if (dbw == 0x1)
 813                         eight_be = 1;
 814         }
 815
 816         threet_en = popts->threet_en;
 817         ba_intlv_ctl = popts->ba_intlv_ctl;
 818         hse = popts->half_strength_driver_enable;
 819
 820         /* set when ddr bus width < 64 */
 821         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 822
 823         ddr->ddr_sdram_cfg = (0
 824                         | ((mem_en & 0x1) << 31)
 825                         | ((sren & 0x1) << 30)
 826                         | ((ecc_en & 0x1) << 29)
 827                         | ((rd_en & 0x1) << 28)
 828                         | ((sdram_type & 0x7) << 24)
 829                         | ((dyn_pwr & 0x1) << 21)
 830                         | ((dbw & 0x3) << 19)
 831                         | ((eight_be & 0x1) << 18)
 832                         | ((ncap & 0x1) << 17)
 833                         | ((threet_en & 0x1) << 16)
 834                         | ((twot_en & 0x1) << 15)
 835                         | ((ba_intlv_ctl & 0x7F) << 8)
 836                         | ((x32_en & 0x1) << 5)
 837                         | ((pchb8 & 0x1) << 4)
 838                         | ((hse & 0x1) << 3)
 839                         | ((acc_ecc_en & 0x1) << 2)
 840                         | ((mem_halt & 0x1) << 1)
 841                         | ((bi & 0x1) << 0)
 842                         );
 843         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 844 }
 845
 846 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 847 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 848                                fsl_ddr_cfg_regs_t *ddr,
 849                                const memctl_options_t *popts,
 850                                const unsigned int unq_mrs_en)
 851 {
 852         unsigned int frc_sr = 0;        /* Force self refresh */
 853         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 854         unsigned int odt_cfg = 0;       /* ODT configuration */
 855         unsigned int num_pr;            /* Number of posted refreshes */
 856         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 857         unsigned int x4_en = 0;         /* x4 DRAM enable */
 858         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 859         unsigned int ap_en;             /* Address Parity Enable */
 860         unsigned int d_init;            /* DRAM data initialization */
 861         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 862         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 863         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 864         int i;
 865 #ifndef CONFIG_SYS_FSL_DDR4
 866         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 867         unsigned int dqs_cfg;           /* DQS configuration */
 868
 869         dqs_cfg = popts->dqs_config;
 870 #endif
 871         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 872                 if (popts->cs_local_opts[i].odt_rd_cfg
 873                         || popts->cs_local_opts[i].odt_wr_cfg) {
 874                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 875                         break;
 876                 }
 877         }
 878         sr_ie = popts->self_refresh_interrupt_en;
 879         num_pr = 1;     /* Make this configurable */
 880
 881         /*
 882          * 8572 manual says
 883          *     {TIMING_CFG_1[PRETOACT]
 884          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 885          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 886          *      << DDR_SDRAM_INTERVAL[REFINT]
 887          */
 888 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 889         obc_cfg = popts->otf_burst_chop_en;
 890 #else
 891         obc_cfg = 0;
 892 #endif
 893
 894 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 895         slow = get_ddr_freq(ctrl_num) < 1249000000;
 896 #endif
 897
 898         if (popts->registered_dimm_en) {
 899                 rcw_en = 1;
 900                 ap_en = popts->ap_en;
 901         } else {
 902                 ap_en = 0;
 903         }
 904
 905         x4_en = popts->x4_en ? 1 : 0;
 906
 907 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 908         /* Use the DDR controller to auto initialize memory. */
 909         d_init = popts->ecc_init_using_memctl;
 910         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 911         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 912 #else
 913         /* Memory will be initialized via DMA, or not at all. */
 914         d_init = 0;
 915 #endif
 916
 917 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 918         md_en = popts->mirrored_dimm;
 919 #endif
 920         qd_en = popts->quad_rank_present ? 1 : 0;
 921         ddr->ddr_sdram_cfg_2 = (0
 922                 | ((frc_sr & 0x1) << 31)
 923                 | ((sr_ie & 0x1) << 30)
 924 #ifndef CONFIG_SYS_FSL_DDR4
 925                 | ((dll_rst_dis & 0x1) << 29)
 926                 | ((dqs_cfg & 0x3) << 26)
 927 #endif
 928                 | ((odt_cfg & 0x3) << 21)
 929                 | ((num_pr & 0xf) << 12)
 930                 | ((slow & 1) << 11)
 931                 | (x4_en << 10)
 932                 | (qd_en << 9)
 933                 | (unq_mrs_en << 8)
 934                 | ((obc_cfg & 0x1) << 6)
 935                 | ((ap_en & 0x1) << 5)
 936                 | ((d_init & 0x1) << 4)
 937                 | ((rcw_en & 0x1) << 2)
 938                 | ((md_en & 0x1) << 0)
 939                 );
 940         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 941 }
 942
 943 #ifdef CONFIG_SYS_FSL_DDR4
 944 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 945 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 946                                 fsl_ddr_cfg_regs_t *ddr,
 947                                 const memctl_options_t *popts,
 948                                 const common_timing_params_t *common_dimm,
 949                                 const unsigned int unq_mrs_en)
 950 {
 951         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 952         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 953         int i;
 954         unsigned int wr_crc = 0;        /* Disable */
 955         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 956         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 957         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 958         unsigned int mpr = 0;   /* serial */
 959         unsigned int wc_lat;
 960         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 961
 962         if (popts->rtt_override)
 963                 rtt_wr = popts->rtt_wr_override_value;
 964         else
 965                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 966
 967         if (common_dimm->extended_op_srt)
 968                 srt = common_dimm->extended_op_srt;
 969
 970         esdmode2 = (0
 971                 | ((wr_crc & 0x1) << 12)
 972                 | ((rtt_wr & 0x3) << 9)
 973                 | ((srt & 0x3) << 6)
 974                 | ((cwl & 0x7) << 3));
 975
 976         if (mclk_ps >= 1250)
 977                 wc_lat = 0;
 978         else if (mclk_ps >= 833)
 979                 wc_lat = 1;
 980         else
 981                 wc_lat = 2;
 982
 983         esdmode3 = (0
 984                 | ((mpr & 0x3) << 11)
 985                 | ((wc_lat & 0x3) << 9));
 986
 987         ddr->ddr_sdram_mode_2 = (0
 988                                  | ((esdmode2 & 0xFFFF) << 16)
 989                                  | ((esdmode3 & 0xFFFF) << 0)
 990                                  );
 991         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
 992
 993         if (unq_mrs_en) {       /* unique mode registers are supported */
 994                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 995                         if (popts->rtt_override)
 996                                 rtt_wr = popts->rtt_wr_override_value;
 997                         else
 998                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
 999
1000                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1001                         esdmode2 |= (rtt_wr & 0x3) << 9;
1002                         switch (i) {
1003                         case 1:
1004                                 ddr->ddr_sdram_mode_4 = (0
1005                                         | ((esdmode2 & 0xFFFF) << 16)
1006                                         | ((esdmode3 & 0xFFFF) << 0)
1007                                         );
1008                                 break;
1009                         case 2:
1010                                 ddr->ddr_sdram_mode_6 = (0
1011                                         | ((esdmode2 & 0xFFFF) << 16)
1012                                         | ((esdmode3 & 0xFFFF) << 0)
1013                                         );
1014                                 break;
1015                         case 3:
1016                                 ddr->ddr_sdram_mode_8 = (0
1017                                         | ((esdmode2 & 0xFFFF) << 16)
1018                                         | ((esdmode3 & 0xFFFF) << 0)
1019                                         );
1020                                 break;
1021                         }
1022                 }
1023                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1024                       ddr->ddr_sdram_mode_4);
1025                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1026                       ddr->ddr_sdram_mode_6);
1027                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1028                       ddr->ddr_sdram_mode_8);
1029         }
1030 }
1031 #elif defined(CONFIG_SYS_FSL_DDR3)
1032 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1033 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1034                                 fsl_ddr_cfg_regs_t *ddr,
1035                                 const memctl_options_t *popts,
1036                                 const common_timing_params_t *common_dimm,
1037                                 const unsigned int unq_mrs_en)
1038 {
1039         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1040         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1041         int i;
1042         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1043         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1044         unsigned int asr = 0;   /* auto self-refresh disable */
1045         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1046         unsigned int pasr = 0;  /* partial array self refresh disable */
1047
1048         if (popts->rtt_override)
1049                 rtt_wr = popts->rtt_wr_override_value;
1050         else
1051                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1052
1053         if (common_dimm->extended_op_srt)
1054                 srt = common_dimm->extended_op_srt;
1055
1056         esdmode2 = (0
1057                 | ((rtt_wr & 0x3) << 9)
1058                 | ((srt & 0x1) << 7)
1059                 | ((asr & 0x1) << 6)
1060                 | ((cwl & 0x7) << 3)
1061                 | ((pasr & 0x7) << 0));
1062         ddr->ddr_sdram_mode_2 = (0
1063                                  | ((esdmode2 & 0xFFFF) << 16)
1064                                  | ((esdmode3 & 0xFFFF) << 0)
1065                                  );
1066         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1067
1068         if (unq_mrs_en) {       /* unique mode registers are supported */
1069                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1070                         if (popts->rtt_override)
1071                                 rtt_wr = popts->rtt_wr_override_value;
1072                         else
1073                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1074
1075                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1076                         esdmode2 |= (rtt_wr & 0x3) << 9;
1077                         switch (i) {
1078                         case 1:
1079                                 ddr->ddr_sdram_mode_4 = (0
1080                                         | ((esdmode2 & 0xFFFF) << 16)
1081                                         | ((esdmode3 & 0xFFFF) << 0)
1082                                         );
1083                                 break;
1084                         case 2:
1085                                 ddr->ddr_sdram_mode_6 = (0
1086                                         | ((esdmode2 & 0xFFFF) << 16)
1087                                         | ((esdmode3 & 0xFFFF) << 0)
1088                                         );
1089                                 break;
1090                         case 3:
1091                                 ddr->ddr_sdram_mode_8 = (0
1092                                         | ((esdmode2 & 0xFFFF) << 16)
1093                                         | ((esdmode3 & 0xFFFF) << 0)
1094                                         );
1095                                 break;
1096                         }
1097                 }
1098                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1099                         ddr->ddr_sdram_mode_4);
1100                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1101                         ddr->ddr_sdram_mode_6);
1102                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1103                         ddr->ddr_sdram_mode_8);
1104         }
1105 }
1106
1107 #else /* for DDR2 and DDR1 */
1108 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1109 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1110                                 fsl_ddr_cfg_regs_t *ddr,
1111                                 const memctl_options_t *popts,
1112                                 const common_timing_params_t *common_dimm,
1113                                 const unsigned int unq_mrs_en)
1114 {
1115         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1116         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1117
1118         ddr->ddr_sdram_mode_2 = (0
1119                                  | ((esdmode2 & 0xFFFF) << 16)
1120                                  | ((esdmode3 & 0xFFFF) << 0)
1121                                  );
1122         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1123 }
1124 #endif
1125
1126 #ifdef CONFIG_SYS_FSL_DDR4
1127 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1128 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1129                                 const memctl_options_t *popts,
1130                                 const common_timing_params_t *common_dimm,
1131                                 const unsigned int unq_mrs_en)
1132 {
1133         int i;
1134         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1135         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1136         int rtt_park = 0;
1137         bool four_cs = false;
1138
1139 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1140         if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1141             (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1142             (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1143             (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1144                 four_cs = true;
1145 #endif
1146         if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1147                 esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1148                 rtt_park = four_cs ? 0 : 1;
1149         } else {
1150                 esdmode5 = 0x00000400;  /* Data mask enabled */
1151         }
1152
1153         ddr->ddr_sdram_mode_9 = (0
1154                                  | ((esdmode4 & 0xffff) << 16)
1155                                  | ((esdmode5 & 0xffff) << 0)
1156                                 );
1157
1158         /* Normally only the first enabled CS use 0x500, others use 0x400
1159          * But when four chip-selects are all enabled, all mode registers
1160          * need 0x500 to park.
1161          */
1162
1163         debug("FSLDDR: ddr_sdram_mode_9) = 0x%08x\n", ddr->ddr_sdram_mode_9);
1164         if (unq_mrs_en) {       /* unique mode registers are supported */
1165                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1166                         if (!rtt_park &&
1167                             (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1168                                 esdmode5 |= 0x00000500; /* RTT_PARK */
1169                                 rtt_park = four_cs ? 0 : 1;
1170                         } else {
1171                                 esdmode5 = 0x00000400;
1172                         }
1173                         switch (i) {
1174                         case 1:
1175                                 ddr->ddr_sdram_mode_11 = (0
1176                                         | ((esdmode4 & 0xFFFF) << 16)
1177                                         | ((esdmode5 & 0xFFFF) << 0)
1178                                         );
1179                                 break;
1180                         case 2:
1181                                 ddr->ddr_sdram_mode_13 = (0
1182                                         | ((esdmode4 & 0xFFFF) << 16)
1183                                         | ((esdmode5 & 0xFFFF) << 0)
1184                                         );
1185                                 break;
1186                         case 3:
1187                                 ddr->ddr_sdram_mode_15 = (0
1188                                         | ((esdmode4 & 0xFFFF) << 16)
1189                                         | ((esdmode5 & 0xFFFF) << 0)
1190                                         );
1191                                 break;
1192                         }
1193                 }
1194                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1195                       ddr->ddr_sdram_mode_11);
1196                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1197                       ddr->ddr_sdram_mode_13);
1198                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1199                       ddr->ddr_sdram_mode_15);
1200         }
1201 }
1202
1203 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1204 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1205                                 fsl_ddr_cfg_regs_t *ddr,
1206                                 const memctl_options_t *popts,
1207                                 const common_timing_params_t *common_dimm,
1208                                 const unsigned int unq_mrs_en)
1209 {
1210         int i;
1211         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1212         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1213         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1214
1215         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1216
1217         if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1218                 esdmode6 |= 1 << 6;     /* Range 2 */
1219
1220         ddr->ddr_sdram_mode_10 = (0
1221                                  | ((esdmode6 & 0xffff) << 16)
1222                                  | ((esdmode7 & 0xffff) << 0)
1223                                 );
1224         debug("FSLDDR: ddr_sdram_mode_10) = 0x%08x\n", ddr->ddr_sdram_mode_10);
1225         if (unq_mrs_en) {       /* unique mode registers are supported */
1226                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1227                         switch (i) {
1228                         case 1:
1229                                 ddr->ddr_sdram_mode_12 = (0
1230                                         | ((esdmode6 & 0xFFFF) << 16)
1231                                         | ((esdmode7 & 0xFFFF) << 0)
1232                                         );
1233                                 break;
1234                         case 2:
1235                                 ddr->ddr_sdram_mode_14 = (0
1236                                         | ((esdmode6 & 0xFFFF) << 16)
1237                                         | ((esdmode7 & 0xFFFF) << 0)
1238                                         );
1239                                 break;
1240                         case 3:
1241                                 ddr->ddr_sdram_mode_16 = (0
1242                                         | ((esdmode6 & 0xFFFF) << 16)
1243                                         | ((esdmode7 & 0xFFFF) << 0)
1244                                         );
1245                                 break;
1246                         }
1247                 }
1248                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1249                       ddr->ddr_sdram_mode_12);
1250                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1251                       ddr->ddr_sdram_mode_14);
1252                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1253                       ddr->ddr_sdram_mode_16);
1254         }
1255 }
1256
1257 #endif
1258
1259 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1260 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1261                                 fsl_ddr_cfg_regs_t *ddr,
1262                                 const memctl_options_t *popts,
1263                                 const common_timing_params_t *common_dimm)
1264 {
1265         unsigned int refint;    /* Refresh interval */
1266         unsigned int bstopre;   /* Precharge interval */
1267
1268         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1269
1270         bstopre = popts->bstopre;
1271
1272         /* refint field used 0x3FFF in earlier controllers */
1273         ddr->ddr_sdram_interval = (0
1274                                    | ((refint & 0xFFFF) << 16)
1275                                    | ((bstopre & 0x3FFF) << 0)
1276                                    );
1277         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1278 }
1279
1280 #ifdef CONFIG_SYS_FSL_DDR4
1281 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1282 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1283                                fsl_ddr_cfg_regs_t *ddr,
1284                                const memctl_options_t *popts,
1285                                const common_timing_params_t *common_dimm,
1286                                unsigned int cas_latency,
1287                                unsigned int additive_latency,
1288                                const unsigned int unq_mrs_en)
1289 {
1290         int i;
1291         unsigned short esdmode;         /* Extended SDRAM mode */
1292         unsigned short sdmode;          /* SDRAM mode */
1293
1294         /* Mode Register - MR1 */
1295         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1296         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1297         unsigned int rtt;
1298         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1299         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1300         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1301         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1302                                                        0=Disable (Test/Debug) */
1303
1304         /* Mode Register - MR0 */
1305         unsigned int wr = 0;    /* Write Recovery */
1306         unsigned int dll_rst;   /* DLL Reset */
1307         unsigned int mode;      /* Normal=0 or Test=1 */
1308         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1309         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1310         unsigned int bt;
1311         unsigned int bl;        /* BL: Burst Length */
1312
1313         unsigned int wr_mclk;
1314         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1315         static const u8 wr_table[] = {
1316                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1317         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1318         static const u8 cas_latency_table[] = {
1319                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1320                 9, 9, 10, 10, 11, 11};
1321
1322         if (popts->rtt_override)
1323                 rtt = popts->rtt_override_value;
1324         else
1325                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1326
1327         if (additive_latency == (cas_latency - 1))
1328                 al = 1;
1329         if (additive_latency == (cas_latency - 2))
1330                 al = 2;
1331
1332         if (popts->quad_rank_present)
1333                 dic = 1;        /* output driver impedance 240/7 ohm */
1334
1335         /*
1336          * The esdmode value will also be used for writing
1337          * MR1 during write leveling for DDR3, although the
1338          * bits specifically related to the write leveling
1339          * scheme will be handled automatically by the DDR
1340          * controller. so we set the wrlvl_en = 0 here.
1341          */
1342         esdmode = (0
1343                 | ((qoff & 0x1) << 12)
1344                 | ((tdqs_en & 0x1) << 11)
1345                 | ((rtt & 0x7) << 8)
1346                 | ((wrlvl_en & 0x1) << 7)
1347                 | ((al & 0x3) << 3)
1348                 | ((dic & 0x3) << 1)   /* DIC field is split */
1349                 | ((dll_en & 0x1) << 0)
1350                 );
1351
1352         /*
1353          * DLL control for precharge PD
1354          * 0=slow exit DLL off (tXPDLL)
1355          * 1=fast exit DLL on (tXP)
1356          */
1357
1358         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1359         if (wr_mclk <= 24) {
1360                 wr = wr_table[wr_mclk - 10];
1361         } else {
1362                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1363                        wr_mclk);
1364         }
1365
1366         dll_rst = 0;    /* dll no reset */
1367         mode = 0;       /* normal mode */
1368
1369         /* look up table to get the cas latency bits */
1370         if (cas_latency >= 9 && cas_latency <= 24)
1371                 caslat = cas_latency_table[cas_latency - 9];
1372         else
1373                 printf("Error: unsupported cas latency for mode register\n");
1374
1375         bt = 0; /* Nibble sequential */
1376
1377         switch (popts->burst_length) {
1378         case DDR_BL8:
1379                 bl = 0;
1380                 break;
1381         case DDR_OTF:
1382                 bl = 1;
1383                 break;
1384         case DDR_BC4:
1385                 bl = 2;
1386                 break;
1387         default:
1388                 printf("Error: invalid burst length of %u specified. ",
1389                        popts->burst_length);
1390                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1391                 bl = 1;
1392                 break;
1393         }
1394
1395         sdmode = (0
1396                   | ((wr & 0x7) << 9)
1397                   | ((dll_rst & 0x1) << 8)
1398                   | ((mode & 0x1) << 7)
1399                   | (((caslat >> 1) & 0x7) << 4)
1400                   | ((bt & 0x1) << 3)
1401                   | ((caslat & 1) << 2)
1402                   | ((bl & 0x3) << 0)
1403                   );
1404
1405         ddr->ddr_sdram_mode = (0
1406                                | ((esdmode & 0xFFFF) << 16)
1407                                | ((sdmode & 0xFFFF) << 0)
1408                                );
1409
1410         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1411
1412         if (unq_mrs_en) {       /* unique mode registers are supported */
1413                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1414                         if (popts->rtt_override)
1415                                 rtt = popts->rtt_override_value;
1416                         else
1417                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1418
1419                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1420                         esdmode |= (rtt & 0x7) << 8;
1421                         switch (i) {
1422                         case 1:
1423                                 ddr->ddr_sdram_mode_3 = (0
1424                                        | ((esdmode & 0xFFFF) << 16)
1425                                        | ((sdmode & 0xFFFF) << 0)
1426                                        );
1427                                 break;
1428                         case 2:
1429                                 ddr->ddr_sdram_mode_5 = (0
1430                                        | ((esdmode & 0xFFFF) << 16)
1431                                        | ((sdmode & 0xFFFF) << 0)
1432                                        );
1433                                 break;
1434                         case 3:
1435                                 ddr->ddr_sdram_mode_7 = (0
1436                                        | ((esdmode & 0xFFFF) << 16)
1437                                        | ((sdmode & 0xFFFF) << 0)
1438                                        );
1439                                 break;
1440                         }
1441                 }
1442                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1443                       ddr->ddr_sdram_mode_3);
1444                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1445                       ddr->ddr_sdram_mode_5);
1446                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1447                       ddr->ddr_sdram_mode_5);
1448         }
1449 }
1450
1451 #elif defined(CONFIG_SYS_FSL_DDR3)
1452 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1453 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1454                                fsl_ddr_cfg_regs_t *ddr,
1455                                const memctl_options_t *popts,
1456                                const common_timing_params_t *common_dimm,
1457                                unsigned int cas_latency,
1458                                unsigned int additive_latency,
1459                                const unsigned int unq_mrs_en)
1460 {
1461         int i;
1462         unsigned short esdmode;         /* Extended SDRAM mode */
1463         unsigned short sdmode;          /* SDRAM mode */
1464
1465         /* Mode Register - MR1 */
1466         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1467         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1468         unsigned int rtt;
1469         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1470         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1471         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1472         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1473                                                        1=Disable (Test/Debug) */
1474
1475         /* Mode Register - MR0 */
1476         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1477         unsigned int wr = 0;    /* Write Recovery */
1478         unsigned int dll_rst;   /* DLL Reset */
1479         unsigned int mode;      /* Normal=0 or Test=1 */
1480         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1481         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1482         unsigned int bt;
1483         unsigned int bl;        /* BL: Burst Length */
1484
1485         unsigned int wr_mclk;
1486         /*
1487          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1488          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1489          * for this table
1490          */
1491         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1492
1493         if (popts->rtt_override)
1494                 rtt = popts->rtt_override_value;
1495         else
1496                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1497
1498         if (additive_latency == (cas_latency - 1))
1499                 al = 1;
1500         if (additive_latency == (cas_latency - 2))
1501                 al = 2;
1502
1503         if (popts->quad_rank_present)
1504                 dic = 1;        /* output driver impedance 240/7 ohm */
1505
1506         /*
1507          * The esdmode value will also be used for writing
1508          * MR1 during write leveling for DDR3, although the
1509          * bits specifically related to the write leveling
1510          * scheme will be handled automatically by the DDR
1511          * controller. so we set the wrlvl_en = 0 here.
1512          */
1513         esdmode = (0
1514                 | ((qoff & 0x1) << 12)
1515                 | ((tdqs_en & 0x1) << 11)
1516                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1517                 | ((wrlvl_en & 0x1) << 7)
1518                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1519                 | ((dic & 0x2) << 4)   /* DIC field is split */
1520                 | ((al & 0x3) << 3)
1521                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1522                 | ((dic & 0x1) << 1)   /* DIC field is split */
1523                 | ((dll_en & 0x1) << 0)
1524                 );
1525
1526         /*
1527          * DLL control for precharge PD
1528          * 0=slow exit DLL off (tXPDLL)
1529          * 1=fast exit DLL on (tXP)
1530          */
1531         dll_on = 1;
1532
1533         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1534         if (wr_mclk <= 16) {
1535                 wr = wr_table[wr_mclk - 5];
1536         } else {
1537                 printf("Error: unsupported write recovery for mode register "
1538                        "wr_mclk = %d\n", wr_mclk);
1539         }
1540
1541         dll_rst = 0;    /* dll no reset */
1542         mode = 0;       /* normal mode */
1543
1544         /* look up table to get the cas latency bits */
1545         if (cas_latency >= 5 && cas_latency <= 16) {
1546                 unsigned char cas_latency_table[] = {
1547                         0x2,    /* 5 clocks */
1548                         0x4,    /* 6 clocks */
1549                         0x6,    /* 7 clocks */
1550                         0x8,    /* 8 clocks */
1551                         0xa,    /* 9 clocks */
1552                         0xc,    /* 10 clocks */
1553                         0xe,    /* 11 clocks */
1554                         0x1,    /* 12 clocks */
1555                         0x3,    /* 13 clocks */
1556                         0x5,    /* 14 clocks */
1557                         0x7,    /* 15 clocks */
1558                         0x9,    /* 16 clocks */
1559                 };
1560                 caslat = cas_latency_table[cas_latency - 5];
1561         } else {
1562                 printf("Error: unsupported cas latency for mode register\n");
1563         }
1564
1565         bt = 0; /* Nibble sequential */
1566
1567         switch (popts->burst_length) {
1568         case DDR_BL8:
1569                 bl = 0;
1570                 break;
1571         case DDR_OTF:
1572                 bl = 1;
1573                 break;
1574         case DDR_BC4:
1575                 bl = 2;
1576                 break;
1577         default:
1578                 printf("Error: invalid burst length of %u specified. "
1579                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1580                         popts->burst_length);
1581                 bl = 1;
1582                 break;
1583         }
1584
1585         sdmode = (0
1586                   | ((dll_on & 0x1) << 12)
1587                   | ((wr & 0x7) << 9)
1588                   | ((dll_rst & 0x1) << 8)
1589                   | ((mode & 0x1) << 7)
1590                   | (((caslat >> 1) & 0x7) << 4)
1591                   | ((bt & 0x1) << 3)
1592                   | ((caslat & 1) << 2)
1593                   | ((bl & 0x3) << 0)
1594                   );
1595
1596         ddr->ddr_sdram_mode = (0
1597                                | ((esdmode & 0xFFFF) << 16)
1598                                | ((sdmode & 0xFFFF) << 0)
1599                                );
1600
1601         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1602
1603         if (unq_mrs_en) {       /* unique mode registers are supported */
1604                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1605                         if (popts->rtt_override)
1606                                 rtt = popts->rtt_override_value;
1607                         else
1608                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1609
1610                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1611                         esdmode |= (0
1612                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1613                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1614                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1615                                 );
1616                         switch (i) {
1617                         case 1:
1618                                 ddr->ddr_sdram_mode_3 = (0
1619                                        | ((esdmode & 0xFFFF) << 16)
1620                                        | ((sdmode & 0xFFFF) << 0)
1621                                        );
1622                                 break;
1623                         case 2:
1624                                 ddr->ddr_sdram_mode_5 = (0
1625                                        | ((esdmode & 0xFFFF) << 16)
1626                                        | ((sdmode & 0xFFFF) << 0)
1627                                        );
1628                                 break;
1629                         case 3:
1630                                 ddr->ddr_sdram_mode_7 = (0
1631                                        | ((esdmode & 0xFFFF) << 16)
1632                                        | ((sdmode & 0xFFFF) << 0)
1633                                        );
1634                                 break;
1635                         }
1636                 }
1637                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1638                         ddr->ddr_sdram_mode_3);
1639                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1640                         ddr->ddr_sdram_mode_5);
1641                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1642                         ddr->ddr_sdram_mode_5);
1643         }
1644 }
1645
1646 #else /* !CONFIG_SYS_FSL_DDR3 */
1647
1648 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1649 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1650                                fsl_ddr_cfg_regs_t *ddr,
1651                                const memctl_options_t *popts,
1652                                const common_timing_params_t *common_dimm,
1653                                unsigned int cas_latency,
1654                                unsigned int additive_latency,
1655                                const unsigned int unq_mrs_en)
1656 {
1657         unsigned short esdmode;         /* Extended SDRAM mode */
1658         unsigned short sdmode;          /* SDRAM mode */
1659
1660         /*
1661          * FIXME: This ought to be pre-calculated in a
1662          * technology-specific routine,
1663          * e.g. compute_DDR2_mode_register(), and then the
1664          * sdmode and esdmode passed in as part of common_dimm.
1665          */
1666
1667         /* Extended Mode Register */
1668         unsigned int mrs = 0;           /* Mode Register Set */
1669         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1670         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1671         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1672         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1673                                            0x7=OCD default state */
1674         unsigned int rtt;
1675         unsigned int al;                /* Posted CAS# additive latency (AL) */
1676         unsigned int ods = 0;           /* Output Drive Strength:
1677                                                 0 = Full strength (18ohm)
1678                                                 1 = Reduced strength (4ohm) */
1679         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1680                                                        1=Disable (Test/Debug) */
1681
1682         /* Mode Register (MR) */
1683         unsigned int mr;        /* Mode Register Definition */
1684         unsigned int pd;        /* Power-Down Mode */
1685         unsigned int wr;        /* Write Recovery */
1686         unsigned int dll_res;   /* DLL Reset */
1687         unsigned int mode;      /* Normal=0 or Test=1 */
1688         unsigned int caslat = 0;/* CAS# latency */
1689         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1690         unsigned int bt;
1691         unsigned int bl;        /* BL: Burst Length */
1692
1693         dqs_en = !popts->dqs_config;
1694         rtt = fsl_ddr_get_rtt();
1695
1696         al = additive_latency;
1697
1698         esdmode = (0
1699                 | ((mrs & 0x3) << 14)
1700                 | ((outputs & 0x1) << 12)
1701                 | ((rdqs_en & 0x1) << 11)
1702                 | ((dqs_en & 0x1) << 10)
1703                 | ((ocd & 0x7) << 7)
1704                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1705                 | ((al & 0x7) << 3)
1706                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1707                 | ((ods & 0x1) << 1)
1708                 | ((dll_en & 0x1) << 0)
1709                 );
1710
1711         mr = 0;          /* FIXME: CHECKME */
1712
1713         /*
1714          * 0 = Fast Exit (Normal)
1715          * 1 = Slow Exit (Low Power)
1716          */
1717         pd = 0;
1718
1719 #if defined(CONFIG_SYS_FSL_DDR1)
1720         wr = 0;       /* Historical */
1721 #elif defined(CONFIG_SYS_FSL_DDR2)
1722         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1723 #endif
1724         dll_res = 0;
1725         mode = 0;
1726
1727 #if defined(CONFIG_SYS_FSL_DDR1)
1728         if (1 <= cas_latency && cas_latency <= 4) {
1729                 unsigned char mode_caslat_table[4] = {
1730                         0x5,    /* 1.5 clocks */
1731                         0x2,    /* 2.0 clocks */
1732                         0x6,    /* 2.5 clocks */
1733                         0x3     /* 3.0 clocks */
1734                 };
1735                 caslat = mode_caslat_table[cas_latency - 1];
1736         } else {
1737                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1738         }
1739 #elif defined(CONFIG_SYS_FSL_DDR2)
1740         caslat = cas_latency;
1741 #endif
1742         bt = 0;
1743
1744         switch (popts->burst_length) {
1745         case DDR_BL4:
1746                 bl = 2;
1747                 break;
1748         case DDR_BL8:
1749                 bl = 3;
1750                 break;
1751         default:
1752                 printf("Error: invalid burst length of %u specified. "
1753                         " Defaulting to 4 beats.\n",
1754                         popts->burst_length);
1755                 bl = 2;
1756                 break;
1757         }
1758
1759         sdmode = (0
1760                   | ((mr & 0x3) << 14)
1761                   | ((pd & 0x1) << 12)
1762                   | ((wr & 0x7) << 9)
1763                   | ((dll_res & 0x1) << 8)
1764                   | ((mode & 0x1) << 7)
1765                   | ((caslat & 0x7) << 4)
1766                   | ((bt & 0x1) << 3)
1767                   | ((bl & 0x7) << 0)
1768                   );
1769
1770         ddr->ddr_sdram_mode = (0
1771                                | ((esdmode & 0xFFFF) << 16)
1772                                | ((sdmode & 0xFFFF) << 0)
1773                                );
1774         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1775 }
1776 #endif
1777
1778 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1779 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1780 {
1781         unsigned int init_value;        /* Initialization value */
1782
1783 #ifdef CONFIG_MEM_INIT_VALUE
1784         init_value = CONFIG_MEM_INIT_VALUE;
1785 #else
1786         init_value = 0xDEADBEEF;
1787 #endif
1788         ddr->ddr_data_init = init_value;
1789 }
1790
1791 /*
1792  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1793  * The old controller on the 8540/60 doesn't have this register.
1794  * Hope it's OK to set it (to 0) anyway.
1795  */
1796 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1797                                          const memctl_options_t *popts)
1798 {
1799         unsigned int clk_adjust;        /* Clock adjust */
1800         unsigned int ss_en = 0;         /* Source synchronous enable */
1801
1802 #if defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555)
1803         /* Per FSL Application Note: AN2805 */
1804         ss_en = 1;
1805 #endif
1806         clk_adjust = popts->clk_adjust;
1807         ddr->ddr_sdram_clk_cntl = (0
1808                                    | ((ss_en & 0x1) << 31)
1809                                    | ((clk_adjust & 0xF) << 23)
1810                                    );
1811         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1812 }
1813
1814 /* DDR Initialization Address (DDR_INIT_ADDR) */
1815 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1816 {
1817         unsigned int init_addr = 0;     /* Initialization address */
1818
1819         ddr->ddr_init_addr = init_addr;
1820 }
1821
1822 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1823 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1824 {
1825         unsigned int uia = 0;   /* Use initialization address */
1826         unsigned int init_ext_addr = 0; /* Initialization address */
1827
1828         ddr->ddr_init_ext_addr = (0
1829                                   | ((uia & 0x1) << 31)
1830                                   | (init_ext_addr & 0xF)
1831                                   );
1832 }
1833
1834 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1835 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1836                                 const memctl_options_t *popts)
1837 {
1838         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1839         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1840         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1841         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1842         unsigned int trwt_mclk = 0;     /* ext_rwt */
1843         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1844
1845 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1846         if (popts->burst_length == DDR_BL8) {
1847                 /* We set BL/2 for fixed BL8 */
1848                 rrt = 0;        /* BL/2 clocks */
1849                 wwt = 0;        /* BL/2 clocks */
1850         } else {
1851                 /* We need to set BL/2 + 2 to BC4 and OTF */
1852                 rrt = 2;        /* BL/2 + 2 clocks */
1853                 wwt = 2;        /* BL/2 + 2 clocks */
1854         }
1855 #endif
1856 #ifdef CONFIG_SYS_FSL_DDR4
1857         dll_lock = 2;   /* tDLLK = 1024 clocks */
1858 #elif defined(CONFIG_SYS_FSL_DDR3)
1859         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1860 #endif
1861
1862         if (popts->trwt_override)
1863                 trwt_mclk = popts->trwt;
1864
1865         ddr->timing_cfg_4 = (0
1866                              | ((rwt & 0xf) << 28)
1867                              | ((wrt & 0xf) << 24)
1868                              | ((rrt & 0xf) << 20)
1869                              | ((wwt & 0xf) << 16)
1870                              | ((trwt_mclk & 0xc) << 12)
1871                              | (dll_lock & 0x3)
1872                              );
1873         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1874 }
1875
1876 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1877 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1878 {
1879         unsigned int rodt_on = 0;       /* Read to ODT on */
1880         unsigned int rodt_off = 0;      /* Read to ODT off */
1881         unsigned int wodt_on = 0;       /* Write to ODT on */
1882         unsigned int wodt_off = 0;      /* Write to ODT off */
1883
1884 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1885         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1886                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1887         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1888         if (cas_latency >= wr_lat)
1889                 rodt_on = cas_latency - wr_lat + 1;
1890         rodt_off = 4;   /*  4 clocks */
1891         wodt_on = 1;    /*  1 clocks */
1892         wodt_off = 4;   /*  4 clocks */
1893 #endif
1894
1895         ddr->timing_cfg_5 = (0
1896                              | ((rodt_on & 0x1f) << 24)
1897                              | ((rodt_off & 0x7) << 20)
1898                              | ((wodt_on & 0x1f) << 12)
1899                              | ((wodt_off & 0x7) << 8)
1900                              );
1901         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1902 }
1903
1904 #ifdef CONFIG_SYS_FSL_DDR4
1905 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1906 {
1907         unsigned int hs_caslat = 0;
1908         unsigned int hs_wrlat = 0;
1909         unsigned int hs_wrrec = 0;
1910         unsigned int hs_clkadj = 0;
1911         unsigned int hs_wrlvl_start = 0;
1912
1913         ddr->timing_cfg_6 = (0
1914                              | ((hs_caslat & 0x1f) << 24)
1915                              | ((hs_wrlat & 0x1f) << 19)
1916                              | ((hs_wrrec & 0x1f) << 12)
1917                              | ((hs_clkadj & 0x1f) << 6)
1918                              | ((hs_wrlvl_start & 0x1f) << 0)
1919                             );
1920         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1921 }
1922
1923 static void set_timing_cfg_7(const unsigned int ctrl_num,
1924                              fsl_ddr_cfg_regs_t *ddr,
1925                              const common_timing_params_t *common_dimm)
1926 {
1927         unsigned int txpr, tcksre, tcksrx;
1928         unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd;
1929
1930         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1931         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1932         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1933         par_lat = 0;
1934         cs_to_cmd = 0;
1935
1936         if (txpr <= 200)
1937                 cke_rst = 0;
1938         else if (txpr <= 256)
1939                 cke_rst = 1;
1940         else if (txpr <= 512)
1941                 cke_rst = 2;
1942         else
1943                 cke_rst = 3;
1944
1945         if (tcksre <= 19)
1946                 cksre = tcksre - 5;
1947         else
1948                 cksre = 15;
1949
1950         if (tcksrx <= 19)
1951                 cksrx = tcksrx - 5;
1952         else
1953                 cksrx = 15;
1954
1955         ddr->timing_cfg_7 = (0
1956                              | ((cke_rst & 0x3) << 28)
1957                              | ((cksre & 0xf) << 24)
1958                              | ((cksrx & 0xf) << 20)
1959                              | ((par_lat & 0xf) << 16)
1960                              | ((cs_to_cmd & 0xf) << 4)
1961                             );
1962         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
1963 }
1964
1965 static void set_timing_cfg_8(const unsigned int ctrl_num,
1966                              fsl_ddr_cfg_regs_t *ddr,
1967                              const memctl_options_t *popts,
1968                              const common_timing_params_t *common_dimm,
1969                              unsigned int cas_latency)
1970 {
1971         unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
1972         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
1973         unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1974         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1975                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1976
1977         rwt_bg = cas_latency + 2 + 4 - wr_lat;
1978         if (rwt_bg < tccdl)
1979                 rwt_bg = tccdl - rwt_bg;
1980         else
1981                 rwt_bg = 0;
1982
1983         wrt_bg = wr_lat + 4 + 1 - cas_latency;
1984         if (wrt_bg < tccdl)
1985                 wrt_bg = tccdl - wrt_bg;
1986         else
1987                 wrt_bg = 0;
1988
1989         if (popts->burst_length == DDR_BL8) {
1990                 rrt_bg = tccdl - 4;
1991                 wwt_bg = tccdl - 4;
1992         } else {
1993                 rrt_bg = tccdl - 2;
1994                 wwt_bg = tccdl - 2;
1995         }
1996
1997         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
1998         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
1999         if (popts->otf_burst_chop_en)
2000                 wrtord_bg += 2;
2001
2002         pre_all_rec = 0;
2003
2004         ddr->timing_cfg_8 = (0
2005                              | ((rwt_bg & 0xf) << 28)
2006                              | ((wrt_bg & 0xf) << 24)
2007                              | ((rrt_bg & 0xf) << 20)
2008                              | ((wwt_bg & 0xf) << 16)
2009                              | ((acttoact_bg & 0xf) << 12)
2010                              | ((wrtord_bg & 0xf) << 8)
2011                              | ((pre_all_rec & 0x1f) << 0)
2012                             );
2013
2014         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2015 }
2016
2017 static void set_timing_cfg_9(fsl_ddr_cfg_regs_t *ddr)
2018 {
2019         ddr->timing_cfg_9 = 0;
2020         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2021 }
2022
2023 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2024 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2025                                const dimm_params_t *dimm_params)
2026 {
2027         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2028         int i;
2029
2030         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2031                 if (dimm_params[i].n_ranks)
2032                         break;
2033         }
2034         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2035                 puts("DDR error: no DIMM found!\n");
2036                 return;
2037         }
2038
2039         ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2040                         ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2041                         ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2042                         ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2043                         ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2044
2045         ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2046                         ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2047                         ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2048                         ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2049                         ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2050
2051         ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2052                         ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2053                         ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2054                         ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2055                         ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2056
2057         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2058         ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2059                         ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2060                         (acc_ecc_en ? 0 :
2061                          (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2062                         dimm_params[i].dq_mapping_ors;
2063
2064         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2065         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2066         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2067         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2068 }
2069 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2070                                const memctl_options_t *popts)
2071 {
2072         int rd_pre;
2073
2074         rd_pre = popts->quad_rank_present ? 1 : 0;
2075
2076         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2077
2078         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2079 }
2080 #endif  /* CONFIG_SYS_FSL_DDR4 */
2081
2082 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2083 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2084 {
2085         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2086         /* Normal Operation Full Calibration Time (tZQoper) */
2087         unsigned int zqoper = 0;
2088         /* Normal Operation Short Calibration Time (tZQCS) */
2089         unsigned int zqcs = 0;
2090 #ifdef CONFIG_SYS_FSL_DDR4
2091         unsigned int zqcs_init;
2092 #endif
2093
2094         if (zq_en) {
2095 #ifdef CONFIG_SYS_FSL_DDR4
2096                 zqinit = 10;    /* 1024 clocks */
2097                 zqoper = 9;     /* 512 clocks */
2098                 zqcs = 7;       /* 128 clocks */
2099                 zqcs_init = 5;  /* 1024 refresh sequences */
2100 #else
2101                 zqinit = 9;     /* 512 clocks */
2102                 zqoper = 8;     /* 256 clocks */
2103                 zqcs = 6;       /* 64 clocks */
2104 #endif
2105         }
2106
2107         ddr->ddr_zq_cntl = (0
2108                             | ((zq_en & 0x1) << 31)
2109                             | ((zqinit & 0xF) << 24)
2110                             | ((zqoper & 0xF) << 16)
2111                             | ((zqcs & 0xF) << 8)
2112 #ifdef CONFIG_SYS_FSL_DDR4
2113                             | ((zqcs_init & 0xF) << 0)
2114 #endif
2115                             );
2116         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2117 }
2118
2119 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2120 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2121                                 const memctl_options_t *popts)
2122 {
2123         /*
2124          * First DQS pulse rising edge after margining mode
2125          * is programmed (tWL_MRD)
2126          */
2127         unsigned int wrlvl_mrd = 0;
2128         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2129         unsigned int wrlvl_odten = 0;
2130         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2131         unsigned int wrlvl_dqsen = 0;
2132         /* WRLVL_SMPL: Write leveling sample time */
2133         unsigned int wrlvl_smpl = 0;
2134         /* WRLVL_WLR: Write leveling repeition time */
2135         unsigned int wrlvl_wlr = 0;
2136         /* WRLVL_START: Write leveling start time */
2137         unsigned int wrlvl_start = 0;
2138
2139         /* suggest enable write leveling for DDR3 due to fly-by topology */
2140         if (wrlvl_en) {
2141                 /* tWL_MRD min = 40 nCK, we set it 64 */
2142                 wrlvl_mrd = 0x6;
2143                 /* tWL_ODTEN 128 */
2144                 wrlvl_odten = 0x7;
2145                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2146                 wrlvl_dqsen = 0x5;
2147                 /*
2148                  * Write leveling sample time at least need 6 clocks
2149                  * higher than tWLO to allow enough time for progagation
2150                  * delay and sampling the prime data bits.
2151                  */
2152                 wrlvl_smpl = 0xf;
2153                 /*
2154                  * Write leveling repetition time
2155                  * at least tWLO + 6 clocks clocks
2156                  * we set it 64
2157                  */
2158                 wrlvl_wlr = 0x6;
2159                 /*
2160                  * Write leveling start time
2161                  * The value use for the DQS_ADJUST for the first sample
2162                  * when write leveling is enabled. It probably needs to be
2163                  * overriden per platform.
2164                  */
2165                 wrlvl_start = 0x8;
2166                 /*
2167                  * Override the write leveling sample and start time
2168                  * according to specific board
2169                  */
2170                 if (popts->wrlvl_override) {
2171                         wrlvl_smpl = popts->wrlvl_sample;
2172                         wrlvl_start = popts->wrlvl_start;
2173                 }
2174         }
2175
2176         ddr->ddr_wrlvl_cntl = (0
2177                                | ((wrlvl_en & 0x1) << 31)
2178                                | ((wrlvl_mrd & 0x7) << 24)
2179                                | ((wrlvl_odten & 0x7) << 20)
2180                                | ((wrlvl_dqsen & 0x7) << 16)
2181                                | ((wrlvl_smpl & 0xf) << 12)
2182                                | ((wrlvl_wlr & 0x7) << 8)
2183                                | ((wrlvl_start & 0x1F) << 0)
2184                                );
2185         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2186         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2187         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2188         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2189         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2190
2191 }
2192
2193 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2194 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2195 {
2196         /* Self Refresh Idle Threshold */
2197         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2198 }
2199
2200 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2201 {
2202         if (popts->addr_hash) {
2203                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2204                 puts("Address hashing enabled.\n");
2205         }
2206 }
2207
2208 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2209 {
2210         ddr->ddr_cdr1 = popts->ddr_cdr1;
2211         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2212 }
2213
2214 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2215 {
2216         ddr->ddr_cdr2 = popts->ddr_cdr2;
2217         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2218 }
2219
2220 unsigned int
2221 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2222 {
2223         unsigned int res = 0;
2224
2225         /*
2226          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2227          * not set at the same time.
2228          */
2229         if (ddr->ddr_sdram_cfg & 0x10000000
2230             && ddr->ddr_sdram_cfg & 0x00008000) {
2231                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2232                                 " should not be set at the same time.\n");
2233                 res++;
2234         }
2235
2236         return res;
2237 }
2238
2239 unsigned int
2240 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2241                                const memctl_options_t *popts,
2242                                fsl_ddr_cfg_regs_t *ddr,
2243                                const common_timing_params_t *common_dimm,
2244                                const dimm_params_t *dimm_params,
2245                                unsigned int dbw_cap_adj,
2246                                unsigned int size_only)
2247 {
2248         unsigned int i;
2249         unsigned int cas_latency;
2250         unsigned int additive_latency;
2251         unsigned int sr_it;
2252         unsigned int zq_en;
2253         unsigned int wrlvl_en;
2254         unsigned int ip_rev = 0;
2255         unsigned int unq_mrs_en = 0;
2256         int cs_en = 1;
2257
2258         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2259
2260         if (common_dimm == NULL) {
2261                 printf("Error: subset DIMM params struct null pointer\n");
2262                 return 1;
2263         }
2264
2265         /*
2266          * Process overrides first.
2267          *
2268          * FIXME: somehow add dereated caslat to this
2269          */
2270         cas_latency = (popts->cas_latency_override)
2271                 ? popts->cas_latency_override_value
2272                 : common_dimm->lowest_common_spd_caslat;
2273
2274         additive_latency = (popts->additive_latency_override)
2275                 ? popts->additive_latency_override_value
2276                 : common_dimm->additive_latency;
2277
2278         sr_it = (popts->auto_self_refresh_en)
2279                 ? popts->sr_it
2280                 : 0;
2281         /* ZQ calibration */
2282         zq_en = (popts->zq_en) ? 1 : 0;
2283         /* write leveling */
2284         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2285
2286         /* Chip Select Memory Bounds (CSn_BNDS) */
2287         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2288                 unsigned long long ea, sa;
2289                 unsigned int cs_per_dimm
2290                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2291                 unsigned int dimm_number
2292                         = i / cs_per_dimm;
2293                 unsigned long long rank_density
2294                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2295
2296                 if (dimm_params[dimm_number].n_ranks == 0) {
2297                         debug("Skipping setup of CS%u "
2298                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2299                         continue;
2300                 }
2301                 if (popts->memctl_interleaving) {
2302                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2303                         case FSL_DDR_CS0_CS1_CS2_CS3:
2304                                 break;
2305                         case FSL_DDR_CS0_CS1:
2306                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2307                                 if (i > 1)
2308                                         cs_en = 0;
2309                                 break;
2310                         case FSL_DDR_CS2_CS3:
2311                         default:
2312                                 if (i > 0)
2313                                         cs_en = 0;
2314                                 break;
2315                         }
2316                         sa = common_dimm->base_address;
2317                         ea = sa + common_dimm->total_mem - 1;
2318                 } else if (!popts->memctl_interleaving) {
2319                         /*
2320                          * If memory interleaving between controllers is NOT
2321                          * enabled, the starting address for each memory
2322                          * controller is distinct.  However, because rank
2323                          * interleaving is enabled, the starting and ending
2324                          * addresses of the total memory on that memory
2325                          * controller needs to be programmed into its
2326                          * respective CS0_BNDS.
2327                          */
2328                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2329                         case FSL_DDR_CS0_CS1_CS2_CS3:
2330                                 sa = common_dimm->base_address;
2331                                 ea = sa + common_dimm->total_mem - 1;
2332                                 break;
2333                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2334                                 if ((i >= 2) && (dimm_number == 0)) {
2335                                         sa = dimm_params[dimm_number].base_address +
2336                                               2 * rank_density;
2337                                         ea = sa + 2 * rank_density - 1;
2338                                 } else {
2339                                         sa = dimm_params[dimm_number].base_address;
2340                                         ea = sa + 2 * rank_density - 1;
2341                                 }
2342                                 break;
2343                         case FSL_DDR_CS0_CS1:
2344                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2345                                         sa = dimm_params[dimm_number].base_address;
2346                                         ea = sa + rank_density - 1;
2347                                         if (i != 1)
2348                                                 sa += (i % cs_per_dimm) * rank_density;
2349                                         ea += (i % cs_per_dimm) * rank_density;
2350                                 } else {
2351                                         sa = 0;
2352                                         ea = 0;
2353                                 }
2354                                 if (i == 0)
2355                                         ea += rank_density;
2356                                 break;
2357                         case FSL_DDR_CS2_CS3:
2358                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2359                                         sa = dimm_params[dimm_number].base_address;
2360                                         ea = sa + rank_density - 1;
2361                                         if (i != 3)
2362                                                 sa += (i % cs_per_dimm) * rank_density;
2363                                         ea += (i % cs_per_dimm) * rank_density;
2364                                 } else {
2365                                         sa = 0;
2366                                         ea = 0;
2367                                 }
2368                                 if (i == 2)
2369                                         ea += (rank_density >> dbw_cap_adj);
2370                                 break;
2371                         default:  /* No bank(chip-select) interleaving */
2372                                 sa = dimm_params[dimm_number].base_address;
2373                                 ea = sa + rank_density - 1;
2374                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2375                                         sa += (i % cs_per_dimm) * rank_density;
2376                                         ea += (i % cs_per_dimm) * rank_density;
2377                                 } else {
2378                                         sa = 0;
2379                                         ea = 0;
2380                                 }
2381                                 break;
2382                         }
2383                 }
2384
2385                 sa >>= 24;
2386                 ea >>= 24;
2387
2388                 if (cs_en) {
2389                         ddr->cs[i].bnds = (0
2390                                 | ((sa & 0xffff) << 16) /* starting address */
2391                                 | ((ea & 0xffff) << 0)  /* ending address */
2392                                 );
2393                 } else {
2394                         /* setting bnds to 0xffffffff for inactive CS */
2395                         ddr->cs[i].bnds = 0xffffffff;
2396                 }
2397
2398                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2399                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2400                 set_csn_config_2(i, ddr);
2401         }
2402
2403         /*
2404          * In the case we only need to compute the ddr sdram size, we only need
2405          * to set csn registers, so return from here.
2406          */
2407         if (size_only)
2408                 return 0;
2409
2410         set_ddr_eor(ddr, popts);
2411
2412 #if !defined(CONFIG_SYS_FSL_DDR1)
2413         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2414 #endif
2415
2416         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2417                          additive_latency);
2418         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2419         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2420                          cas_latency, additive_latency);
2421
2422         set_ddr_cdr1(ddr, popts);
2423         set_ddr_cdr2(ddr, popts);
2424         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2425         ip_rev = fsl_ddr_get_version(ctrl_num);
2426         if (ip_rev > 0x40400)
2427                 unq_mrs_en = 1;
2428
2429         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2430                 ddr->debug[18] = popts->cswl_override;
2431
2432         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2433         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2434                            cas_latency, additive_latency, unq_mrs_en);
2435         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2436 #ifdef CONFIG_SYS_FSL_DDR4
2437         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2438         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2439 #endif
2440         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2441         set_ddr_data_init(ddr);
2442         set_ddr_sdram_clk_cntl(ddr, popts);
2443         set_ddr_init_addr(ddr);
2444         set_ddr_init_ext_addr(ddr);
2445         set_timing_cfg_4(ddr, popts);
2446         set_timing_cfg_5(ddr, cas_latency);
2447 #ifdef CONFIG_SYS_FSL_DDR4
2448         set_ddr_sdram_cfg_3(ddr, popts);
2449         set_timing_cfg_6(ddr);
2450         set_timing_cfg_7(ctrl_num, ddr, common_dimm);
2451         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2452         set_timing_cfg_9(ddr);
2453         set_ddr_dq_mapping(ddr, dimm_params);
2454 #endif
2455
2456         set_ddr_zq_cntl(ddr, zq_en);
2457         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2458
2459         set_ddr_sr_cntr(ddr, sr_it);
2460
2461         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2462
2463 #ifdef CONFIG_SYS_FSL_DDR_EMU
2464         /* disble DDR training for emulator */
2465         ddr->debug[2] = 0x00000400;
2466         ddr->debug[4] = 0xff800800;
2467         ddr->debug[5] = 0x08000800;
2468         ddr->debug[6] = 0x08000800;
2469         ddr->debug[7] = 0x08000800;
2470         ddr->debug[8] = 0x08000800;
2471 #endif
2472 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2473         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2474                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2475 #endif
2476
2477         return check_fsl_memctl_config_regs(ddr);
2478 }