2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
17 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
20 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
22 static struct socfpga_sdr_reg_file *sdr_reg_file =
23 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
25 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
26 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
28 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
29 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
31 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
32 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
34 static struct socfpga_data_mgr *data_mgr =
35 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
55 #define STATIC_IN_RTL_SIM 0
56 #define STATIC_SKIP_DELAY_LOOPS 0
58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
61 /* calibration steps requested by the rtl */
62 uint16_t dyn_calib_steps;
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
69 * The mask is set to include all bits when not-skipping, but is
73 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
79 struct param_type *param;
80 uint32_t curr_shadow_reg;
82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
83 uint32_t write_group, uint32_t use_dm,
84 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86 static void set_failing_group_stage(uint32_t group, uint32_t stage,
90 * Only set the global stage if there was not been any other
93 if (gbl->error_stage == CAL_STAGE_NIL) {
94 gbl->error_substage = substage;
95 gbl->error_stage = stage;
96 gbl->error_group = group;
100 static void reg_file_set_group(u16 set_group)
102 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
105 static void reg_file_set_stage(u8 set_stage)
107 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
110 static void reg_file_set_sub_stage(u8 set_sub_stage)
112 set_sub_stage &= 0xff;
113 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
116 static void initialize(void)
118 debug("%s:%d\n", __func__, __LINE__);
119 /* USER calibration has control over path to memory */
121 * In Hard PHY this is a 2-bit control:
125 writel(0x3, &phy_mgr_cfg->mux_sel);
127 /* USER memory clock is not stable we begin initialization */
128 writel(0, &phy_mgr_cfg->reset_mem_stbl);
130 /* USER calibration status all set to zero */
131 writel(0, &phy_mgr_cfg->cal_status);
133 writel(0, &phy_mgr_cfg->cal_debug_info);
135 if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
136 param->read_correct_mask_vg = ((uint32_t)1 <<
137 (RW_MGR_MEM_DQ_PER_READ_DQS /
138 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
139 param->write_correct_mask_vg = ((uint32_t)1 <<
140 (RW_MGR_MEM_DQ_PER_READ_DQS /
141 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
142 param->read_correct_mask = ((uint32_t)1 <<
143 RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
144 param->write_correct_mask = ((uint32_t)1 <<
145 RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
146 param->dm_correct_mask = ((uint32_t)1 <<
147 (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
152 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
154 uint32_t odt_mask_0 = 0;
155 uint32_t odt_mask_1 = 0;
156 uint32_t cs_and_odt_mask;
158 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
159 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
167 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
169 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
170 /* - Dual-Slot , Single-Rank
171 * (1 chip-select per DIMM)
173 * - RDIMM, 4 total CS (2 CS per DIMM)
175 * Since MEM_NUMBER_OF_RANKS is 2 they are
177 * with 2 CS each (special for RDIMM)
178 * Read: Turn on ODT on the opposite rank
179 * Write: Turn on ODT on all ranks
181 odt_mask_0 = 0x3 & ~(1 << rank);
185 * USER - Single-Slot , Dual-rank DIMMs
186 * (2 chip-selects per DIMM)
187 * USER Read: Turn on ODT off on all ranks
188 * USER Write: Turn on ODT on active rank
191 odt_mask_1 = 0x3 & (1 << rank);
196 * ----------+-----------------------+
199 * Read From +-----------------------+
200 * Rank | 3 | 2 | 1 | 0 |
201 * ----------+-----+-----+-----+-----+
202 * 0 | 0 | 1 | 0 | 0 |
203 * 1 | 1 | 0 | 0 | 0 |
204 * 2 | 0 | 0 | 0 | 1 |
205 * 3 | 0 | 0 | 1 | 0 |
206 * ----------+-----+-----+-----+-----+
209 * ----------+-----------------------+
212 * Write To +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 1 |
216 * 1 | 1 | 0 | 1 | 0 |
217 * 2 | 0 | 1 | 0 | 1 |
218 * 3 | 1 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
246 (0xFF & ~(1 << rank)) |
247 ((0xFF & odt_mask_0) << 8) |
248 ((0xFF & odt_mask_1) << 16);
249 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
250 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
254 * scc_mgr_set() - Set SCC Manager register
255 * @off: Base offset in SCC Manager space
256 * @grp: Read/Write group
257 * @val: Value to be set
259 * This function sets the SCC Manager (Scan Chain Control Manager) register.
261 static void scc_mgr_set(u32 off, u32 grp, u32 val)
263 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
267 * scc_mgr_initialize() - Initialize SCC Manager registers
269 * Initialize SCC Manager registers.
271 static void scc_mgr_initialize(void)
274 * Clear register file for HPS. 16 (2^4) is the size of the
275 * full register file in the scc mgr:
276 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
277 * MEM_IF_READ_DQS_WIDTH - 1);
281 for (i = 0; i < 16; i++) {
282 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
283 __func__, __LINE__, i);
284 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
288 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
290 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
293 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
295 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
298 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
300 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
303 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
305 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
308 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
310 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
314 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
316 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
319 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
330 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
332 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
333 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
337 /* load up dqs config settings */
338 static void scc_mgr_load_dqs(uint32_t dqs)
340 writel(dqs, &sdr_scc_mgr->dqs_ena);
343 /* load up dqs io config settings */
344 static void scc_mgr_load_dqs_io(void)
346 writel(0, &sdr_scc_mgr->dqs_io_ena);
349 /* load up dq config settings */
350 static void scc_mgr_load_dq(uint32_t dq_in_group)
352 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
355 /* load up dm config settings */
356 static void scc_mgr_load_dm(uint32_t dm)
358 writel(dm, &sdr_scc_mgr->dm_ena);
362 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
363 * @off: Base offset in SCC Manager space
364 * @grp: Read/Write group
365 * @val: Value to be set
366 * @update: If non-zero, trigger SCC Manager update for all ranks
368 * This function sets the SCC Manager (Scan Chain Control Manager) register
369 * and optionally triggers the SCC update for all ranks.
371 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
376 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
377 r += NUM_RANKS_PER_SHADOW_REG) {
378 scc_mgr_set(off, grp, val);
380 if (update || (r == 0)) {
381 writel(grp, &sdr_scc_mgr->dqs_ena);
382 writel(0, &sdr_scc_mgr->update);
387 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
390 * USER although the h/w doesn't support different phases per
391 * shadow register, for simplicity our scc manager modeling
392 * keeps different phase settings per shadow reg, and it's
393 * important for us to keep them in sync to match h/w.
394 * for efficiency, the scan chain update should occur only
397 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
398 read_group, phase, 0);
401 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
405 * USER although the h/w doesn't support different phases per
406 * shadow register, for simplicity our scc manager modeling
407 * keeps different phase settings per shadow reg, and it's
408 * important for us to keep them in sync to match h/w.
409 * for efficiency, the scan chain update should occur only
412 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
413 write_group, phase, 0);
416 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
420 * In shadow register mode, the T11 settings are stored in
421 * registers in the core, which are updated by the DQS_ENA
422 * signals. Not issuing the SCC_MGR_UPD command allows us to
423 * save lots of rank switching overhead, by calling
424 * select_shadow_regs_for_update with update_scan_chains
427 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
428 read_group, delay, 1);
429 writel(0, &sdr_scc_mgr->update);
433 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
434 * @write_group: Write group
435 * @delay: Delay value
437 * This function sets the OCT output delay in SCC manager.
439 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
441 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
442 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
443 const int base = write_group * ratio;
446 * Load the setting in the SCC manager
447 * Although OCT affects only write data, the OCT delay is controlled
448 * by the DQS logic block which is instantiated once per read group.
449 * For protocols where a write group consists of multiple read groups,
450 * the setting must be set multiple times.
452 for (i = 0; i < ratio; i++)
453 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
457 * scc_mgr_set_hhp_extras() - Set HHP extras.
459 * Load the fixed setting in the SCC manager HHP extras.
461 static void scc_mgr_set_hhp_extras(void)
464 * Load the fixed setting in the SCC manager
465 * bits: 0:0 = 1'b1 - DQS bypass
466 * bits: 1:1 = 1'b1 - DQ bypass
467 * bits: 4:2 = 3'b001 - rfifo_mode
468 * bits: 6:5 = 2'b01 - rfifo clock_select
469 * bits: 7:7 = 1'b0 - separate gating from ungating setting
470 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
472 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
473 (1 << 2) | (1 << 1) | (1 << 0);
474 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
475 SCC_MGR_HHP_GLOBALS_OFFSET |
476 SCC_MGR_HHP_EXTRAS_OFFSET;
478 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
481 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
486 * USER Zero all DQS config
487 * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
489 static void scc_mgr_zero_all(void)
494 * USER Zero all DQS config settings, across all groups and all
497 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
498 NUM_RANKS_PER_SHADOW_REG) {
499 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
501 * The phases actually don't exist on a per-rank basis,
502 * but there's no harm updating them several times, so
503 * let's keep the code simple.
505 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
506 scc_mgr_set_dqs_en_phase(i, 0);
507 scc_mgr_set_dqs_en_delay(i, 0);
510 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
511 scc_mgr_set_dqdqs_output_phase(i, 0);
512 /* av/cv don't have out2 */
513 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
517 /* multicast to all DQS group enables */
518 writel(0xff, &sdr_scc_mgr->dqs_ena);
519 writel(0, &sdr_scc_mgr->update);
523 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
524 * @write_group: Write group
526 * Set bypass mode and trigger SCC update.
528 static void scc_set_bypass_mode(const u32 write_group)
530 /* Multicast to all DQ enables. */
531 writel(0xff, &sdr_scc_mgr->dq_ena);
532 writel(0xff, &sdr_scc_mgr->dm_ena);
534 /* Update current DQS IO enable. */
535 writel(0, &sdr_scc_mgr->dqs_io_ena);
537 /* Update the DQS logic. */
538 writel(write_group, &sdr_scc_mgr->dqs_ena);
541 writel(0, &sdr_scc_mgr->update);
545 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
546 * @write_group: Write group
548 * Load DQS settings for Write Group, do not trigger SCC update.
550 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
552 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
553 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
554 const int base = write_group * ratio;
557 * Load the setting in the SCC manager
558 * Although OCT affects only write data, the OCT delay is controlled
559 * by the DQS logic block which is instantiated once per read group.
560 * For protocols where a write group consists of multiple read groups,
561 * the setting must be set multiple times.
563 for (i = 0; i < ratio; i++)
564 writel(base + i, &sdr_scc_mgr->dqs_ena);
567 static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
572 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
573 NUM_RANKS_PER_SHADOW_REG) {
574 /* Zero all DQ config settings */
575 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
576 scc_mgr_set_dq_out1_delay(i, 0);
578 scc_mgr_set_dq_in_delay(i, 0);
581 /* multicast to all DQ enables */
582 writel(0xff, &sdr_scc_mgr->dq_ena);
584 /* Zero all DM config settings */
585 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
586 scc_mgr_set_dm_out1_delay(i, 0);
589 /* multicast to all DM enables */
590 writel(0xff, &sdr_scc_mgr->dm_ena);
592 /* zero all DQS io settings */
594 scc_mgr_set_dqs_io_in_delay(0);
595 /* av/cv don't have out2 */
596 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
597 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
598 scc_mgr_load_dqs_for_write_group(write_group);
600 /* multicast to all DQS IO enables (only 1) */
601 writel(0, &sdr_scc_mgr->dqs_io_ena);
603 /* hit update to zero everything */
604 writel(0, &sdr_scc_mgr->update);
609 * apply and load a particular input delay for the DQ pins in a group
610 * group_bgn is the index of the first dq pin (in the write group)
612 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
616 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
617 scc_mgr_set_dq_in_delay(p, delay);
623 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
624 * @delay: Delay value
626 * Apply and load a particular output delay for the DQ pins in a group.
628 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
632 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
633 scc_mgr_set_dq_out1_delay(i, delay);
638 /* apply and load a particular output delay for the DM pins in a group */
639 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
643 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
644 scc_mgr_set_dm_out1_delay(i, delay1);
650 /* apply and load delay on both DQS and OCT out1 */
651 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
654 scc_mgr_set_dqs_out1_delay(delay);
655 scc_mgr_load_dqs_io();
657 scc_mgr_set_oct_out1_delay(write_group, delay);
658 scc_mgr_load_dqs_for_write_group(write_group);
661 /* apply a delay to the entire output side: DQ, DM, DQS, OCT */
662 static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
666 uint32_t i, p, new_delay;
669 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
670 new_delay = READ_SCC_DQ_OUT2_DELAY;
673 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
674 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
675 %u > %lu => %lu", __func__, __LINE__,
676 write_group, group_bgn, delay, i, p, new_delay,
677 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
678 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
679 new_delay = IO_IO_OUT2_DELAY_MAX;
686 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
687 new_delay = READ_SCC_DM_IO_OUT2_DELAY;
690 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
691 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
692 %u > %lu => %lu\n", __func__, __LINE__,
693 write_group, group_bgn, delay, i, new_delay,
694 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
695 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
696 new_delay = IO_IO_OUT2_DELAY_MAX;
703 new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
706 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
707 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
708 " adding %u to OUT1\n", __func__, __LINE__,
709 write_group, group_bgn, delay, new_delay,
710 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
711 new_delay - IO_IO_OUT2_DELAY_MAX);
712 scc_mgr_set_dqs_out1_delay(new_delay -
713 IO_IO_OUT2_DELAY_MAX);
714 new_delay = IO_IO_OUT2_DELAY_MAX;
717 scc_mgr_load_dqs_io();
720 new_delay = READ_SCC_OCT_OUT2_DELAY;
723 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
724 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
725 " adding %u to OUT1\n", __func__, __LINE__,
726 write_group, group_bgn, delay, new_delay,
727 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
728 new_delay - IO_IO_OUT2_DELAY_MAX);
729 scc_mgr_set_oct_out1_delay(write_group, new_delay -
730 IO_IO_OUT2_DELAY_MAX);
731 new_delay = IO_IO_OUT2_DELAY_MAX;
734 scc_mgr_load_dqs_for_write_group(write_group);
738 * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
741 static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
742 uint32_t write_group, uint32_t group_bgn, uint32_t delay)
746 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
747 r += NUM_RANKS_PER_SHADOW_REG) {
748 scc_mgr_apply_group_all_out_delay_add(write_group,
750 writel(0, &sdr_scc_mgr->update);
754 /* optimization used to recover some slots in ddr3 inst_rom */
755 /* could be applied to other protocols if we wanted to */
756 static void set_jump_as_return(void)
759 * to save space, we replace return with jump to special shared
760 * RETURN instruction so we set the counter to large value so that
763 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
764 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
768 * should always use constants as argument to ensure all computations are
769 * performed at compile time
771 static void delay_for_n_mem_clocks(const uint32_t clocks)
778 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
781 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
782 /* scale (rounding up) to get afi clocks */
785 * Note, we don't bother accounting for being off a little bit
786 * because of a few extra instructions in outer loops
787 * Note, the loops have a test at the end, and do the test before
788 * the decrement, and so always perform the loop
789 * 1 time more than the counter value
791 if (afi_clocks == 0) {
793 } else if (afi_clocks <= 0x100) {
794 inner = afi_clocks-1;
797 } else if (afi_clocks <= 0x10000) {
799 outer = (afi_clocks-1) >> 8;
804 c_loop = (afi_clocks-1) >> 16;
808 * rom instructions are structured as follows:
810 * IDLE_LOOP2: jnz cntr0, TARGET_A
811 * IDLE_LOOP1: jnz cntr1, TARGET_B
814 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
815 * TARGET_B is set to IDLE_LOOP2 as well
817 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
818 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
820 * a little confusing, but it helps save precious space in the inst_rom
821 * and sequencer rom and keeps the delays more accurate and reduces
824 if (afi_clocks <= 0x100) {
825 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
826 &sdr_rw_load_mgr_regs->load_cntr1);
828 writel(RW_MGR_IDLE_LOOP1,
829 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
831 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
832 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
834 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
835 &sdr_rw_load_mgr_regs->load_cntr0);
837 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
838 &sdr_rw_load_mgr_regs->load_cntr1);
840 writel(RW_MGR_IDLE_LOOP2,
841 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
843 writel(RW_MGR_IDLE_LOOP2,
844 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
846 /* hack to get around compiler not being smart enough */
847 if (afi_clocks <= 0x10000) {
848 /* only need to run once */
849 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
850 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
853 writel(RW_MGR_IDLE_LOOP2,
854 SDR_PHYGRP_RWMGRGRP_ADDRESS |
855 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
856 } while (c_loop-- != 0);
859 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
862 static void rw_mgr_mem_initialize(void)
865 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
866 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
868 debug("%s:%d\n", __func__, __LINE__);
870 /* The reset / cke part of initialization is broadcasted to all ranks */
871 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
872 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
875 * Here's how you load register for a loop
876 * Counters are located @ 0x800
877 * Jump address are located @ 0xC00
878 * For both, registers 0 to 3 are selected using bits 3 and 2, like
879 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
880 * I know this ain't pretty, but Avalon bus throws away the 2 least
884 /* start with memory RESET activated */
889 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
890 * If a and b are the number of iteration in 2 nested loops
891 * it takes the following number of cycles to complete the operation:
892 * number_of_cycles = ((2 + n) * a + 2) * b
893 * where n is the number of instruction in the inner loop
894 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
899 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
900 &sdr_rw_load_mgr_regs->load_cntr0);
901 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
902 &sdr_rw_load_mgr_regs->load_cntr1);
903 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
904 &sdr_rw_load_mgr_regs->load_cntr2);
906 /* Load jump address */
907 writel(RW_MGR_INIT_RESET_0_CKE_0,
908 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
909 writel(RW_MGR_INIT_RESET_0_CKE_0,
910 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
911 writel(RW_MGR_INIT_RESET_0_CKE_0,
912 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
914 /* Execute count instruction */
915 writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
917 /* indicate that memory is stable */
918 writel(1, &phy_mgr_cfg->reset_mem_stbl);
921 * transition the RESET to high
926 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
927 * If a and b are the number of iteration in 2 nested loops
928 * it takes the following number of cycles to complete the operation
929 * number_of_cycles = ((2 + n) * a + 2) * b
930 * where n is the number of instruction in the inner loop
931 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
936 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
937 &sdr_rw_load_mgr_regs->load_cntr0);
938 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
939 &sdr_rw_load_mgr_regs->load_cntr1);
940 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
941 &sdr_rw_load_mgr_regs->load_cntr2);
943 /* Load jump address */
944 writel(RW_MGR_INIT_RESET_1_CKE_0,
945 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
946 writel(RW_MGR_INIT_RESET_1_CKE_0,
947 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
948 writel(RW_MGR_INIT_RESET_1_CKE_0,
949 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
951 writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
953 /* bring up clock enable */
955 /* tXRP < 250 ck cycles */
956 delay_for_n_mem_clocks(250);
958 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
959 if (param->skip_ranks[r]) {
960 /* request to skip the rank */
965 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
968 * USER Use Mirror-ed commands for odd ranks if address
971 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
972 set_jump_as_return();
973 writel(RW_MGR_MRS2_MIRR, grpaddr);
974 delay_for_n_mem_clocks(4);
975 set_jump_as_return();
976 writel(RW_MGR_MRS3_MIRR, grpaddr);
977 delay_for_n_mem_clocks(4);
978 set_jump_as_return();
979 writel(RW_MGR_MRS1_MIRR, grpaddr);
980 delay_for_n_mem_clocks(4);
981 set_jump_as_return();
982 writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
984 set_jump_as_return();
985 writel(RW_MGR_MRS2, grpaddr);
986 delay_for_n_mem_clocks(4);
987 set_jump_as_return();
988 writel(RW_MGR_MRS3, grpaddr);
989 delay_for_n_mem_clocks(4);
990 set_jump_as_return();
991 writel(RW_MGR_MRS1, grpaddr);
992 set_jump_as_return();
993 writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
995 set_jump_as_return();
996 writel(RW_MGR_ZQCL, grpaddr);
998 /* tZQinit = tDLLK = 512 ck cycles */
999 delay_for_n_mem_clocks(512);
1004 * At the end of calibration we have to program the user settings in, and
1005 * USER hand off the memory to the user.
1007 static void rw_mgr_mem_handoff(void)
1010 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1011 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1013 debug("%s:%d\n", __func__, __LINE__);
1014 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
1015 if (param->skip_ranks[r])
1016 /* request to skip the rank */
1019 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1021 /* precharge all banks ... */
1022 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
1024 /* load up MR settings specified by user */
1027 * Use Mirror-ed commands for odd ranks if address
1030 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1031 set_jump_as_return();
1032 writel(RW_MGR_MRS2_MIRR, grpaddr);
1033 delay_for_n_mem_clocks(4);
1034 set_jump_as_return();
1035 writel(RW_MGR_MRS3_MIRR, grpaddr);
1036 delay_for_n_mem_clocks(4);
1037 set_jump_as_return();
1038 writel(RW_MGR_MRS1_MIRR, grpaddr);
1039 delay_for_n_mem_clocks(4);
1040 set_jump_as_return();
1041 writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
1043 set_jump_as_return();
1044 writel(RW_MGR_MRS2, grpaddr);
1045 delay_for_n_mem_clocks(4);
1046 set_jump_as_return();
1047 writel(RW_MGR_MRS3, grpaddr);
1048 delay_for_n_mem_clocks(4);
1049 set_jump_as_return();
1050 writel(RW_MGR_MRS1, grpaddr);
1051 delay_for_n_mem_clocks(4);
1052 set_jump_as_return();
1053 writel(RW_MGR_MRS0_USER, grpaddr);
1056 * USER need to wait tMOD (12CK or 15ns) time before issuing
1057 * other commands, but we will have plenty of NIOS cycles before
1058 * actual handoff so its okay.
1064 * performs a guaranteed read on the patterns we are going to use during a
1065 * read test to ensure memory works
1067 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1068 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1072 uint32_t correct_mask_vg;
1073 uint32_t tmp_bit_chk;
1074 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1075 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1077 uint32_t base_rw_mgr;
1079 *bit_chk = param->read_correct_mask;
1080 correct_mask_vg = param->read_correct_mask_vg;
1082 for (r = rank_bgn; r < rank_end; r++) {
1083 if (param->skip_ranks[r])
1084 /* request to skip the rank */
1088 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1090 /* Load up a constant bursts of read commands */
1091 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1092 writel(RW_MGR_GUARANTEED_READ,
1093 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1095 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1096 writel(RW_MGR_GUARANTEED_READ_CONT,
1097 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1100 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1101 /* reset the fifos to get pointers to known state */
1103 writel(0, &phy_mgr_cmd->fifo_reset);
1104 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1105 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1107 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1108 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1110 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1111 writel(RW_MGR_GUARANTEED_READ, addr +
1112 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1115 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1116 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1121 *bit_chk &= tmp_bit_chk;
1124 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1125 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1127 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1128 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1129 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1130 (long unsigned int)(*bit_chk == param->read_correct_mask));
1131 return *bit_chk == param->read_correct_mask;
1134 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1135 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1137 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1138 num_tries, bit_chk, 1);
1141 /* load up the patterns we are going to use during a read test */
1142 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1146 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1147 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1149 debug("%s:%d\n", __func__, __LINE__);
1150 for (r = rank_bgn; r < rank_end; r++) {
1151 if (param->skip_ranks[r])
1152 /* request to skip the rank */
1156 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1158 /* Load up a constant bursts */
1159 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1161 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1162 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1164 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1166 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1167 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1169 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1171 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1172 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1174 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1176 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1177 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1179 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1180 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1183 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1187 * try a read and see if it returns correct data back. has dummy reads
1188 * inserted into the mix used to align dqs enable. has more thorough checks
1189 * than the regular read test.
1191 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1192 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1193 uint32_t all_groups, uint32_t all_ranks)
1196 uint32_t correct_mask_vg;
1197 uint32_t tmp_bit_chk;
1198 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1199 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1201 uint32_t base_rw_mgr;
1203 *bit_chk = param->read_correct_mask;
1204 correct_mask_vg = param->read_correct_mask_vg;
1206 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1207 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1209 for (r = rank_bgn; r < rank_end; r++) {
1210 if (param->skip_ranks[r])
1211 /* request to skip the rank */
1215 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1217 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1219 writel(RW_MGR_READ_B2B_WAIT1,
1220 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1222 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1223 writel(RW_MGR_READ_B2B_WAIT2,
1224 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1226 if (quick_read_mode)
1227 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1228 /* need at least two (1+1) reads to capture failures */
1229 else if (all_groups)
1230 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1232 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1234 writel(RW_MGR_READ_B2B,
1235 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1237 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1238 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1239 &sdr_rw_load_mgr_regs->load_cntr3);
1241 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1243 writel(RW_MGR_READ_B2B,
1244 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1247 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1248 /* reset the fifos to get pointers to known state */
1249 writel(0, &phy_mgr_cmd->fifo_reset);
1250 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1251 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1253 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1254 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1257 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1259 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261 writel(RW_MGR_READ_B2B, addr +
1262 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1265 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1266 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1271 *bit_chk &= tmp_bit_chk;
1274 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1275 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1278 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1279 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1280 (%u == %u) => %lu", __func__, __LINE__, group,
1281 all_groups, *bit_chk, param->read_correct_mask,
1282 (long unsigned int)(*bit_chk ==
1283 param->read_correct_mask));
1284 return *bit_chk == param->read_correct_mask;
1286 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1287 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1288 (%u != %lu) => %lu\n", __func__, __LINE__,
1289 group, all_groups, *bit_chk, (long unsigned int)0,
1290 (long unsigned int)(*bit_chk != 0x00));
1291 return *bit_chk != 0x00;
1295 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1296 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1297 uint32_t all_groups)
1299 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1300 bit_chk, all_groups, 1);
1303 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1305 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1309 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1313 for (i = 0; i < VFIFO_SIZE-1; i++)
1314 rw_mgr_incr_vfifo(grp, v);
1317 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1320 uint32_t fail_cnt = 0;
1321 uint32_t test_status;
1323 for (v = 0; v < VFIFO_SIZE; ) {
1324 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1325 __func__, __LINE__, v);
1326 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1327 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1335 /* fiddle with FIFO */
1336 rw_mgr_incr_vfifo(grp, &v);
1339 if (v >= VFIFO_SIZE) {
1340 /* no failing read found!! Something must have gone wrong */
1341 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1342 __func__, __LINE__);
1349 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1350 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1351 uint32_t *v, uint32_t *d, uint32_t *p,
1352 uint32_t *i, uint32_t *max_working_cnt)
1354 uint32_t found_begin = 0;
1355 uint32_t tmp_delay = 0;
1356 uint32_t test_status;
1358 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1359 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1360 *work_bgn = tmp_delay;
1361 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1363 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1364 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1365 IO_DELAY_PER_OPA_TAP) {
1366 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1369 rw_mgr_mem_calibrate_read_test_all_ranks
1370 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1373 *max_working_cnt = 1;
1382 if (*p > IO_DQS_EN_PHASE_MAX)
1383 /* fiddle with FIFO */
1384 rw_mgr_incr_vfifo(*grp, v);
1391 if (*i >= VFIFO_SIZE) {
1392 /* cannot find working solution */
1393 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1394 ptap/dtap\n", __func__, __LINE__);
1401 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1402 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1403 uint32_t *p, uint32_t *max_working_cnt)
1405 uint32_t found_begin = 0;
1408 /* Special case code for backing up a phase */
1410 *p = IO_DQS_EN_PHASE_MAX;
1411 rw_mgr_decr_vfifo(*grp, v);
1415 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1416 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1418 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1419 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1420 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1422 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1426 *work_bgn = tmp_delay;
1431 /* We have found a working dtap before the ptap found above */
1432 if (found_begin == 1)
1433 (*max_working_cnt)++;
1436 * Restore VFIFO to old state before we decremented it
1440 if (*p > IO_DQS_EN_PHASE_MAX) {
1442 rw_mgr_incr_vfifo(*grp, v);
1445 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1448 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1449 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1450 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1453 uint32_t found_end = 0;
1456 *work_end += IO_DELAY_PER_OPA_TAP;
1457 if (*p > IO_DQS_EN_PHASE_MAX) {
1458 /* fiddle with FIFO */
1460 rw_mgr_incr_vfifo(*grp, v);
1463 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1464 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1465 += IO_DELAY_PER_OPA_TAP) {
1466 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1468 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1469 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1473 (*max_working_cnt)++;
1480 if (*p > IO_DQS_EN_PHASE_MAX) {
1481 /* fiddle with FIFO */
1482 rw_mgr_incr_vfifo(*grp, v);
1487 if (*i >= VFIFO_SIZE + 1) {
1488 /* cannot see edge of failing read */
1489 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1490 failed\n", __func__, __LINE__);
1497 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1498 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1499 uint32_t *p, uint32_t *work_mid,
1505 *work_mid = (*work_bgn + *work_end) / 2;
1507 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1508 *work_bgn, *work_end, *work_mid);
1509 /* Get the middle delay to be less than a VFIFO delay */
1510 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1511 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1513 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1514 while (*work_mid > tmp_delay)
1515 *work_mid -= tmp_delay;
1516 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1519 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1520 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1522 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1523 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1524 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1525 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1527 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1529 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1530 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1533 * push vfifo until we can successfully calibrate. We can do this
1534 * because the largest possible margin in 1 VFIFO cycle.
1536 for (i = 0; i < VFIFO_SIZE; i++) {
1537 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1539 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1545 /* fiddle with FIFO */
1546 rw_mgr_incr_vfifo(*grp, v);
1549 if (i >= VFIFO_SIZE) {
1550 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1551 failed\n", __func__, __LINE__);
1558 /* find a good dqs enable to use */
1559 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1561 uint32_t v, d, p, i;
1562 uint32_t max_working_cnt;
1564 uint32_t dtaps_per_ptap;
1565 uint32_t work_bgn, work_mid, work_end;
1566 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1568 debug("%s:%d %u\n", __func__, __LINE__, grp);
1570 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1572 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1573 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1575 /* ************************************************************** */
1576 /* * Step 0 : Determine number of delay taps for each phase tap * */
1577 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1579 /* ********************************************************* */
1580 /* * Step 1 : First push vfifo until we get a failing read * */
1581 v = find_vfifo_read(grp, &bit_chk);
1583 max_working_cnt = 0;
1585 /* ******************************************************** */
1586 /* * step 2: find first working phase, increment in ptaps * */
1588 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1589 &p, &i, &max_working_cnt) == 0)
1592 work_end = work_bgn;
1595 * If d is 0 then the working window covers a phase tap and
1596 * we can follow the old procedure otherwise, we've found the beginning,
1597 * and we need to increment the dtaps until we find the end.
1600 /* ********************************************************* */
1601 /* * step 3a: if we have room, back off by one and
1602 increment in dtaps * */
1604 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1607 /* ********************************************************* */
1608 /* * step 4a: go forward from working phase to non working
1609 phase, increment in ptaps * */
1610 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1611 &i, &max_working_cnt, &work_end) == 0)
1614 /* ********************************************************* */
1615 /* * step 5a: back off one from last, increment in dtaps * */
1617 /* Special case code for backing up a phase */
1619 p = IO_DQS_EN_PHASE_MAX;
1620 rw_mgr_decr_vfifo(grp, &v);
1625 work_end -= IO_DELAY_PER_OPA_TAP;
1626 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1628 /* * The actual increment of dtaps is done outside of
1629 the if/else loop to share code */
1632 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1633 vfifo=%u ptap=%u\n", __func__, __LINE__,
1636 /* ******************************************************* */
1637 /* * step 3-5b: Find the right edge of the window using
1639 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1640 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1643 work_end = work_bgn;
1645 /* * The actual increment of dtaps is done outside of the
1646 if/else loop to share code */
1648 /* Only here to counterbalance a subtract later on which is
1649 not needed if this branch of the algorithm is taken */
1653 /* The dtap increment to find the failing edge is done here */
1654 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1655 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1656 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1657 end-2: dtap=%u\n", __func__, __LINE__, d);
1658 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1660 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1667 /* Go back to working dtap */
1669 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1671 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1672 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1673 v, p, d-1, work_end);
1675 if (work_end < work_bgn) {
1677 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1678 failed\n", __func__, __LINE__);
1682 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1683 __func__, __LINE__, work_bgn, work_end);
1685 /* *************************************************************** */
1687 * * We need to calculate the number of dtaps that equal a ptap
1688 * * To do that we'll back up a ptap and re-find the edge of the
1689 * * window using dtaps
1692 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1693 for tracking\n", __func__, __LINE__);
1695 /* Special case code for backing up a phase */
1697 p = IO_DQS_EN_PHASE_MAX;
1698 rw_mgr_decr_vfifo(grp, &v);
1699 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1700 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1704 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1705 phase only: v=%u p=%u", __func__, __LINE__,
1709 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1712 * Increase dtap until we first see a passing read (in case the
1713 * window is smaller than a ptap),
1714 * and then a failing read to mark the edge of the window again
1717 /* Find a passing read */
1718 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1719 __func__, __LINE__);
1720 found_passing_read = 0;
1721 found_failing_read = 0;
1722 initial_failing_dtap = d;
1723 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1724 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1725 read d=%u\n", __func__, __LINE__, d);
1726 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1728 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1731 found_passing_read = 1;
1736 if (found_passing_read) {
1737 /* Find a failing read */
1738 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1739 read\n", __func__, __LINE__);
1740 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1741 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1742 testing read d=%u\n", __func__, __LINE__, d);
1743 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1745 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1746 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1747 found_failing_read = 1;
1752 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1753 calculate dtaps", __func__, __LINE__);
1754 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1758 * The dynamically calculated dtaps_per_ptap is only valid if we
1759 * found a passing/failing read. If we didn't, it means d hit the max
1760 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1761 * statically calculated value.
1763 if (found_passing_read && found_failing_read)
1764 dtaps_per_ptap = d - initial_failing_dtap;
1766 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1767 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1768 - %u = %u", __func__, __LINE__, d,
1769 initial_failing_dtap, dtaps_per_ptap);
1771 /* ******************************************** */
1772 /* * step 6: Find the centre of the window * */
1773 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1774 &work_mid, &work_end) == 0)
1777 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1778 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1784 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1785 * dq_in_delay values
1788 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1789 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1797 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1798 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1799 /* we start at zero, so have one less dq to devide among */
1801 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1804 /* try different dq_in_delays since the dq path is shorter than dqs */
1806 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1807 r += NUM_RANKS_PER_SHADOW_REG) {
1808 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1809 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1810 vfifo_find_dqs_", __func__, __LINE__);
1811 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1812 write_group, read_group);
1813 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1814 scc_mgr_set_dq_in_delay(p, d);
1817 writel(0, &sdr_scc_mgr->update);
1820 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1822 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1823 en_phase_sweep_dq", __func__, __LINE__);
1824 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1825 chain to zero\n", write_group, read_group, found);
1827 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1828 r += NUM_RANKS_PER_SHADOW_REG) {
1829 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1831 scc_mgr_set_dq_in_delay(p, 0);
1834 writel(0, &sdr_scc_mgr->update);
1840 /* per-bit deskew DQ and center */
1841 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1842 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1843 uint32_t use_read_test, uint32_t update_fom)
1845 uint32_t i, p, d, min_index;
1847 * Store these as signed since there are comparisons with
1851 uint32_t sticky_bit_chk;
1852 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1853 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1854 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1856 int32_t orig_mid_min, mid_min;
1857 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1859 int32_t dq_margin, dqs_margin;
1861 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1864 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1866 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1867 start_dqs = readl(addr + (read_group << 2));
1868 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1869 start_dqs_en = readl(addr + ((read_group << 2)
1870 - IO_DQS_EN_DELAY_OFFSET));
1872 /* set the left and right edge of each bit to an illegal value */
1873 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1875 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1876 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1877 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1880 /* Search for the left edge of the window for each bit */
1881 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1882 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1884 writel(0, &sdr_scc_mgr->update);
1887 * Stop searching when the read test doesn't pass AND when
1888 * we've seen a passing read on every bit.
1890 if (use_read_test) {
1891 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1892 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1895 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1898 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1899 (read_group - (write_group *
1900 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1901 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1902 stop = (bit_chk == 0);
1904 sticky_bit_chk = sticky_bit_chk | bit_chk;
1905 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1906 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1907 && %u", __func__, __LINE__, d,
1909 param->read_correct_mask, stop);
1914 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1916 /* Remember a passing test as the
1920 /* If a left edge has not been seen yet,
1921 then a future passing test will mark
1922 this edge as the right edge */
1924 IO_IO_IN_DELAY_MAX + 1) {
1925 right_edge[i] = -(d + 1);
1928 bit_chk = bit_chk >> 1;
1933 /* Reset DQ delay chains to 0 */
1934 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1936 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1937 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1938 %d right_edge[%u]: %d\n", __func__, __LINE__,
1939 i, left_edge[i], i, right_edge[i]);
1942 * Check for cases where we haven't found the left edge,
1943 * which makes our assignment of the the right edge invalid.
1944 * Reset it to the illegal value.
1946 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1947 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1948 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1949 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1950 right_edge[%u]: %d\n", __func__, __LINE__,
1955 * Reset sticky bit (except for bits where we have seen
1956 * both the left and right edge).
1958 sticky_bit_chk = sticky_bit_chk << 1;
1959 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1960 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1961 sticky_bit_chk = sticky_bit_chk | 1;
1968 /* Search for the right edge of the window for each bit */
1969 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1970 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1971 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1972 uint32_t delay = d + start_dqs_en;
1973 if (delay > IO_DQS_EN_DELAY_MAX)
1974 delay = IO_DQS_EN_DELAY_MAX;
1975 scc_mgr_set_dqs_en_delay(read_group, delay);
1977 scc_mgr_load_dqs(read_group);
1979 writel(0, &sdr_scc_mgr->update);
1982 * Stop searching when the read test doesn't pass AND when
1983 * we've seen a passing read on every bit.
1985 if (use_read_test) {
1986 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1987 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1990 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1993 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1994 (read_group - (write_group *
1995 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1996 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1997 stop = (bit_chk == 0);
1999 sticky_bit_chk = sticky_bit_chk | bit_chk;
2000 stop = stop && (sticky_bit_chk == param->read_correct_mask);
2002 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
2003 %u && %u", __func__, __LINE__, d,
2004 sticky_bit_chk, param->read_correct_mask, stop);
2009 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2011 /* Remember a passing test as
2016 /* If a right edge has not been
2017 seen yet, then a future passing
2018 test will mark this edge as the
2020 if (right_edge[i] ==
2021 IO_IO_IN_DELAY_MAX + 1) {
2022 left_edge[i] = -(d + 1);
2025 /* d = 0 failed, but it passed
2026 when testing the left edge,
2027 so it must be marginal,
2029 if (right_edge[i] ==
2030 IO_IO_IN_DELAY_MAX + 1 &&
2036 /* If a right edge has not been
2037 seen yet, then a future passing
2038 test will mark this edge as the
2040 else if (right_edge[i] ==
2041 IO_IO_IN_DELAY_MAX +
2043 left_edge[i] = -(d + 1);
2048 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2049 d=%u]: ", __func__, __LINE__, d);
2050 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2051 (int)(bit_chk & 1), i, left_edge[i]);
2052 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2054 bit_chk = bit_chk >> 1;
2059 /* Check that all bits have a window */
2060 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2061 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2062 %d right_edge[%u]: %d", __func__, __LINE__,
2063 i, left_edge[i], i, right_edge[i]);
2064 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2065 == IO_IO_IN_DELAY_MAX + 1)) {
2067 * Restore delay chain settings before letting the loop
2068 * in rw_mgr_mem_calibrate_vfifo to retry different
2069 * dqs/ck relationships.
2071 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2072 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2073 scc_mgr_set_dqs_en_delay(read_group,
2076 scc_mgr_load_dqs(read_group);
2077 writel(0, &sdr_scc_mgr->update);
2079 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2080 find edge [%u]: %d %d", __func__, __LINE__,
2081 i, left_edge[i], right_edge[i]);
2082 if (use_read_test) {
2083 set_failing_group_stage(read_group *
2084 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2086 CAL_SUBSTAGE_VFIFO_CENTER);
2088 set_failing_group_stage(read_group *
2089 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2090 CAL_STAGE_VFIFO_AFTER_WRITES,
2091 CAL_SUBSTAGE_VFIFO_CENTER);
2097 /* Find middle of window for each DQ bit */
2098 mid_min = left_edge[0] - right_edge[0];
2100 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2101 mid = left_edge[i] - right_edge[i];
2102 if (mid < mid_min) {
2109 * -mid_min/2 represents the amount that we need to move DQS.
2110 * If mid_min is odd and positive we'll need to add one to
2111 * make sure the rounding in further calculations is correct
2112 * (always bias to the right), so just add 1 for all positive values.
2117 mid_min = mid_min / 2;
2119 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2120 __func__, __LINE__, mid_min, min_index);
2122 /* Determine the amount we can change DQS (which is -mid_min) */
2123 orig_mid_min = mid_min;
2124 new_dqs = start_dqs - mid_min;
2125 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2126 new_dqs = IO_DQS_IN_DELAY_MAX;
2127 else if (new_dqs < 0)
2130 mid_min = start_dqs - new_dqs;
2131 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2134 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2135 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2136 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2137 else if (start_dqs_en - mid_min < 0)
2138 mid_min += start_dqs_en - mid_min;
2140 new_dqs = start_dqs - mid_min;
2142 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2143 new_dqs=%d mid_min=%d\n", start_dqs,
2144 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2147 /* Initialize data for export structures */
2148 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2149 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2151 /* add delay to bring centre of all DQ windows to the same "level" */
2152 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2153 /* Use values before divide by 2 to reduce round off error */
2154 shift_dq = (left_edge[i] - right_edge[i] -
2155 (left_edge[min_index] - right_edge[min_index]))/2 +
2156 (orig_mid_min - mid_min);
2158 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2159 shift_dq[%u]=%d\n", i, shift_dq);
2161 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2162 temp_dq_in_delay1 = readl(addr + (p << 2));
2163 temp_dq_in_delay2 = readl(addr + (i << 2));
2165 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2166 (int32_t)IO_IO_IN_DELAY_MAX) {
2167 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2168 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2169 shift_dq = -(int32_t)temp_dq_in_delay1;
2171 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2172 shift_dq[%u]=%d\n", i, shift_dq);
2173 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2174 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2177 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2178 left_edge[i] - shift_dq + (-mid_min),
2179 right_edge[i] + shift_dq - (-mid_min));
2180 /* To determine values for export structures */
2181 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2182 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2184 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2185 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2188 final_dqs = new_dqs;
2189 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2190 final_dqs_en = start_dqs_en - mid_min;
2193 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2194 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2195 scc_mgr_load_dqs(read_group);
2199 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2200 scc_mgr_load_dqs(read_group);
2201 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2202 dqs_margin=%d", __func__, __LINE__,
2203 dq_margin, dqs_margin);
2206 * Do not remove this line as it makes sure all of our decisions
2207 * have been applied. Apply the update bit.
2209 writel(0, &sdr_scc_mgr->update);
2211 return (dq_margin >= 0) && (dqs_margin >= 0);
2215 * calibrate the read valid prediction FIFO.
2217 * - read valid prediction will consist of finding a good DQS enable phase,
2218 * DQS enable delay, DQS input phase, and DQS input delay.
2219 * - we also do a per-bit deskew on the DQ lines.
2221 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2224 uint32_t p, d, rank_bgn, sr;
2225 uint32_t dtaps_per_ptap;
2228 uint32_t grp_calibrated;
2229 uint32_t write_group, write_test_bgn;
2230 uint32_t failed_substage;
2232 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2234 /* update info for sims */
2235 reg_file_set_stage(CAL_STAGE_VFIFO);
2237 write_group = read_group;
2238 write_test_bgn = test_bgn;
2240 /* USER Determine number of delay taps for each phase tap */
2243 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2245 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2250 /* update info for sims */
2251 reg_file_set_group(read_group);
2255 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2256 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2258 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2260 * In RLDRAMX we may be messing the delay of pins in
2261 * the same write group but outside of the current read
2262 * the group, but that's ok because we haven't
2263 * calibrated output side yet.
2266 scc_mgr_apply_group_all_out_delay_add_all_ranks
2267 (write_group, write_test_bgn, d);
2270 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2272 /* set a particular dqdqs phase */
2273 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2275 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2276 p=%u d=%u\n", __func__, __LINE__,
2280 * Load up the patterns used by read calibration
2281 * using current DQDQS phase.
2283 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2284 if (!(gbl->phy_debug_mode_flags &
2285 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2286 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2287 (read_group, 1, &bit_chk)) {
2288 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2289 __func__, __LINE__);
2290 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2298 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2299 (write_group, read_group, test_bgn)) {
2301 * USER Read per-bit deskew can be done on a
2302 * per shadow register basis.
2304 for (rank_bgn = 0, sr = 0;
2305 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2306 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2309 * Determine if this set of ranks
2310 * should be skipped entirely.
2312 if (!param->skip_shadow_regs[sr]) {
2314 * If doing read after write
2315 * calibration, do not update
2316 * FOM, now - do it then.
2318 if (!rw_mgr_mem_calibrate_vfifo_center
2319 (rank_bgn, write_group,
2320 read_group, test_bgn, 1, 0)) {
2323 CAL_SUBSTAGE_VFIFO_CENTER;
2329 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2334 if (grp_calibrated == 0) {
2335 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2341 * Reset the delay chains back to zero if they have moved > 1
2342 * (check for > 1 because loop will increase d even when pass in
2346 scc_mgr_zero_group(write_group, write_test_bgn, 1);
2351 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2352 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2355 uint32_t rank_bgn, sr;
2356 uint32_t grp_calibrated;
2357 uint32_t write_group;
2359 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2361 /* update info for sims */
2363 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2364 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2366 write_group = read_group;
2368 /* update info for sims */
2369 reg_file_set_group(read_group);
2372 /* Read per-bit deskew can be done on a per shadow register basis */
2373 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2374 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2375 /* Determine if this set of ranks should be skipped entirely */
2376 if (!param->skip_shadow_regs[sr]) {
2377 /* This is the last calibration round, update FOM here */
2378 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2389 if (grp_calibrated == 0) {
2390 set_failing_group_stage(write_group,
2391 CAL_STAGE_VFIFO_AFTER_WRITES,
2392 CAL_SUBSTAGE_VFIFO_CENTER);
2399 /* Calibrate LFIFO to find smallest read latency */
2400 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2405 debug("%s:%d\n", __func__, __LINE__);
2407 /* update info for sims */
2408 reg_file_set_stage(CAL_STAGE_LFIFO);
2409 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2411 /* Load up the patterns used by read calibration for all ranks */
2412 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2416 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2417 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2418 __func__, __LINE__, gbl->curr_read_lat);
2420 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2428 /* reduce read latency and see if things are working */
2430 gbl->curr_read_lat--;
2431 } while (gbl->curr_read_lat > 0);
2433 /* reset the fifos to get pointers to known state */
2435 writel(0, &phy_mgr_cmd->fifo_reset);
2438 /* add a fudge factor to the read latency that was determined */
2439 gbl->curr_read_lat += 2;
2440 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2441 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2442 read_lat=%u\n", __func__, __LINE__,
2443 gbl->curr_read_lat);
2446 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2447 CAL_SUBSTAGE_READ_LATENCY);
2449 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2450 read_lat=%u\n", __func__, __LINE__,
2451 gbl->curr_read_lat);
2457 * issue write test command.
2458 * two variants are provided. one that just tests a write pattern and
2459 * another that tests datamask functionality.
2461 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2464 uint32_t mcc_instruction;
2465 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2466 ENABLE_SUPER_QUICK_CALIBRATION);
2467 uint32_t rw_wl_nop_cycles;
2471 * Set counter and jump addresses for the right
2472 * number of NOP cycles.
2473 * The number of supported NOP cycles can range from -1 to infinity
2474 * Three different cases are handled:
2476 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2477 * mechanism will be used to insert the right number of NOPs
2479 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2480 * issuing the write command will jump straight to the
2481 * micro-instruction that turns on DQS (for DDRx), or outputs write
2482 * data (for RLD), skipping
2483 * the NOP micro-instruction all together
2485 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2486 * turned on in the same micro-instruction that issues the write
2487 * command. Then we need
2488 * to directly jump to the micro-instruction that sends out the data
2490 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2491 * (2 and 3). One jump-counter (0) is used to perform multiple
2492 * write-read operations.
2493 * one counter left to issue this command in "multiple-group" mode
2496 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2498 if (rw_wl_nop_cycles == -1) {
2500 * CNTR 2 - We want to execute the special write operation that
2501 * turns on DQS right away and then skip directly to the
2502 * instruction that sends out the data. We set the counter to a
2503 * large number so that the jump is always taken.
2505 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2507 /* CNTR 3 - Not used */
2509 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2510 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2511 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2512 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2513 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2515 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2516 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2517 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2518 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2519 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2521 } else if (rw_wl_nop_cycles == 0) {
2523 * CNTR 2 - We want to skip the NOP operation and go straight
2524 * to the DQS enable instruction. We set the counter to a large
2525 * number so that the jump is always taken.
2527 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2529 /* CNTR 3 - Not used */
2531 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2532 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2533 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2535 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2536 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2537 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2541 * CNTR 2 - In this case we want to execute the next instruction
2542 * and NOT take the jump. So we set the counter to 0. The jump
2543 * address doesn't count.
2545 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2546 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2549 * CNTR 3 - Set the nop counter to the number of cycles we
2550 * need to loop for, minus 1.
2552 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2554 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2555 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2556 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2558 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2559 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2560 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2564 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2565 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2567 if (quick_write_mode)
2568 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2570 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2572 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2575 * CNTR 1 - This is used to ensure enough time elapses
2576 * for read data to come back.
2578 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2581 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2582 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2584 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2585 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2588 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2589 writel(mcc_instruction, addr + (group << 2));
2592 /* Test writes, can check for a single bit pass or multiple bit pass */
2593 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2594 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2595 uint32_t *bit_chk, uint32_t all_ranks)
2598 uint32_t correct_mask_vg;
2599 uint32_t tmp_bit_chk;
2601 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2602 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2603 uint32_t addr_rw_mgr;
2604 uint32_t base_rw_mgr;
2606 *bit_chk = param->write_correct_mask;
2607 correct_mask_vg = param->write_correct_mask_vg;
2609 for (r = rank_bgn; r < rank_end; r++) {
2610 if (param->skip_ranks[r]) {
2611 /* request to skip the rank */
2616 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2619 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2620 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2621 /* reset the fifos to get pointers to known state */
2622 writel(0, &phy_mgr_cmd->fifo_reset);
2624 tmp_bit_chk = tmp_bit_chk <<
2625 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2626 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2627 rw_mgr_mem_calibrate_write_test_issue(write_group *
2628 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2631 base_rw_mgr = readl(addr_rw_mgr);
2632 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2636 *bit_chk &= tmp_bit_chk;
2640 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2641 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2642 %u => %lu", write_group, use_dm,
2643 *bit_chk, param->write_correct_mask,
2644 (long unsigned int)(*bit_chk ==
2645 param->write_correct_mask));
2646 return *bit_chk == param->write_correct_mask;
2648 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2649 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2650 write_group, use_dm, *bit_chk);
2651 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2652 (long unsigned int)(*bit_chk != 0));
2653 return *bit_chk != 0x00;
2658 * center all windows. do per-bit-deskew to possibly increase size of
2661 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2662 uint32_t write_group, uint32_t test_bgn)
2664 uint32_t i, p, min_index;
2667 * Store these as signed since there are comparisons with
2671 uint32_t sticky_bit_chk;
2672 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2673 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2675 int32_t mid_min, orig_mid_min;
2676 int32_t new_dqs, start_dqs, shift_dq;
2677 int32_t dq_margin, dqs_margin, dm_margin;
2679 uint32_t temp_dq_out1_delay;
2682 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2686 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2687 start_dqs = readl(addr +
2688 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2690 /* per-bit deskew */
2693 * set the left and right edge of each bit to an illegal value
2694 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2697 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2698 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2699 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2702 /* Search for the left edge of the window for each bit */
2703 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2704 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2706 writel(0, &sdr_scc_mgr->update);
2709 * Stop searching when the read test doesn't pass AND when
2710 * we've seen a passing read on every bit.
2712 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2713 0, PASS_ONE_BIT, &bit_chk, 0);
2714 sticky_bit_chk = sticky_bit_chk | bit_chk;
2715 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2716 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2717 == %u && %u [bit_chk= %u ]\n",
2718 d, sticky_bit_chk, param->write_correct_mask,
2724 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2727 * Remember a passing test as the
2733 * If a left edge has not been seen
2734 * yet, then a future passing test will
2735 * mark this edge as the right edge.
2738 IO_IO_OUT1_DELAY_MAX + 1) {
2739 right_edge[i] = -(d + 1);
2742 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2743 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2744 (int)(bit_chk & 1), i, left_edge[i]);
2745 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2747 bit_chk = bit_chk >> 1;
2752 /* Reset DQ delay chains to 0 */
2753 scc_mgr_apply_group_dq_out1_delay(0);
2755 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2756 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2757 %d right_edge[%u]: %d\n", __func__, __LINE__,
2758 i, left_edge[i], i, right_edge[i]);
2761 * Check for cases where we haven't found the left edge,
2762 * which makes our assignment of the the right edge invalid.
2763 * Reset it to the illegal value.
2765 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2766 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2767 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2768 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2769 right_edge[%u]: %d\n", __func__, __LINE__,
2774 * Reset sticky bit (except for bits where we have
2775 * seen the left edge).
2777 sticky_bit_chk = sticky_bit_chk << 1;
2778 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2779 sticky_bit_chk = sticky_bit_chk | 1;
2785 /* Search for the right edge of the window for each bit */
2786 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2787 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2790 writel(0, &sdr_scc_mgr->update);
2793 * Stop searching when the read test doesn't pass AND when
2794 * we've seen a passing read on every bit.
2796 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2797 0, PASS_ONE_BIT, &bit_chk, 0);
2799 sticky_bit_chk = sticky_bit_chk | bit_chk;
2800 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2802 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2803 %u && %u\n", d, sticky_bit_chk,
2804 param->write_correct_mask, stop);
2808 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2810 /* d = 0 failed, but it passed when
2811 testing the left edge, so it must be
2812 marginal, set it to -1 */
2813 if (right_edge[i] ==
2814 IO_IO_OUT1_DELAY_MAX + 1 &&
2816 IO_IO_OUT1_DELAY_MAX + 1) {
2823 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2826 * Remember a passing test as
2833 * If a right edge has not
2834 * been seen yet, then a future
2835 * passing test will mark this
2836 * edge as the left edge.
2838 if (right_edge[i] ==
2839 IO_IO_OUT1_DELAY_MAX + 1)
2840 left_edge[i] = -(d + 1);
2843 * d = 0 failed, but it passed
2844 * when testing the left edge,
2845 * so it must be marginal, set
2848 if (right_edge[i] ==
2849 IO_IO_OUT1_DELAY_MAX + 1 &&
2851 IO_IO_OUT1_DELAY_MAX + 1)
2854 * If a right edge has not been
2855 * seen yet, then a future
2856 * passing test will mark this
2857 * edge as the left edge.
2859 else if (right_edge[i] ==
2860 IO_IO_OUT1_DELAY_MAX +
2862 left_edge[i] = -(d + 1);
2865 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2866 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2867 (int)(bit_chk & 1), i, left_edge[i]);
2868 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2870 bit_chk = bit_chk >> 1;
2875 /* Check that all bits have a window */
2876 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2877 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2878 %d right_edge[%u]: %d", __func__, __LINE__,
2879 i, left_edge[i], i, right_edge[i]);
2880 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2881 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2882 set_failing_group_stage(test_bgn + i,
2884 CAL_SUBSTAGE_WRITES_CENTER);
2889 /* Find middle of window for each DQ bit */
2890 mid_min = left_edge[0] - right_edge[0];
2892 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2893 mid = left_edge[i] - right_edge[i];
2894 if (mid < mid_min) {
2901 * -mid_min/2 represents the amount that we need to move DQS.
2902 * If mid_min is odd and positive we'll need to add one to
2903 * make sure the rounding in further calculations is correct
2904 * (always bias to the right), so just add 1 for all positive values.
2908 mid_min = mid_min / 2;
2909 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2912 /* Determine the amount we can change DQS (which is -mid_min) */
2913 orig_mid_min = mid_min;
2914 new_dqs = start_dqs;
2916 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2917 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2918 /* Initialize data for export structures */
2919 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2920 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2922 /* add delay to bring centre of all DQ windows to the same "level" */
2923 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2924 /* Use values before divide by 2 to reduce round off error */
2925 shift_dq = (left_edge[i] - right_edge[i] -
2926 (left_edge[min_index] - right_edge[min_index]))/2 +
2927 (orig_mid_min - mid_min);
2929 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2930 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2932 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2933 temp_dq_out1_delay = readl(addr + (i << 2));
2934 if (shift_dq + (int32_t)temp_dq_out1_delay >
2935 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2936 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2937 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2938 shift_dq = -(int32_t)temp_dq_out1_delay;
2940 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2942 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2945 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2946 left_edge[i] - shift_dq + (-mid_min),
2947 right_edge[i] + shift_dq - (-mid_min));
2948 /* To determine values for export structures */
2949 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2950 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2952 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2953 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2957 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2958 writel(0, &sdr_scc_mgr->update);
2961 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2964 * set the left and right edge of each bit to an illegal value,
2965 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2967 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2968 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2969 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2970 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2971 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2972 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2973 int32_t win_best = 0;
2975 /* Search for the/part of the window with DM shift */
2976 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2977 scc_mgr_apply_group_dm_out1_delay(d);
2978 writel(0, &sdr_scc_mgr->update);
2980 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2981 PASS_ALL_BITS, &bit_chk,
2983 /* USE Set current end of the window */
2986 * If a starting edge of our window has not been seen
2987 * this is our current start of the DM window.
2989 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2993 * If current window is bigger than best seen.
2994 * Set best seen to be current window.
2996 if ((end_curr-bgn_curr+1) > win_best) {
2997 win_best = end_curr-bgn_curr+1;
2998 bgn_best = bgn_curr;
2999 end_best = end_curr;
3002 /* We just saw a failing test. Reset temp edge */
3003 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3004 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3009 /* Reset DM delay chains to 0 */
3010 scc_mgr_apply_group_dm_out1_delay(0);
3013 * Check to see if the current window nudges up aganist 0 delay.
3014 * If so we need to continue the search by shifting DQS otherwise DQS
3015 * search begins as a new search. */
3016 if (end_curr != 0) {
3017 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3018 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3021 /* Search for the/part of the window with DQS shifts */
3022 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3024 * Note: This only shifts DQS, so are we limiting ourselve to
3025 * width of DQ unnecessarily.
3027 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3030 writel(0, &sdr_scc_mgr->update);
3031 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3032 PASS_ALL_BITS, &bit_chk,
3034 /* USE Set current end of the window */
3037 * If a beginning edge of our window has not been seen
3038 * this is our current begin of the DM window.
3040 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3044 * If current window is bigger than best seen. Set best
3045 * seen to be current window.
3047 if ((end_curr-bgn_curr+1) > win_best) {
3048 win_best = end_curr-bgn_curr+1;
3049 bgn_best = bgn_curr;
3050 end_best = end_curr;
3053 /* We just saw a failing test. Reset temp edge */
3054 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3055 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3057 /* Early exit optimization: if ther remaining delay
3058 chain space is less than already seen largest window
3061 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3067 /* assign left and right edge for cal and reporting; */
3068 left_edge[0] = -1*bgn_best;
3069 right_edge[0] = end_best;
3071 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3072 __LINE__, left_edge[0], right_edge[0]);
3074 /* Move DQS (back to orig) */
3075 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3079 /* Find middle of window for the DM bit */
3080 mid = (left_edge[0] - right_edge[0]) / 2;
3082 /* only move right, since we are not moving DQS/DQ */
3086 /* dm_marign should fail if we never find a window */
3090 dm_margin = left_edge[0] - mid;
3092 scc_mgr_apply_group_dm_out1_delay(mid);
3093 writel(0, &sdr_scc_mgr->update);
3095 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3096 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3097 right_edge[0], mid, dm_margin);
3099 gbl->fom_out += dq_margin + dqs_margin;
3101 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3102 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3103 dq_margin, dqs_margin, dm_margin);
3106 * Do not remove this line as it makes sure all of our
3107 * decisions have been applied.
3109 writel(0, &sdr_scc_mgr->update);
3110 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3113 /* calibrate the write operations */
3114 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3117 /* update info for sims */
3118 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3120 reg_file_set_stage(CAL_STAGE_WRITES);
3121 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3123 reg_file_set_group(g);
3125 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3126 set_failing_group_stage(g, CAL_STAGE_WRITES,
3127 CAL_SUBSTAGE_WRITES_CENTER);
3134 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3135 static void mem_precharge_and_activate(void)
3139 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3140 if (param->skip_ranks[r]) {
3141 /* request to skip the rank */
3146 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3148 /* precharge all banks ... */
3149 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3150 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3152 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3153 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3154 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3156 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3157 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3158 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3161 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3162 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3166 /* Configure various memory related parameters. */
3167 static void mem_config(void)
3169 uint32_t rlat, wlat;
3170 uint32_t rw_wl_nop_cycles;
3171 uint32_t max_latency;
3173 debug("%s:%d\n", __func__, __LINE__);
3174 /* read in write and read latency */
3175 wlat = readl(&data_mgr->t_wl_add);
3176 wlat += readl(&data_mgr->mem_t_add);
3178 /* WL for hard phy does not include additive latency */
3181 * add addtional write latency to offset the address/command extra
3182 * clock cycle. We change the AC mux setting causing AC to be delayed
3183 * by one mem clock cycle. Only do this for DDR3
3187 rlat = readl(&data_mgr->t_rl_add);
3189 rw_wl_nop_cycles = wlat - 2;
3190 gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3193 * For AV/CV, lfifo is hardened and always runs at full rate so
3194 * max latency in AFI clocks, used here, is correspondingly smaller.
3196 max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3197 /* configure for a burst length of 8 */
3200 /* Adjust Write Latency for Hard PHY */
3203 /* set a pretty high read latency initially */
3204 gbl->curr_read_lat = rlat + 16;
3206 if (gbl->curr_read_lat > max_latency)
3207 gbl->curr_read_lat = max_latency;
3209 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3211 /* advertise write latency */
3212 gbl->curr_write_lat = wlat;
3213 writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3215 /* initialize bit slips */
3216 mem_precharge_and_activate();
3219 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3220 static void mem_skip_calibrate(void)
3222 uint32_t vfifo_offset;
3225 debug("%s:%d\n", __func__, __LINE__);
3226 /* Need to update every shadow register set used by the interface */
3227 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3228 r += NUM_RANKS_PER_SHADOW_REG) {
3230 * Set output phase alignment settings appropriate for
3233 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3234 scc_mgr_set_dqs_en_phase(i, 0);
3235 #if IO_DLL_CHAIN_LENGTH == 6
3236 scc_mgr_set_dqdqs_output_phase(i, 6);
3238 scc_mgr_set_dqdqs_output_phase(i, 7);
3243 * Write data arrives to the I/O two cycles before write
3244 * latency is reached (720 deg).
3245 * -> due to bit-slip in a/c bus
3246 * -> to allow board skew where dqs is longer than ck
3247 * -> how often can this happen!?
3248 * -> can claim back some ptaps for high freq
3249 * support if we can relax this, but i digress...
3251 * The write_clk leads mem_ck by 90 deg
3252 * The minimum ptap of the OPA is 180 deg
3253 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3254 * The write_clk is always delayed by 2 ptaps
3256 * Hence, to make DQS aligned to CK, we need to delay
3258 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3260 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3261 * gives us the number of ptaps, which simplies to:
3263 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3265 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3266 IO_DLL_CHAIN_LENGTH - 2));
3268 writel(0xff, &sdr_scc_mgr->dqs_ena);
3269 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3271 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3272 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3273 SCC_MGR_GROUP_COUNTER_OFFSET);
3275 writel(0xff, &sdr_scc_mgr->dq_ena);
3276 writel(0xff, &sdr_scc_mgr->dm_ena);
3277 writel(0, &sdr_scc_mgr->update);
3280 /* Compensate for simulation model behaviour */
3281 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3282 scc_mgr_set_dqs_bus_in_delay(i, 10);
3283 scc_mgr_load_dqs(i);
3285 writel(0, &sdr_scc_mgr->update);
3288 * ArriaV has hard FIFOs that can only be initialized by incrementing
3291 vfifo_offset = CALIB_VFIFO_OFFSET;
3292 for (j = 0; j < vfifo_offset; j++) {
3293 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3295 writel(0, &phy_mgr_cmd->fifo_reset);
3298 * For ACV with hard lfifo, we get the skip-cal setting from
3299 * generation-time constant.
3301 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3302 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3305 /* Memory calibration entry point */
3306 static uint32_t mem_calibrate(void)
3309 uint32_t rank_bgn, sr;
3310 uint32_t write_group, write_test_bgn;
3311 uint32_t read_group, read_test_bgn;
3312 uint32_t run_groups, current_run;
3313 uint32_t failing_groups = 0;
3314 uint32_t group_failed = 0;
3315 uint32_t sr_failed = 0;
3317 debug("%s:%d\n", __func__, __LINE__);
3318 /* Initialize the data settings */
3320 gbl->error_substage = CAL_SUBSTAGE_NIL;
3321 gbl->error_stage = CAL_STAGE_NIL;
3322 gbl->error_group = 0xff;
3328 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3329 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3330 SCC_MGR_GROUP_COUNTER_OFFSET);
3331 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3333 scc_mgr_set_hhp_extras();
3335 scc_set_bypass_mode(i);
3338 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3340 * Set VFIFO and LFIFO to instant-on settings in skip
3343 mem_skip_calibrate();
3345 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3347 * Zero all delay chain/phase settings for all
3348 * groups and all shadow register sets.
3352 run_groups = ~param->skip_groups;
3354 for (write_group = 0, write_test_bgn = 0; write_group
3355 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3356 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3357 /* Initialized the group failure */
3360 current_run = run_groups & ((1 <<
3361 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3362 run_groups = run_groups >>
3363 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3365 if (current_run == 0)
3368 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3369 SCC_MGR_GROUP_COUNTER_OFFSET);
3370 scc_mgr_zero_group(write_group, write_test_bgn,
3373 for (read_group = write_group *
3374 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3375 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3377 read_group < (write_group + 1) *
3378 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3379 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3381 read_group++, read_test_bgn +=
3382 RW_MGR_MEM_DQ_PER_READ_DQS) {
3383 /* Calibrate the VFIFO */
3384 if (!((STATIC_CALIB_STEPS) &
3385 CALIB_SKIP_VFIFO)) {
3386 if (!rw_mgr_mem_calibrate_vfifo
3392 phy_debug_mode_flags &
3393 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3400 /* Calibrate the output side */
3401 if (group_failed == 0) {
3402 for (rank_bgn = 0, sr = 0; rank_bgn
3403 < RW_MGR_MEM_NUMBER_OF_RANKS;
3405 NUM_RANKS_PER_SHADOW_REG,
3408 if (!((STATIC_CALIB_STEPS) &
3409 CALIB_SKIP_WRITES)) {
3410 if ((STATIC_CALIB_STEPS)
3411 & CALIB_SKIP_DELAY_SWEEPS) {
3412 /* not needed in quick mode! */
3415 * Determine if this set of
3416 * ranks should be skipped
3419 if (!param->skip_shadow_regs[sr]) {
3420 if (!rw_mgr_mem_calibrate_writes
3421 (rank_bgn, write_group,
3425 phy_debug_mode_flags &
3426 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3438 if (group_failed == 0) {
3439 for (read_group = write_group *
3440 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3441 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3443 read_group < (write_group + 1)
3444 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3445 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3447 read_group++, read_test_bgn +=
3448 RW_MGR_MEM_DQ_PER_READ_DQS) {
3449 if (!((STATIC_CALIB_STEPS) &
3450 CALIB_SKIP_WRITES)) {
3451 if (!rw_mgr_mem_calibrate_vfifo_end
3452 (read_group, read_test_bgn)) {
3455 if (!(gbl->phy_debug_mode_flags
3456 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3464 if (group_failed != 0)
3469 * USER If there are any failing groups then report
3472 if (failing_groups != 0)
3475 /* Calibrate the LFIFO */
3476 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3478 * If we're skipping groups as part of debug,
3479 * don't calibrate LFIFO.
3481 if (param->skip_groups == 0) {
3482 if (!rw_mgr_mem_calibrate_lfifo())
3490 * Do not remove this line as it makes sure all of our decisions
3491 * have been applied.
3493 writel(0, &sdr_scc_mgr->update);
3497 static uint32_t run_mem_calibrate(void)
3500 uint32_t debug_info;
3502 debug("%s:%d\n", __func__, __LINE__);
3504 /* Reset pass/fail status shown on afi_cal_success/fail */
3505 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3507 /* stop tracking manger */
3508 uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3510 writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3513 rw_mgr_mem_initialize();
3515 pass = mem_calibrate();
3517 mem_precharge_and_activate();
3518 writel(0, &phy_mgr_cmd->fifo_reset);
3522 * Don't return control of the PHY back to AFI when in debug mode.
3524 if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3525 rw_mgr_mem_handoff();
3527 * In Hard PHY this is a 2-bit control:
3529 * 1: DDIO Mux Select
3531 writel(0x2, &phy_mgr_cfg->mux_sel);
3534 writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3537 printf("%s: CALIBRATION PASSED\n", __FILE__);
3542 if (gbl->fom_in > 0xff)
3545 if (gbl->fom_out > 0xff)
3546 gbl->fom_out = 0xff;
3548 /* Update the FOM in the register file */
3549 debug_info = gbl->fom_in;
3550 debug_info |= gbl->fom_out << 8;
3551 writel(debug_info, &sdr_reg_file->fom);
3553 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3554 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3556 printf("%s: CALIBRATION FAILED\n", __FILE__);
3558 debug_info = gbl->error_stage;
3559 debug_info |= gbl->error_substage << 8;
3560 debug_info |= gbl->error_group << 16;
3562 writel(debug_info, &sdr_reg_file->failing_stage);
3563 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3564 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3566 /* Update the failing group/stage in the register file */
3567 debug_info = gbl->error_stage;
3568 debug_info |= gbl->error_substage << 8;
3569 debug_info |= gbl->error_group << 16;
3570 writel(debug_info, &sdr_reg_file->failing_stage);
3577 * hc_initialize_rom_data() - Initialize ROM data
3579 * Initialize ROM data.
3581 static void hc_initialize_rom_data(void)
3585 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3586 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3587 writel(inst_rom_init[i], addr + (i << 2));
3589 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3590 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3591 writel(ac_rom_init[i], addr + (i << 2));
3595 * initialize_reg_file() - Initialize SDR register file
3597 * Initialize SDR register file.
3599 static void initialize_reg_file(void)
3601 /* Initialize the register file with the correct data */
3602 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3603 writel(0, &sdr_reg_file->debug_data_addr);
3604 writel(0, &sdr_reg_file->cur_stage);
3605 writel(0, &sdr_reg_file->fom);
3606 writel(0, &sdr_reg_file->failing_stage);
3607 writel(0, &sdr_reg_file->debug1);
3608 writel(0, &sdr_reg_file->debug2);
3612 * initialize_hps_phy() - Initialize HPS PHY
3614 * Initialize HPS PHY.
3616 static void initialize_hps_phy(void)
3620 * Tracking also gets configured here because it's in the
3623 uint32_t trk_sample_count = 7500;
3624 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3626 * Format is number of outer loops in the 16 MSB, sample
3631 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3632 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3633 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3634 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3635 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3636 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3638 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3639 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3641 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3642 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3644 writel(reg, &sdr_ctrl->phy_ctrl0);
3647 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3649 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3650 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3651 trk_long_idle_sample_count);
3652 writel(reg, &sdr_ctrl->phy_ctrl1);
3655 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3656 trk_long_idle_sample_count >>
3657 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3658 writel(reg, &sdr_ctrl->phy_ctrl2);
3661 static void initialize_tracking(void)
3663 uint32_t concatenated_longidle = 0x0;
3664 uint32_t concatenated_delays = 0x0;
3665 uint32_t concatenated_rw_addr = 0x0;
3666 uint32_t concatenated_refresh = 0x0;
3667 uint32_t trk_sample_count = 7500;
3668 uint32_t dtaps_per_ptap;
3672 * compute usable version of value in case we skip full
3677 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3679 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3683 concatenated_longidle = concatenated_longidle ^ 10;
3684 /*longidle outer loop */
3685 concatenated_longidle = concatenated_longidle << 16;
3686 concatenated_longidle = concatenated_longidle ^ 100;
3687 /*longidle sample count */
3688 concatenated_delays = concatenated_delays ^ 243;
3689 /* trfc, worst case of 933Mhz 4Gb */
3690 concatenated_delays = concatenated_delays << 8;
3691 concatenated_delays = concatenated_delays ^ 14;
3692 /* trcd, worst case */
3693 concatenated_delays = concatenated_delays << 8;
3694 concatenated_delays = concatenated_delays ^ 10;
3696 concatenated_delays = concatenated_delays << 8;
3697 concatenated_delays = concatenated_delays ^ 4;
3700 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3701 concatenated_rw_addr = concatenated_rw_addr << 8;
3702 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3703 concatenated_rw_addr = concatenated_rw_addr << 8;
3704 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3705 concatenated_rw_addr = concatenated_rw_addr << 8;
3706 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3708 concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3709 concatenated_refresh = concatenated_refresh << 24;
3710 concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3712 /* Initialize the register file with the correct data */
3713 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3714 writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3715 writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3716 writel(concatenated_delays, &sdr_reg_file->delays);
3717 writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3718 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3719 writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3722 int sdram_calibration_full(void)
3724 struct param_type my_param;
3725 struct gbl_type my_gbl;
3732 /* Initialize the debug mode flags */
3733 gbl->phy_debug_mode_flags = 0;
3734 /* Set the calibration enabled by default */
3735 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3737 * Only sweep all groups (regardless of fail state) by default
3738 * Set enabled read test by default.
3740 #if DISABLE_GUARANTEED_READ
3741 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3743 /* Initialize the register file */
3744 initialize_reg_file();
3746 /* Initialize any PHY CSR */
3747 initialize_hps_phy();
3749 scc_mgr_initialize();
3751 initialize_tracking();
3753 /* USER Enable all ranks, groups */
3754 for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3755 param->skip_ranks[i] = 0;
3756 for (i = 0; i < NUM_SHADOW_REGS; ++i)
3757 param->skip_shadow_regs[i] = 0;
3758 param->skip_groups = 0;
3760 printf("%s: Preparing to start memory calibration\n", __FILE__);
3762 debug("%s:%d\n", __func__, __LINE__);
3763 debug_cond(DLEVEL == 1,
3764 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3765 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3766 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3767 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3768 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3769 debug_cond(DLEVEL == 1,
3770 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3771 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3772 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3773 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3774 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3775 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3776 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3777 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3778 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3779 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3780 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3781 IO_IO_OUT2_DELAY_MAX);
3782 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3783 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3785 hc_initialize_rom_data();
3787 /* update info for sims */
3788 reg_file_set_stage(CAL_STAGE_NIL);
3789 reg_file_set_group(0);
3792 * Load global needed for those actions that require
3793 * some dynamic calibration support.
3795 dyn_calib_steps = STATIC_CALIB_STEPS;
3797 * Load global to allow dynamic selection of delay loop settings
3798 * based on calibration mode.
3800 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3801 skip_delay_mask = 0xff;
3803 skip_delay_mask = 0x0;
3805 pass = run_mem_calibrate();
3807 printf("%s: Calibration complete\n", __FILE__);