2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * performs a guaranteed read on the patterns we are going to use during a
1041 * read test to ensure memory works
1043 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1044 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1048 uint32_t correct_mask_vg;
1049 uint32_t tmp_bit_chk;
1050 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1051 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1053 uint32_t base_rw_mgr;
1055 *bit_chk = param->read_correct_mask;
1056 correct_mask_vg = param->read_correct_mask_vg;
1058 for (r = rank_bgn; r < rank_end; r++) {
1059 if (param->skip_ranks[r])
1060 /* request to skip the rank */
1064 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1066 /* Load up a constant bursts of read commands */
1067 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1068 writel(RW_MGR_GUARANTEED_READ,
1069 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1071 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1072 writel(RW_MGR_GUARANTEED_READ_CONT,
1073 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1076 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1077 /* reset the fifos to get pointers to known state */
1079 writel(0, &phy_mgr_cmd->fifo_reset);
1080 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1081 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1083 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1084 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1086 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1087 writel(RW_MGR_GUARANTEED_READ, addr +
1088 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1091 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1092 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1097 *bit_chk &= tmp_bit_chk;
1100 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1101 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1103 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1104 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1105 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1106 (long unsigned int)(*bit_chk == param->read_correct_mask));
1107 return *bit_chk == param->read_correct_mask;
1110 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1111 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1113 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1114 num_tries, bit_chk, 1);
1117 /* load up the patterns we are going to use during a read test */
1118 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1122 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1123 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1125 debug("%s:%d\n", __func__, __LINE__);
1126 for (r = rank_bgn; r < rank_end; r++) {
1127 if (param->skip_ranks[r])
1128 /* request to skip the rank */
1132 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1134 /* Load up a constant bursts */
1135 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1137 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1138 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1140 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1142 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1143 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1145 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1150 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1155 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1156 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1159 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1163 * try a read and see if it returns correct data back. has dummy reads
1164 * inserted into the mix used to align dqs enable. has more thorough checks
1165 * than the regular read test.
1167 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1168 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1169 uint32_t all_groups, uint32_t all_ranks)
1172 uint32_t correct_mask_vg;
1173 uint32_t tmp_bit_chk;
1174 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1175 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1177 uint32_t base_rw_mgr;
1179 *bit_chk = param->read_correct_mask;
1180 correct_mask_vg = param->read_correct_mask_vg;
1182 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1183 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1185 for (r = rank_bgn; r < rank_end; r++) {
1186 if (param->skip_ranks[r])
1187 /* request to skip the rank */
1191 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1193 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1195 writel(RW_MGR_READ_B2B_WAIT1,
1196 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1198 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1199 writel(RW_MGR_READ_B2B_WAIT2,
1200 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1202 if (quick_read_mode)
1203 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1204 /* need at least two (1+1) reads to capture failures */
1205 else if (all_groups)
1206 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1208 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1210 writel(RW_MGR_READ_B2B,
1211 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1213 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1214 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1215 &sdr_rw_load_mgr_regs->load_cntr3);
1217 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1219 writel(RW_MGR_READ_B2B,
1220 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1223 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1224 /* reset the fifos to get pointers to known state */
1225 writel(0, &phy_mgr_cmd->fifo_reset);
1226 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1227 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1229 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1230 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1233 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1235 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1237 writel(RW_MGR_READ_B2B, addr +
1238 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1241 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1242 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1247 *bit_chk &= tmp_bit_chk;
1250 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1251 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1254 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1255 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1256 (%u == %u) => %lu", __func__, __LINE__, group,
1257 all_groups, *bit_chk, param->read_correct_mask,
1258 (long unsigned int)(*bit_chk ==
1259 param->read_correct_mask));
1260 return *bit_chk == param->read_correct_mask;
1262 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1263 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1264 (%u != %lu) => %lu\n", __func__, __LINE__,
1265 group, all_groups, *bit_chk, (long unsigned int)0,
1266 (long unsigned int)(*bit_chk != 0x00));
1267 return *bit_chk != 0x00;
1271 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1272 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1273 uint32_t all_groups)
1275 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1276 bit_chk, all_groups, 1);
1279 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1281 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1285 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1289 for (i = 0; i < VFIFO_SIZE-1; i++)
1290 rw_mgr_incr_vfifo(grp, v);
1293 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1296 uint32_t fail_cnt = 0;
1297 uint32_t test_status;
1299 for (v = 0; v < VFIFO_SIZE; ) {
1300 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1301 __func__, __LINE__, v);
1302 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1303 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1311 /* fiddle with FIFO */
1312 rw_mgr_incr_vfifo(grp, &v);
1315 if (v >= VFIFO_SIZE) {
1316 /* no failing read found!! Something must have gone wrong */
1317 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1318 __func__, __LINE__);
1325 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1326 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1327 uint32_t *v, uint32_t *d, uint32_t *p,
1328 uint32_t *i, uint32_t *max_working_cnt)
1330 uint32_t found_begin = 0;
1331 uint32_t tmp_delay = 0;
1332 uint32_t test_status;
1334 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1335 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1336 *work_bgn = tmp_delay;
1337 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1339 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1340 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1341 IO_DELAY_PER_OPA_TAP) {
1342 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1345 rw_mgr_mem_calibrate_read_test_all_ranks
1346 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1349 *max_working_cnt = 1;
1358 if (*p > IO_DQS_EN_PHASE_MAX)
1359 /* fiddle with FIFO */
1360 rw_mgr_incr_vfifo(*grp, v);
1367 if (*i >= VFIFO_SIZE) {
1368 /* cannot find working solution */
1369 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1370 ptap/dtap\n", __func__, __LINE__);
1377 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1378 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1379 uint32_t *p, uint32_t *max_working_cnt)
1381 uint32_t found_begin = 0;
1384 /* Special case code for backing up a phase */
1386 *p = IO_DQS_EN_PHASE_MAX;
1387 rw_mgr_decr_vfifo(*grp, v);
1391 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1392 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1394 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1395 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1396 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1398 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1402 *work_bgn = tmp_delay;
1407 /* We have found a working dtap before the ptap found above */
1408 if (found_begin == 1)
1409 (*max_working_cnt)++;
1412 * Restore VFIFO to old state before we decremented it
1416 if (*p > IO_DQS_EN_PHASE_MAX) {
1418 rw_mgr_incr_vfifo(*grp, v);
1421 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1424 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1425 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1426 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1429 uint32_t found_end = 0;
1432 *work_end += IO_DELAY_PER_OPA_TAP;
1433 if (*p > IO_DQS_EN_PHASE_MAX) {
1434 /* fiddle with FIFO */
1436 rw_mgr_incr_vfifo(*grp, v);
1439 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1440 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1441 += IO_DELAY_PER_OPA_TAP) {
1442 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1444 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1445 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1449 (*max_working_cnt)++;
1456 if (*p > IO_DQS_EN_PHASE_MAX) {
1457 /* fiddle with FIFO */
1458 rw_mgr_incr_vfifo(*grp, v);
1463 if (*i >= VFIFO_SIZE + 1) {
1464 /* cannot see edge of failing read */
1465 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1466 failed\n", __func__, __LINE__);
1473 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1474 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1475 uint32_t *p, uint32_t *work_mid,
1481 *work_mid = (*work_bgn + *work_end) / 2;
1483 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1484 *work_bgn, *work_end, *work_mid);
1485 /* Get the middle delay to be less than a VFIFO delay */
1486 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1487 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1489 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1490 while (*work_mid > tmp_delay)
1491 *work_mid -= tmp_delay;
1492 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1495 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1496 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1498 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1499 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1500 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1501 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1503 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1505 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1506 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1509 * push vfifo until we can successfully calibrate. We can do this
1510 * because the largest possible margin in 1 VFIFO cycle.
1512 for (i = 0; i < VFIFO_SIZE; i++) {
1513 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1515 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1521 /* fiddle with FIFO */
1522 rw_mgr_incr_vfifo(*grp, v);
1525 if (i >= VFIFO_SIZE) {
1526 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1527 failed\n", __func__, __LINE__);
1534 /* find a good dqs enable to use */
1535 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1537 uint32_t v, d, p, i;
1538 uint32_t max_working_cnt;
1540 uint32_t dtaps_per_ptap;
1541 uint32_t work_bgn, work_mid, work_end;
1542 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1544 debug("%s:%d %u\n", __func__, __LINE__, grp);
1546 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1548 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1549 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1551 /* ************************************************************** */
1552 /* * Step 0 : Determine number of delay taps for each phase tap * */
1553 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1555 /* ********************************************************* */
1556 /* * Step 1 : First push vfifo until we get a failing read * */
1557 v = find_vfifo_read(grp, &bit_chk);
1559 max_working_cnt = 0;
1561 /* ******************************************************** */
1562 /* * step 2: find first working phase, increment in ptaps * */
1564 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1565 &p, &i, &max_working_cnt) == 0)
1568 work_end = work_bgn;
1571 * If d is 0 then the working window covers a phase tap and
1572 * we can follow the old procedure otherwise, we've found the beginning,
1573 * and we need to increment the dtaps until we find the end.
1576 /* ********************************************************* */
1577 /* * step 3a: if we have room, back off by one and
1578 increment in dtaps * */
1580 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1583 /* ********************************************************* */
1584 /* * step 4a: go forward from working phase to non working
1585 phase, increment in ptaps * */
1586 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1587 &i, &max_working_cnt, &work_end) == 0)
1590 /* ********************************************************* */
1591 /* * step 5a: back off one from last, increment in dtaps * */
1593 /* Special case code for backing up a phase */
1595 p = IO_DQS_EN_PHASE_MAX;
1596 rw_mgr_decr_vfifo(grp, &v);
1601 work_end -= IO_DELAY_PER_OPA_TAP;
1602 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1604 /* * The actual increment of dtaps is done outside of
1605 the if/else loop to share code */
1608 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1609 vfifo=%u ptap=%u\n", __func__, __LINE__,
1612 /* ******************************************************* */
1613 /* * step 3-5b: Find the right edge of the window using
1615 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1616 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1619 work_end = work_bgn;
1621 /* * The actual increment of dtaps is done outside of the
1622 if/else loop to share code */
1624 /* Only here to counterbalance a subtract later on which is
1625 not needed if this branch of the algorithm is taken */
1629 /* The dtap increment to find the failing edge is done here */
1630 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1631 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1632 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1633 end-2: dtap=%u\n", __func__, __LINE__, d);
1634 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1636 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1643 /* Go back to working dtap */
1645 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1647 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1648 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1649 v, p, d-1, work_end);
1651 if (work_end < work_bgn) {
1653 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1654 failed\n", __func__, __LINE__);
1658 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1659 __func__, __LINE__, work_bgn, work_end);
1661 /* *************************************************************** */
1663 * * We need to calculate the number of dtaps that equal a ptap
1664 * * To do that we'll back up a ptap and re-find the edge of the
1665 * * window using dtaps
1668 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1669 for tracking\n", __func__, __LINE__);
1671 /* Special case code for backing up a phase */
1673 p = IO_DQS_EN_PHASE_MAX;
1674 rw_mgr_decr_vfifo(grp, &v);
1675 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1676 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1680 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1681 phase only: v=%u p=%u", __func__, __LINE__,
1685 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1688 * Increase dtap until we first see a passing read (in case the
1689 * window is smaller than a ptap),
1690 * and then a failing read to mark the edge of the window again
1693 /* Find a passing read */
1694 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1695 __func__, __LINE__);
1696 found_passing_read = 0;
1697 found_failing_read = 0;
1698 initial_failing_dtap = d;
1699 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1700 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1701 read d=%u\n", __func__, __LINE__, d);
1702 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1704 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1707 found_passing_read = 1;
1712 if (found_passing_read) {
1713 /* Find a failing read */
1714 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1715 read\n", __func__, __LINE__);
1716 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1717 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1718 testing read d=%u\n", __func__, __LINE__, d);
1719 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1721 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1722 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1723 found_failing_read = 1;
1728 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1729 calculate dtaps", __func__, __LINE__);
1730 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1734 * The dynamically calculated dtaps_per_ptap is only valid if we
1735 * found a passing/failing read. If we didn't, it means d hit the max
1736 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1737 * statically calculated value.
1739 if (found_passing_read && found_failing_read)
1740 dtaps_per_ptap = d - initial_failing_dtap;
1742 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1743 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1744 - %u = %u", __func__, __LINE__, d,
1745 initial_failing_dtap, dtaps_per_ptap);
1747 /* ******************************************** */
1748 /* * step 6: Find the centre of the window * */
1749 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1750 &work_mid, &work_end) == 0)
1753 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1754 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1760 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1761 * dq_in_delay values
1764 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1765 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1773 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1774 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1775 /* we start at zero, so have one less dq to devide among */
1777 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1780 /* try different dq_in_delays since the dq path is shorter than dqs */
1782 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1783 r += NUM_RANKS_PER_SHADOW_REG) {
1784 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1785 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1786 vfifo_find_dqs_", __func__, __LINE__);
1787 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1788 write_group, read_group);
1789 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1790 scc_mgr_set_dq_in_delay(p, d);
1793 writel(0, &sdr_scc_mgr->update);
1796 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1798 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1799 en_phase_sweep_dq", __func__, __LINE__);
1800 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1801 chain to zero\n", write_group, read_group, found);
1803 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1804 r += NUM_RANKS_PER_SHADOW_REG) {
1805 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1807 scc_mgr_set_dq_in_delay(p, 0);
1810 writel(0, &sdr_scc_mgr->update);
1816 /* per-bit deskew DQ and center */
1817 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1818 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1819 uint32_t use_read_test, uint32_t update_fom)
1821 uint32_t i, p, d, min_index;
1823 * Store these as signed since there are comparisons with
1827 uint32_t sticky_bit_chk;
1828 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1829 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1830 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1832 int32_t orig_mid_min, mid_min;
1833 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1835 int32_t dq_margin, dqs_margin;
1837 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1840 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1842 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1843 start_dqs = readl(addr + (read_group << 2));
1844 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1845 start_dqs_en = readl(addr + ((read_group << 2)
1846 - IO_DQS_EN_DELAY_OFFSET));
1848 /* set the left and right edge of each bit to an illegal value */
1849 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1851 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1852 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1853 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1856 /* Search for the left edge of the window for each bit */
1857 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1858 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1860 writel(0, &sdr_scc_mgr->update);
1863 * Stop searching when the read test doesn't pass AND when
1864 * we've seen a passing read on every bit.
1866 if (use_read_test) {
1867 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1868 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1871 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1874 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1875 (read_group - (write_group *
1876 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1877 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1878 stop = (bit_chk == 0);
1880 sticky_bit_chk = sticky_bit_chk | bit_chk;
1881 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1882 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1883 && %u", __func__, __LINE__, d,
1885 param->read_correct_mask, stop);
1890 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1892 /* Remember a passing test as the
1896 /* If a left edge has not been seen yet,
1897 then a future passing test will mark
1898 this edge as the right edge */
1900 IO_IO_IN_DELAY_MAX + 1) {
1901 right_edge[i] = -(d + 1);
1904 bit_chk = bit_chk >> 1;
1909 /* Reset DQ delay chains to 0 */
1910 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1912 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1913 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1914 %d right_edge[%u]: %d\n", __func__, __LINE__,
1915 i, left_edge[i], i, right_edge[i]);
1918 * Check for cases where we haven't found the left edge,
1919 * which makes our assignment of the the right edge invalid.
1920 * Reset it to the illegal value.
1922 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1923 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1924 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1925 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1926 right_edge[%u]: %d\n", __func__, __LINE__,
1931 * Reset sticky bit (except for bits where we have seen
1932 * both the left and right edge).
1934 sticky_bit_chk = sticky_bit_chk << 1;
1935 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1936 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1937 sticky_bit_chk = sticky_bit_chk | 1;
1944 /* Search for the right edge of the window for each bit */
1945 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1946 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1947 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1948 uint32_t delay = d + start_dqs_en;
1949 if (delay > IO_DQS_EN_DELAY_MAX)
1950 delay = IO_DQS_EN_DELAY_MAX;
1951 scc_mgr_set_dqs_en_delay(read_group, delay);
1953 scc_mgr_load_dqs(read_group);
1955 writel(0, &sdr_scc_mgr->update);
1958 * Stop searching when the read test doesn't pass AND when
1959 * we've seen a passing read on every bit.
1961 if (use_read_test) {
1962 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1963 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1966 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1969 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1970 (read_group - (write_group *
1971 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1972 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1973 stop = (bit_chk == 0);
1975 sticky_bit_chk = sticky_bit_chk | bit_chk;
1976 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1978 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1979 %u && %u", __func__, __LINE__, d,
1980 sticky_bit_chk, param->read_correct_mask, stop);
1985 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1987 /* Remember a passing test as
1992 /* If a right edge has not been
1993 seen yet, then a future passing
1994 test will mark this edge as the
1996 if (right_edge[i] ==
1997 IO_IO_IN_DELAY_MAX + 1) {
1998 left_edge[i] = -(d + 1);
2001 /* d = 0 failed, but it passed
2002 when testing the left edge,
2003 so it must be marginal,
2005 if (right_edge[i] ==
2006 IO_IO_IN_DELAY_MAX + 1 &&
2012 /* If a right edge has not been
2013 seen yet, then a future passing
2014 test will mark this edge as the
2016 else if (right_edge[i] ==
2017 IO_IO_IN_DELAY_MAX +
2019 left_edge[i] = -(d + 1);
2024 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2025 d=%u]: ", __func__, __LINE__, d);
2026 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2027 (int)(bit_chk & 1), i, left_edge[i]);
2028 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2030 bit_chk = bit_chk >> 1;
2035 /* Check that all bits have a window */
2036 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2037 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2038 %d right_edge[%u]: %d", __func__, __LINE__,
2039 i, left_edge[i], i, right_edge[i]);
2040 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2041 == IO_IO_IN_DELAY_MAX + 1)) {
2043 * Restore delay chain settings before letting the loop
2044 * in rw_mgr_mem_calibrate_vfifo to retry different
2045 * dqs/ck relationships.
2047 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2048 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2049 scc_mgr_set_dqs_en_delay(read_group,
2052 scc_mgr_load_dqs(read_group);
2053 writel(0, &sdr_scc_mgr->update);
2055 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2056 find edge [%u]: %d %d", __func__, __LINE__,
2057 i, left_edge[i], right_edge[i]);
2058 if (use_read_test) {
2059 set_failing_group_stage(read_group *
2060 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2062 CAL_SUBSTAGE_VFIFO_CENTER);
2064 set_failing_group_stage(read_group *
2065 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2066 CAL_STAGE_VFIFO_AFTER_WRITES,
2067 CAL_SUBSTAGE_VFIFO_CENTER);
2073 /* Find middle of window for each DQ bit */
2074 mid_min = left_edge[0] - right_edge[0];
2076 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2077 mid = left_edge[i] - right_edge[i];
2078 if (mid < mid_min) {
2085 * -mid_min/2 represents the amount that we need to move DQS.
2086 * If mid_min is odd and positive we'll need to add one to
2087 * make sure the rounding in further calculations is correct
2088 * (always bias to the right), so just add 1 for all positive values.
2093 mid_min = mid_min / 2;
2095 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2096 __func__, __LINE__, mid_min, min_index);
2098 /* Determine the amount we can change DQS (which is -mid_min) */
2099 orig_mid_min = mid_min;
2100 new_dqs = start_dqs - mid_min;
2101 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2102 new_dqs = IO_DQS_IN_DELAY_MAX;
2103 else if (new_dqs < 0)
2106 mid_min = start_dqs - new_dqs;
2107 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2110 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2111 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2112 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2113 else if (start_dqs_en - mid_min < 0)
2114 mid_min += start_dqs_en - mid_min;
2116 new_dqs = start_dqs - mid_min;
2118 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2119 new_dqs=%d mid_min=%d\n", start_dqs,
2120 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2123 /* Initialize data for export structures */
2124 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2125 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2127 /* add delay to bring centre of all DQ windows to the same "level" */
2128 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2129 /* Use values before divide by 2 to reduce round off error */
2130 shift_dq = (left_edge[i] - right_edge[i] -
2131 (left_edge[min_index] - right_edge[min_index]))/2 +
2132 (orig_mid_min - mid_min);
2134 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2135 shift_dq[%u]=%d\n", i, shift_dq);
2137 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2138 temp_dq_in_delay1 = readl(addr + (p << 2));
2139 temp_dq_in_delay2 = readl(addr + (i << 2));
2141 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2142 (int32_t)IO_IO_IN_DELAY_MAX) {
2143 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2144 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2145 shift_dq = -(int32_t)temp_dq_in_delay1;
2147 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2148 shift_dq[%u]=%d\n", i, shift_dq);
2149 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2150 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2153 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2154 left_edge[i] - shift_dq + (-mid_min),
2155 right_edge[i] + shift_dq - (-mid_min));
2156 /* To determine values for export structures */
2157 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2158 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2160 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2161 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2164 final_dqs = new_dqs;
2165 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2166 final_dqs_en = start_dqs_en - mid_min;
2169 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2170 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2171 scc_mgr_load_dqs(read_group);
2175 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2176 scc_mgr_load_dqs(read_group);
2177 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2178 dqs_margin=%d", __func__, __LINE__,
2179 dq_margin, dqs_margin);
2182 * Do not remove this line as it makes sure all of our decisions
2183 * have been applied. Apply the update bit.
2185 writel(0, &sdr_scc_mgr->update);
2187 return (dq_margin >= 0) && (dqs_margin >= 0);
2191 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2192 * @rw_group: Read/Write Group
2193 * @phase: DQ/DQS phase
2195 * Because initially no communication ca be reliably performed with the memory
2196 * device, the sequencer uses a guaranteed write mechanism to write data into
2197 * the memory device.
2199 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2205 /* Set a particular DQ/DQS phase. */
2206 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2208 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2209 __func__, __LINE__, rw_group, phase);
2212 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2213 * Load up the patterns used by read calibration using the
2214 * current DQDQS phase.
2216 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2218 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2222 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2223 * Back-to-Back reads of the patterns used for calibration.
2225 ret = rw_mgr_mem_calibrate_read_test_patterns_all_ranks(rw_group, 1,
2227 if (!ret) { /* FIXME: 0 means failure in this old code :-( */
2228 debug_cond(DLEVEL == 1,
2229 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2230 __func__, __LINE__, rw_group, phase);
2238 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2239 * @rw_group: Read/Write Group
2240 * @test_bgn: Rank at which the test begins
2242 * DQS enable calibration ensures reliable capture of the DQ signal without
2243 * glitches on the DQS line.
2245 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2251 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2252 * DQS and DQS Eanble Signal Relationships.
2254 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
2255 rw_group, rw_group, test_bgn);
2256 if (!ret) /* FIXME: 0 means failure in this old code :-( */
2263 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2264 * @rw_group: Read/Write Group
2265 * @test_bgn: Rank at which the test begins
2267 * Stage 1: Calibrate the read valid prediction FIFO.
2269 * This function implements UniPHY calibration Stage 1, as explained in
2270 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2272 * - read valid prediction will consist of finding:
2273 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2274 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2275 * - we also do a per-bit deskew on the DQ lines.
2277 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2279 uint32_t p, d, rank_bgn, sr;
2280 uint32_t dtaps_per_ptap;
2281 uint32_t grp_calibrated;
2282 uint32_t failed_substage;
2286 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2288 /* Update info for sims */
2289 reg_file_set_group(rw_group);
2290 reg_file_set_stage(CAL_STAGE_VFIFO);
2291 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2293 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2295 /* USER Determine number of delay taps for each phase tap. */
2296 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2297 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2299 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2301 * In RLDRAMX we may be messing the delay of pins in
2302 * the same write rw_group but outside of the current read
2303 * the rw_group, but that's ok because we haven't calibrated
2307 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2311 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2312 /* 1) Guaranteed Write */
2313 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2317 /* 2) DQS Enable Calibration */
2318 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2321 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2326 * USER Read per-bit deskew can be done on a
2327 * per shadow register basis.
2330 for (rank_bgn = 0, sr = 0;
2331 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2332 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2334 * Determine if this set of ranks
2335 * should be skipped entirely.
2337 if (param->skip_shadow_regs[sr])
2340 * If doing read after write
2341 * calibration, do not update
2342 * FOM, now - do it then.
2344 if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2350 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2358 /* Calibration Stage 1 failed. */
2359 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2362 /* Calibration Stage 1 completed OK. */
2365 * Reset the delay chains back to zero if they have moved > 1
2366 * (check for > 1 because loop will increase d even when pass in
2370 scc_mgr_zero_group(rw_group, 1);
2375 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2376 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2379 uint32_t rank_bgn, sr;
2380 uint32_t grp_calibrated;
2381 uint32_t write_group;
2383 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2385 /* update info for sims */
2387 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2388 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2390 write_group = read_group;
2392 /* update info for sims */
2393 reg_file_set_group(read_group);
2396 /* Read per-bit deskew can be done on a per shadow register basis */
2397 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2398 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2399 /* Determine if this set of ranks should be skipped entirely */
2400 if (!param->skip_shadow_regs[sr]) {
2401 /* This is the last calibration round, update FOM here */
2402 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2413 if (grp_calibrated == 0) {
2414 set_failing_group_stage(write_group,
2415 CAL_STAGE_VFIFO_AFTER_WRITES,
2416 CAL_SUBSTAGE_VFIFO_CENTER);
2423 /* Calibrate LFIFO to find smallest read latency */
2424 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2429 debug("%s:%d\n", __func__, __LINE__);
2431 /* update info for sims */
2432 reg_file_set_stage(CAL_STAGE_LFIFO);
2433 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2435 /* Load up the patterns used by read calibration for all ranks */
2436 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2440 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2441 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2442 __func__, __LINE__, gbl->curr_read_lat);
2444 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2452 /* reduce read latency and see if things are working */
2454 gbl->curr_read_lat--;
2455 } while (gbl->curr_read_lat > 0);
2457 /* reset the fifos to get pointers to known state */
2459 writel(0, &phy_mgr_cmd->fifo_reset);
2462 /* add a fudge factor to the read latency that was determined */
2463 gbl->curr_read_lat += 2;
2464 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2465 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2466 read_lat=%u\n", __func__, __LINE__,
2467 gbl->curr_read_lat);
2470 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2471 CAL_SUBSTAGE_READ_LATENCY);
2473 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2474 read_lat=%u\n", __func__, __LINE__,
2475 gbl->curr_read_lat);
2481 * issue write test command.
2482 * two variants are provided. one that just tests a write pattern and
2483 * another that tests datamask functionality.
2485 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2488 uint32_t mcc_instruction;
2489 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2490 ENABLE_SUPER_QUICK_CALIBRATION);
2491 uint32_t rw_wl_nop_cycles;
2495 * Set counter and jump addresses for the right
2496 * number of NOP cycles.
2497 * The number of supported NOP cycles can range from -1 to infinity
2498 * Three different cases are handled:
2500 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2501 * mechanism will be used to insert the right number of NOPs
2503 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2504 * issuing the write command will jump straight to the
2505 * micro-instruction that turns on DQS (for DDRx), or outputs write
2506 * data (for RLD), skipping
2507 * the NOP micro-instruction all together
2509 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2510 * turned on in the same micro-instruction that issues the write
2511 * command. Then we need
2512 * to directly jump to the micro-instruction that sends out the data
2514 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2515 * (2 and 3). One jump-counter (0) is used to perform multiple
2516 * write-read operations.
2517 * one counter left to issue this command in "multiple-group" mode
2520 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2522 if (rw_wl_nop_cycles == -1) {
2524 * CNTR 2 - We want to execute the special write operation that
2525 * turns on DQS right away and then skip directly to the
2526 * instruction that sends out the data. We set the counter to a
2527 * large number so that the jump is always taken.
2529 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2531 /* CNTR 3 - Not used */
2533 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2534 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2535 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2536 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2537 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2539 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2540 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2541 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2542 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2543 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2545 } else if (rw_wl_nop_cycles == 0) {
2547 * CNTR 2 - We want to skip the NOP operation and go straight
2548 * to the DQS enable instruction. We set the counter to a large
2549 * number so that the jump is always taken.
2551 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2553 /* CNTR 3 - Not used */
2555 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2556 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2557 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2559 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2560 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2561 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2565 * CNTR 2 - In this case we want to execute the next instruction
2566 * and NOT take the jump. So we set the counter to 0. The jump
2567 * address doesn't count.
2569 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2570 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2573 * CNTR 3 - Set the nop counter to the number of cycles we
2574 * need to loop for, minus 1.
2576 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2578 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2579 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2580 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2582 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2583 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2584 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2588 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2589 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2591 if (quick_write_mode)
2592 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2594 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2596 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2599 * CNTR 1 - This is used to ensure enough time elapses
2600 * for read data to come back.
2602 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2605 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2606 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2608 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2609 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2612 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2613 writel(mcc_instruction, addr + (group << 2));
2616 /* Test writes, can check for a single bit pass or multiple bit pass */
2617 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2618 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2619 uint32_t *bit_chk, uint32_t all_ranks)
2622 uint32_t correct_mask_vg;
2623 uint32_t tmp_bit_chk;
2625 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2626 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2627 uint32_t addr_rw_mgr;
2628 uint32_t base_rw_mgr;
2630 *bit_chk = param->write_correct_mask;
2631 correct_mask_vg = param->write_correct_mask_vg;
2633 for (r = rank_bgn; r < rank_end; r++) {
2634 if (param->skip_ranks[r]) {
2635 /* request to skip the rank */
2640 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2643 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2644 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2645 /* reset the fifos to get pointers to known state */
2646 writel(0, &phy_mgr_cmd->fifo_reset);
2648 tmp_bit_chk = tmp_bit_chk <<
2649 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2650 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2651 rw_mgr_mem_calibrate_write_test_issue(write_group *
2652 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2655 base_rw_mgr = readl(addr_rw_mgr);
2656 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2660 *bit_chk &= tmp_bit_chk;
2664 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2665 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2666 %u => %lu", write_group, use_dm,
2667 *bit_chk, param->write_correct_mask,
2668 (long unsigned int)(*bit_chk ==
2669 param->write_correct_mask));
2670 return *bit_chk == param->write_correct_mask;
2672 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2673 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2674 write_group, use_dm, *bit_chk);
2675 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2676 (long unsigned int)(*bit_chk != 0));
2677 return *bit_chk != 0x00;
2682 * center all windows. do per-bit-deskew to possibly increase size of
2685 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2686 uint32_t write_group, uint32_t test_bgn)
2688 uint32_t i, p, min_index;
2691 * Store these as signed since there are comparisons with
2695 uint32_t sticky_bit_chk;
2696 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2697 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2699 int32_t mid_min, orig_mid_min;
2700 int32_t new_dqs, start_dqs, shift_dq;
2701 int32_t dq_margin, dqs_margin, dm_margin;
2703 uint32_t temp_dq_out1_delay;
2706 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2710 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2711 start_dqs = readl(addr +
2712 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2714 /* per-bit deskew */
2717 * set the left and right edge of each bit to an illegal value
2718 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2721 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2722 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2723 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2726 /* Search for the left edge of the window for each bit */
2727 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2728 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2730 writel(0, &sdr_scc_mgr->update);
2733 * Stop searching when the read test doesn't pass AND when
2734 * we've seen a passing read on every bit.
2736 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2737 0, PASS_ONE_BIT, &bit_chk, 0);
2738 sticky_bit_chk = sticky_bit_chk | bit_chk;
2739 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2740 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2741 == %u && %u [bit_chk= %u ]\n",
2742 d, sticky_bit_chk, param->write_correct_mask,
2748 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2751 * Remember a passing test as the
2757 * If a left edge has not been seen
2758 * yet, then a future passing test will
2759 * mark this edge as the right edge.
2762 IO_IO_OUT1_DELAY_MAX + 1) {
2763 right_edge[i] = -(d + 1);
2766 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2767 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2768 (int)(bit_chk & 1), i, left_edge[i]);
2769 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2771 bit_chk = bit_chk >> 1;
2776 /* Reset DQ delay chains to 0 */
2777 scc_mgr_apply_group_dq_out1_delay(0);
2779 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2780 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2781 %d right_edge[%u]: %d\n", __func__, __LINE__,
2782 i, left_edge[i], i, right_edge[i]);
2785 * Check for cases where we haven't found the left edge,
2786 * which makes our assignment of the the right edge invalid.
2787 * Reset it to the illegal value.
2789 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2790 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2791 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2792 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2793 right_edge[%u]: %d\n", __func__, __LINE__,
2798 * Reset sticky bit (except for bits where we have
2799 * seen the left edge).
2801 sticky_bit_chk = sticky_bit_chk << 1;
2802 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2803 sticky_bit_chk = sticky_bit_chk | 1;
2809 /* Search for the right edge of the window for each bit */
2810 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2811 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2814 writel(0, &sdr_scc_mgr->update);
2817 * Stop searching when the read test doesn't pass AND when
2818 * we've seen a passing read on every bit.
2820 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2821 0, PASS_ONE_BIT, &bit_chk, 0);
2823 sticky_bit_chk = sticky_bit_chk | bit_chk;
2824 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2826 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2827 %u && %u\n", d, sticky_bit_chk,
2828 param->write_correct_mask, stop);
2832 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2834 /* d = 0 failed, but it passed when
2835 testing the left edge, so it must be
2836 marginal, set it to -1 */
2837 if (right_edge[i] ==
2838 IO_IO_OUT1_DELAY_MAX + 1 &&
2840 IO_IO_OUT1_DELAY_MAX + 1) {
2847 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2850 * Remember a passing test as
2857 * If a right edge has not
2858 * been seen yet, then a future
2859 * passing test will mark this
2860 * edge as the left edge.
2862 if (right_edge[i] ==
2863 IO_IO_OUT1_DELAY_MAX + 1)
2864 left_edge[i] = -(d + 1);
2867 * d = 0 failed, but it passed
2868 * when testing the left edge,
2869 * so it must be marginal, set
2872 if (right_edge[i] ==
2873 IO_IO_OUT1_DELAY_MAX + 1 &&
2875 IO_IO_OUT1_DELAY_MAX + 1)
2878 * If a right edge has not been
2879 * seen yet, then a future
2880 * passing test will mark this
2881 * edge as the left edge.
2883 else if (right_edge[i] ==
2884 IO_IO_OUT1_DELAY_MAX +
2886 left_edge[i] = -(d + 1);
2889 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2890 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2891 (int)(bit_chk & 1), i, left_edge[i]);
2892 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2894 bit_chk = bit_chk >> 1;
2899 /* Check that all bits have a window */
2900 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2901 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2902 %d right_edge[%u]: %d", __func__, __LINE__,
2903 i, left_edge[i], i, right_edge[i]);
2904 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2905 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2906 set_failing_group_stage(test_bgn + i,
2908 CAL_SUBSTAGE_WRITES_CENTER);
2913 /* Find middle of window for each DQ bit */
2914 mid_min = left_edge[0] - right_edge[0];
2916 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2917 mid = left_edge[i] - right_edge[i];
2918 if (mid < mid_min) {
2925 * -mid_min/2 represents the amount that we need to move DQS.
2926 * If mid_min is odd and positive we'll need to add one to
2927 * make sure the rounding in further calculations is correct
2928 * (always bias to the right), so just add 1 for all positive values.
2932 mid_min = mid_min / 2;
2933 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2936 /* Determine the amount we can change DQS (which is -mid_min) */
2937 orig_mid_min = mid_min;
2938 new_dqs = start_dqs;
2940 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2941 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2942 /* Initialize data for export structures */
2943 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2944 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2946 /* add delay to bring centre of all DQ windows to the same "level" */
2947 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2948 /* Use values before divide by 2 to reduce round off error */
2949 shift_dq = (left_edge[i] - right_edge[i] -
2950 (left_edge[min_index] - right_edge[min_index]))/2 +
2951 (orig_mid_min - mid_min);
2953 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2954 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2956 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2957 temp_dq_out1_delay = readl(addr + (i << 2));
2958 if (shift_dq + (int32_t)temp_dq_out1_delay >
2959 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2960 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2961 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2962 shift_dq = -(int32_t)temp_dq_out1_delay;
2964 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2966 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2969 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2970 left_edge[i] - shift_dq + (-mid_min),
2971 right_edge[i] + shift_dq - (-mid_min));
2972 /* To determine values for export structures */
2973 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2974 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2976 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2977 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2981 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2982 writel(0, &sdr_scc_mgr->update);
2985 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2988 * set the left and right edge of each bit to an illegal value,
2989 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2991 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2992 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2993 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2994 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2995 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2996 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2997 int32_t win_best = 0;
2999 /* Search for the/part of the window with DM shift */
3000 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3001 scc_mgr_apply_group_dm_out1_delay(d);
3002 writel(0, &sdr_scc_mgr->update);
3004 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3005 PASS_ALL_BITS, &bit_chk,
3007 /* USE Set current end of the window */
3010 * If a starting edge of our window has not been seen
3011 * this is our current start of the DM window.
3013 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3017 * If current window is bigger than best seen.
3018 * Set best seen to be current window.
3020 if ((end_curr-bgn_curr+1) > win_best) {
3021 win_best = end_curr-bgn_curr+1;
3022 bgn_best = bgn_curr;
3023 end_best = end_curr;
3026 /* We just saw a failing test. Reset temp edge */
3027 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3028 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3033 /* Reset DM delay chains to 0 */
3034 scc_mgr_apply_group_dm_out1_delay(0);
3037 * Check to see if the current window nudges up aganist 0 delay.
3038 * If so we need to continue the search by shifting DQS otherwise DQS
3039 * search begins as a new search. */
3040 if (end_curr != 0) {
3041 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3042 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3045 /* Search for the/part of the window with DQS shifts */
3046 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3048 * Note: This only shifts DQS, so are we limiting ourselve to
3049 * width of DQ unnecessarily.
3051 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3054 writel(0, &sdr_scc_mgr->update);
3055 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3056 PASS_ALL_BITS, &bit_chk,
3058 /* USE Set current end of the window */
3061 * If a beginning edge of our window has not been seen
3062 * this is our current begin of the DM window.
3064 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3068 * If current window is bigger than best seen. Set best
3069 * seen to be current window.
3071 if ((end_curr-bgn_curr+1) > win_best) {
3072 win_best = end_curr-bgn_curr+1;
3073 bgn_best = bgn_curr;
3074 end_best = end_curr;
3077 /* We just saw a failing test. Reset temp edge */
3078 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3079 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3081 /* Early exit optimization: if ther remaining delay
3082 chain space is less than already seen largest window
3085 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3091 /* assign left and right edge for cal and reporting; */
3092 left_edge[0] = -1*bgn_best;
3093 right_edge[0] = end_best;
3095 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3096 __LINE__, left_edge[0], right_edge[0]);
3098 /* Move DQS (back to orig) */
3099 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3103 /* Find middle of window for the DM bit */
3104 mid = (left_edge[0] - right_edge[0]) / 2;
3106 /* only move right, since we are not moving DQS/DQ */
3110 /* dm_marign should fail if we never find a window */
3114 dm_margin = left_edge[0] - mid;
3116 scc_mgr_apply_group_dm_out1_delay(mid);
3117 writel(0, &sdr_scc_mgr->update);
3119 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3120 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3121 right_edge[0], mid, dm_margin);
3123 gbl->fom_out += dq_margin + dqs_margin;
3125 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3126 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3127 dq_margin, dqs_margin, dm_margin);
3130 * Do not remove this line as it makes sure all of our
3131 * decisions have been applied.
3133 writel(0, &sdr_scc_mgr->update);
3134 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3137 /* calibrate the write operations */
3138 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3141 /* update info for sims */
3142 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3144 reg_file_set_stage(CAL_STAGE_WRITES);
3145 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3147 reg_file_set_group(g);
3149 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3150 set_failing_group_stage(g, CAL_STAGE_WRITES,
3151 CAL_SUBSTAGE_WRITES_CENTER);
3159 * mem_precharge_and_activate() - Precharge all banks and activate
3161 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3163 static void mem_precharge_and_activate(void)
3167 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3168 /* Test if the rank should be skipped. */
3169 if (param->skip_ranks[r])
3173 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3175 /* Precharge all banks. */
3176 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3177 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3179 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3180 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3181 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3183 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3184 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3185 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3187 /* Activate rows. */
3188 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3189 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3194 * mem_init_latency() - Configure memory RLAT and WLAT settings
3196 * Configure memory RLAT and WLAT parameters.
3198 static void mem_init_latency(void)
3201 * For AV/CV, LFIFO is hardened and always runs at full rate
3202 * so max latency in AFI clocks, used here, is correspondingly
3205 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3208 debug("%s:%d\n", __func__, __LINE__);
3211 * Read in write latency.
3212 * WL for Hard PHY does not include additive latency.
3214 wlat = readl(&data_mgr->t_wl_add);
3215 wlat += readl(&data_mgr->mem_t_add);
3217 gbl->rw_wl_nop_cycles = wlat - 1;
3219 /* Read in readl latency. */
3220 rlat = readl(&data_mgr->t_rl_add);
3222 /* Set a pretty high read latency initially. */
3223 gbl->curr_read_lat = rlat + 16;
3224 if (gbl->curr_read_lat > max_latency)
3225 gbl->curr_read_lat = max_latency;
3227 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3229 /* Advertise write latency. */
3230 writel(wlat, &phy_mgr_cfg->afi_wlat);
3234 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3236 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3238 static void mem_skip_calibrate(void)
3240 uint32_t vfifo_offset;
3243 debug("%s:%d\n", __func__, __LINE__);
3244 /* Need to update every shadow register set used by the interface */
3245 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3246 r += NUM_RANKS_PER_SHADOW_REG) {
3248 * Set output phase alignment settings appropriate for
3251 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3252 scc_mgr_set_dqs_en_phase(i, 0);
3253 #if IO_DLL_CHAIN_LENGTH == 6
3254 scc_mgr_set_dqdqs_output_phase(i, 6);
3256 scc_mgr_set_dqdqs_output_phase(i, 7);
3261 * Write data arrives to the I/O two cycles before write
3262 * latency is reached (720 deg).
3263 * -> due to bit-slip in a/c bus
3264 * -> to allow board skew where dqs is longer than ck
3265 * -> how often can this happen!?
3266 * -> can claim back some ptaps for high freq
3267 * support if we can relax this, but i digress...
3269 * The write_clk leads mem_ck by 90 deg
3270 * The minimum ptap of the OPA is 180 deg
3271 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3272 * The write_clk is always delayed by 2 ptaps
3274 * Hence, to make DQS aligned to CK, we need to delay
3276 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3278 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3279 * gives us the number of ptaps, which simplies to:
3281 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3283 scc_mgr_set_dqdqs_output_phase(i,
3284 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3286 writel(0xff, &sdr_scc_mgr->dqs_ena);
3287 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3289 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3290 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3291 SCC_MGR_GROUP_COUNTER_OFFSET);
3293 writel(0xff, &sdr_scc_mgr->dq_ena);
3294 writel(0xff, &sdr_scc_mgr->dm_ena);
3295 writel(0, &sdr_scc_mgr->update);
3298 /* Compensate for simulation model behaviour */
3299 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3300 scc_mgr_set_dqs_bus_in_delay(i, 10);
3301 scc_mgr_load_dqs(i);
3303 writel(0, &sdr_scc_mgr->update);
3306 * ArriaV has hard FIFOs that can only be initialized by incrementing
3309 vfifo_offset = CALIB_VFIFO_OFFSET;
3310 for (j = 0; j < vfifo_offset; j++)
3311 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3312 writel(0, &phy_mgr_cmd->fifo_reset);
3315 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3316 * setting from generation-time constant.
3318 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3319 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3323 * mem_calibrate() - Memory calibration entry point.
3325 * Perform memory calibration.
3327 static uint32_t mem_calibrate(void)
3330 uint32_t rank_bgn, sr;
3331 uint32_t write_group, write_test_bgn;
3332 uint32_t read_group, read_test_bgn;
3333 uint32_t run_groups, current_run;
3334 uint32_t failing_groups = 0;
3335 uint32_t group_failed = 0;
3337 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3338 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3340 debug("%s:%d\n", __func__, __LINE__);
3342 /* Initialize the data settings */
3343 gbl->error_substage = CAL_SUBSTAGE_NIL;
3344 gbl->error_stage = CAL_STAGE_NIL;
3345 gbl->error_group = 0xff;
3349 /* Initialize WLAT and RLAT. */
3352 /* Initialize bit slips. */
3353 mem_precharge_and_activate();
3355 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3356 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3357 SCC_MGR_GROUP_COUNTER_OFFSET);
3358 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3360 scc_mgr_set_hhp_extras();
3362 scc_set_bypass_mode(i);
3365 /* Calibration is skipped. */
3366 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3368 * Set VFIFO and LFIFO to instant-on settings in skip
3371 mem_skip_calibrate();
3374 * Do not remove this line as it makes sure all of our
3375 * decisions have been applied.
3377 writel(0, &sdr_scc_mgr->update);
3381 /* Calibration is not skipped. */
3382 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3384 * Zero all delay chain/phase settings for all
3385 * groups and all shadow register sets.
3389 run_groups = ~param->skip_groups;
3391 for (write_group = 0, write_test_bgn = 0; write_group
3392 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3393 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3395 /* Initialize the group failure */
3398 current_run = run_groups & ((1 <<
3399 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3400 run_groups = run_groups >>
3401 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3403 if (current_run == 0)
3406 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3407 SCC_MGR_GROUP_COUNTER_OFFSET);
3408 scc_mgr_zero_group(write_group, 0);
3410 for (read_group = write_group * rwdqs_ratio,
3412 read_group < (write_group + 1) * rwdqs_ratio;
3414 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3415 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3418 /* Calibrate the VFIFO */
3419 if (rw_mgr_mem_calibrate_vfifo(read_group,
3423 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3426 /* The group failed, we're done. */
3430 /* Calibrate the output side */
3431 for (rank_bgn = 0, sr = 0;
3432 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3433 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3434 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3437 /* Not needed in quick mode! */
3438 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3442 * Determine if this set of ranks
3443 * should be skipped entirely.
3445 if (param->skip_shadow_regs[sr])
3448 /* Calibrate WRITEs */
3449 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3450 write_group, write_test_bgn))
3454 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3458 /* Some group failed, we're done. */
3462 for (read_group = write_group * rwdqs_ratio,
3464 read_group < (write_group + 1) * rwdqs_ratio;
3466 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3467 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3470 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3474 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3477 /* The group failed, we're done. */
3481 /* No group failed, continue as usual. */
3484 grp_failed: /* A group failed, increment the counter. */
3489 * USER If there are any failing groups then report
3492 if (failing_groups != 0)
3495 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3499 * If we're skipping groups as part of debug,
3500 * don't calibrate LFIFO.
3502 if (param->skip_groups != 0)
3505 /* Calibrate the LFIFO */
3506 if (!rw_mgr_mem_calibrate_lfifo())
3511 * Do not remove this line as it makes sure all of our decisions
3512 * have been applied.
3514 writel(0, &sdr_scc_mgr->update);
3519 * run_mem_calibrate() - Perform memory calibration
3521 * This function triggers the entire memory calibration procedure.
3523 static int run_mem_calibrate(void)
3527 debug("%s:%d\n", __func__, __LINE__);
3529 /* Reset pass/fail status shown on afi_cal_success/fail */
3530 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3532 /* Stop tracking manager. */
3533 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3535 phy_mgr_initialize();
3536 rw_mgr_mem_initialize();
3538 /* Perform the actual memory calibration. */
3539 pass = mem_calibrate();
3541 mem_precharge_and_activate();
3542 writel(0, &phy_mgr_cmd->fifo_reset);
3545 rw_mgr_mem_handoff();
3547 * In Hard PHY this is a 2-bit control:
3549 * 1: DDIO Mux Select
3551 writel(0x2, &phy_mgr_cfg->mux_sel);
3553 /* Start tracking manager. */
3554 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3560 * debug_mem_calibrate() - Report result of memory calibration
3561 * @pass: Value indicating whether calibration passed or failed
3563 * This function reports the results of the memory calibration
3564 * and writes debug information into the register file.
3566 static void debug_mem_calibrate(int pass)
3568 uint32_t debug_info;
3571 printf("%s: CALIBRATION PASSED\n", __FILE__);
3576 if (gbl->fom_in > 0xff)
3579 if (gbl->fom_out > 0xff)
3580 gbl->fom_out = 0xff;
3582 /* Update the FOM in the register file */
3583 debug_info = gbl->fom_in;
3584 debug_info |= gbl->fom_out << 8;
3585 writel(debug_info, &sdr_reg_file->fom);
3587 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3588 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3590 printf("%s: CALIBRATION FAILED\n", __FILE__);
3592 debug_info = gbl->error_stage;
3593 debug_info |= gbl->error_substage << 8;
3594 debug_info |= gbl->error_group << 16;
3596 writel(debug_info, &sdr_reg_file->failing_stage);
3597 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3598 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3600 /* Update the failing group/stage in the register file */
3601 debug_info = gbl->error_stage;
3602 debug_info |= gbl->error_substage << 8;
3603 debug_info |= gbl->error_group << 16;
3604 writel(debug_info, &sdr_reg_file->failing_stage);
3607 printf("%s: Calibration complete\n", __FILE__);
3611 * hc_initialize_rom_data() - Initialize ROM data
3613 * Initialize ROM data.
3615 static void hc_initialize_rom_data(void)
3619 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3620 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3621 writel(inst_rom_init[i], addr + (i << 2));
3623 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3624 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3625 writel(ac_rom_init[i], addr + (i << 2));
3629 * initialize_reg_file() - Initialize SDR register file
3631 * Initialize SDR register file.
3633 static void initialize_reg_file(void)
3635 /* Initialize the register file with the correct data */
3636 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3637 writel(0, &sdr_reg_file->debug_data_addr);
3638 writel(0, &sdr_reg_file->cur_stage);
3639 writel(0, &sdr_reg_file->fom);
3640 writel(0, &sdr_reg_file->failing_stage);
3641 writel(0, &sdr_reg_file->debug1);
3642 writel(0, &sdr_reg_file->debug2);
3646 * initialize_hps_phy() - Initialize HPS PHY
3648 * Initialize HPS PHY.
3650 static void initialize_hps_phy(void)
3654 * Tracking also gets configured here because it's in the
3657 uint32_t trk_sample_count = 7500;
3658 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3660 * Format is number of outer loops in the 16 MSB, sample
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3666 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3667 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3668 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3669 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3670 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3672 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3673 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3675 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3676 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3678 writel(reg, &sdr_ctrl->phy_ctrl0);
3681 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3683 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3684 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3685 trk_long_idle_sample_count);
3686 writel(reg, &sdr_ctrl->phy_ctrl1);
3689 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3690 trk_long_idle_sample_count >>
3691 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3692 writel(reg, &sdr_ctrl->phy_ctrl2);
3696 * initialize_tracking() - Initialize tracking
3698 * Initialize the register file with usable initial data.
3700 static void initialize_tracking(void)
3703 * Initialize the register file with the correct data.
3704 * Compute usable version of value in case we skip full
3705 * computation later.
3707 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3708 &sdr_reg_file->dtaps_per_ptap);
3710 /* trk_sample_count */
3711 writel(7500, &sdr_reg_file->trk_sample_count);
3713 /* longidle outer loop [15:0] */
3714 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3717 * longidle sample count [31:24]
3718 * trfc, worst case of 933Mhz 4Gb [23:16]
3719 * trcd, worst case [15:8]
3722 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3723 &sdr_reg_file->delays);
3726 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3727 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3728 &sdr_reg_file->trk_rw_mgr_addr);
3730 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3731 &sdr_reg_file->trk_read_dqs_width);
3734 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3735 &sdr_reg_file->trk_rfsh);
3738 int sdram_calibration_full(void)
3740 struct param_type my_param;
3741 struct gbl_type my_gbl;
3744 memset(&my_param, 0, sizeof(my_param));
3745 memset(&my_gbl, 0, sizeof(my_gbl));
3750 /* Set the calibration enabled by default */
3751 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3753 * Only sweep all groups (regardless of fail state) by default
3754 * Set enabled read test by default.
3756 #if DISABLE_GUARANTEED_READ
3757 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3759 /* Initialize the register file */
3760 initialize_reg_file();
3762 /* Initialize any PHY CSR */
3763 initialize_hps_phy();
3765 scc_mgr_initialize();
3767 initialize_tracking();
3769 printf("%s: Preparing to start memory calibration\n", __FILE__);
3771 debug("%s:%d\n", __func__, __LINE__);
3772 debug_cond(DLEVEL == 1,
3773 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3774 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3775 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3776 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3777 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3778 debug_cond(DLEVEL == 1,
3779 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3780 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3781 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3782 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3783 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3784 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3785 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3786 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3787 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3788 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3789 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3790 IO_IO_OUT2_DELAY_MAX);
3791 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3792 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3794 hc_initialize_rom_data();
3796 /* update info for sims */
3797 reg_file_set_stage(CAL_STAGE_NIL);
3798 reg_file_set_group(0);
3801 * Load global needed for those actions that require
3802 * some dynamic calibration support.
3804 dyn_calib_steps = STATIC_CALIB_STEPS;
3806 * Load global to allow dynamic selection of delay loop settings
3807 * based on calibration mode.
3809 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3810 skip_delay_mask = 0xff;
3812 skip_delay_mask = 0x0;
3814 pass = run_mem_calibrate();
3815 debug_mem_calibrate(pass);