2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group);
18 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
19 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
21 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
22 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
24 static struct socfpga_sdr_reg_file *sdr_reg_file =
25 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
27 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
28 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
30 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
31 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
33 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
34 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
36 static struct socfpga_data_mgr *data_mgr =
37 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
39 static struct socfpga_sdr_ctrl *sdr_ctrl =
40 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
45 * In order to reduce ROM size, most of the selectable calibration steps are
46 * decided at compile time based on the user's calibration mode selection,
47 * as captured by the STATIC_CALIB_STEPS selection below.
49 * However, to support simulation-time selection of fast simulation mode, where
50 * we skip everything except the bare minimum, we need a few of the steps to
51 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
52 * check, which is based on the rtl-supplied value, or we dynamically compute
53 * the value to use based on the dynamically-chosen calibration mode
57 #define STATIC_IN_RTL_SIM 0
58 #define STATIC_SKIP_DELAY_LOOPS 0
60 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
61 STATIC_SKIP_DELAY_LOOPS)
63 /* calibration steps requested by the rtl */
64 uint16_t dyn_calib_steps;
67 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
68 * instead of static, we use boolean logic to select between
69 * non-skip and skip values
71 * The mask is set to include all bits when not-skipping, but is
75 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
77 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
78 ((non_skip_value) & skip_delay_mask)
81 struct param_type *param;
82 uint32_t curr_shadow_reg;
84 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
85 uint32_t write_group, uint32_t use_dm,
86 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
88 static void set_failing_group_stage(uint32_t group, uint32_t stage,
92 * Only set the global stage if there was not been any other
95 if (gbl->error_stage == CAL_STAGE_NIL) {
96 gbl->error_substage = substage;
97 gbl->error_stage = stage;
98 gbl->error_group = group;
102 static void reg_file_set_group(u16 set_group)
104 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
107 static void reg_file_set_stage(u8 set_stage)
109 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
112 static void reg_file_set_sub_stage(u8 set_sub_stage)
114 set_sub_stage &= 0xff;
115 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 static void initialize(void)
120 debug("%s:%d\n", __func__, __LINE__);
121 /* USER calibration has control over path to memory */
123 * In Hard PHY this is a 2-bit control:
127 writel(0x3, &phy_mgr_cfg->mux_sel);
129 /* USER memory clock is not stable we begin initialization */
130 writel(0, &phy_mgr_cfg->reset_mem_stbl);
132 /* USER calibration status all set to zero */
133 writel(0, &phy_mgr_cfg->cal_status);
135 writel(0, &phy_mgr_cfg->cal_debug_info);
137 if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
138 param->read_correct_mask_vg = ((uint32_t)1 <<
139 (RW_MGR_MEM_DQ_PER_READ_DQS /
140 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
141 param->write_correct_mask_vg = ((uint32_t)1 <<
142 (RW_MGR_MEM_DQ_PER_READ_DQS /
143 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
144 param->read_correct_mask = ((uint32_t)1 <<
145 RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
146 param->write_correct_mask = ((uint32_t)1 <<
147 RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
148 param->dm_correct_mask = ((uint32_t)1 <<
149 (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
154 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
156 uint32_t odt_mask_0 = 0;
157 uint32_t odt_mask_1 = 0;
158 uint32_t cs_and_odt_mask;
160 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
161 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
169 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
171 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
172 /* - Dual-Slot , Single-Rank
173 * (1 chip-select per DIMM)
175 * - RDIMM, 4 total CS (2 CS per DIMM)
177 * Since MEM_NUMBER_OF_RANKS is 2 they are
179 * with 2 CS each (special for RDIMM)
180 * Read: Turn on ODT on the opposite rank
181 * Write: Turn on ODT on all ranks
183 odt_mask_0 = 0x3 & ~(1 << rank);
187 * USER - Single-Slot , Dual-rank DIMMs
188 * (2 chip-selects per DIMM)
189 * USER Read: Turn on ODT off on all ranks
190 * USER Write: Turn on ODT on active rank
193 odt_mask_1 = 0x3 & (1 << rank);
198 * ----------+-----------------------+
201 * Read From +-----------------------+
202 * Rank | 3 | 2 | 1 | 0 |
203 * ----------+-----+-----+-----+-----+
204 * 0 | 0 | 1 | 0 | 0 |
205 * 1 | 1 | 0 | 0 | 0 |
206 * 2 | 0 | 0 | 0 | 1 |
207 * 3 | 0 | 0 | 1 | 0 |
208 * ----------+-----+-----+-----+-----+
211 * ----------+-----------------------+
214 * Write To +-----------------------+
215 * Rank | 3 | 2 | 1 | 0 |
216 * ----------+-----+-----+-----+-----+
217 * 0 | 0 | 1 | 0 | 1 |
218 * 1 | 1 | 0 | 1 | 0 |
219 * 2 | 0 | 1 | 0 | 1 |
220 * 3 | 1 | 0 | 1 | 0 |
221 * ----------+-----+-----+-----+-----+
248 (0xFF & ~(1 << rank)) |
249 ((0xFF & odt_mask_0) << 8) |
250 ((0xFF & odt_mask_1) << 16);
251 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
252 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
255 static void scc_mgr_initialize(void)
257 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_RFILE_OFFSET;
260 * Clear register file for HPS
261 * 16 (2^4) is the size of the full register file in the scc mgr:
262 * RFILE_DEPTH = log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
263 * MEM_IF_READ_DQS_WIDTH - 1) + 1;
266 for (i = 0; i < 16; i++) {
267 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
268 __func__, __LINE__, i);
269 writel(0, addr + (i << 2));
273 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group,
276 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
278 /* Load the setting in the SCC manager */
279 writel(delay, addr + (read_group << 2));
282 static void scc_mgr_set_dqs_io_in_delay(uint32_t write_group,
285 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
287 writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
290 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
292 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_PHASE_OFFSET;
294 /* Load the setting in the SCC manager */
295 writel(phase, addr + (read_group << 2));
298 static void scc_mgr_set_dqs_en_phase_all_ranks(uint32_t read_group,
302 uint32_t update_scan_chains;
304 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
305 r += NUM_RANKS_PER_SHADOW_REG) {
307 * USER although the h/w doesn't support different phases per
308 * shadow register, for simplicity our scc manager modeling
309 * keeps different phase settings per shadow reg, and it's
310 * important for us to keep them in sync to match h/w.
311 * for efficiency, the scan chain update should occur only
314 update_scan_chains = (r == 0) ? 1 : 0;
316 scc_mgr_set_dqs_en_phase(read_group, phase);
318 if (update_scan_chains) {
319 writel(read_group, &sdr_scc_mgr->dqs_ena);
320 writel(0, &sdr_scc_mgr->update);
325 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group,
328 u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQDQS_OUT_PHASE_OFFSET;
330 /* Load the setting in the SCC manager */
331 writel(phase, addr + (write_group << 2));
334 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
338 uint32_t update_scan_chains;
340 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
341 r += NUM_RANKS_PER_SHADOW_REG) {
343 * USER although the h/w doesn't support different phases per
344 * shadow register, for simplicity our scc manager modeling
345 * keeps different phase settings per shadow reg, and it's
346 * important for us to keep them in sync to match h/w.
347 * for efficiency, the scan chain update should occur only
350 update_scan_chains = (r == 0) ? 1 : 0;
352 scc_mgr_set_dqdqs_output_phase(write_group, phase);
354 if (update_scan_chains) {
355 writel(write_group, &sdr_scc_mgr->dqs_ena);
356 writel(0, &sdr_scc_mgr->update);
361 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
363 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_EN_DELAY_OFFSET;
365 /* Load the setting in the SCC manager */
366 writel(delay + IO_DQS_EN_DELAY_OFFSET, addr +
370 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
375 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
376 r += NUM_RANKS_PER_SHADOW_REG) {
377 scc_mgr_set_dqs_en_delay(read_group, delay);
379 writel(read_group, &sdr_scc_mgr->dqs_ena);
381 * In shadow register mode, the T11 settings are stored in
382 * registers in the core, which are updated by the DQS_ENA
383 * signals. Not issuing the SCC_MGR_UPD command allows us to
384 * save lots of rank switching overhead, by calling
385 * select_shadow_regs_for_update with update_scan_chains
388 writel(0, &sdr_scc_mgr->update);
391 * In shadow register mode, the T11 settings are stored in
392 * registers in the core, which are updated by the DQS_ENA
393 * signals. Not issuing the SCC_MGR_UPD command allows us to
394 * save lots of rank switching overhead, by calling
395 * select_shadow_regs_for_update with update_scan_chains
398 writel(0, &sdr_scc_mgr->update);
401 static void scc_mgr_set_oct_out1_delay(uint32_t write_group, uint32_t delay)
404 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_OCT_OUT1_DELAY_OFFSET;
407 * Load the setting in the SCC manager
408 * Although OCT affects only write data, the OCT delay is controlled
409 * by the DQS logic block which is instantiated once per read group.
410 * For protocols where a write group consists of multiple read groups,
411 * the setting must be set multiple times.
413 for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
414 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
415 read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
416 RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
417 writel(delay, addr + (read_group << 2));
420 static void scc_mgr_set_dq_out1_delay(uint32_t write_group,
421 uint32_t dq_in_group, uint32_t delay)
423 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
425 /* Load the setting in the SCC manager */
426 writel(delay, addr + (dq_in_group << 2));
429 static void scc_mgr_set_dq_in_delay(uint32_t write_group,
430 uint32_t dq_in_group, uint32_t delay)
432 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
434 /* Load the setting in the SCC manager */
435 writel(delay, addr + (dq_in_group << 2));
438 static void scc_mgr_set_hhp_extras(void)
441 * Load the fixed setting in the SCC manager
442 * bits: 0:0 = 1'b1 - dqs bypass
443 * bits: 1:1 = 1'b1 - dq bypass
444 * bits: 4:2 = 3'b001 - rfifo_mode
445 * bits: 6:5 = 2'b01 - rfifo clock_select
446 * bits: 7:7 = 1'b0 - separate gating from ungating setting
447 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
449 uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
450 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
452 writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
455 static void scc_mgr_set_dqs_out1_delay(uint32_t write_group,
458 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
460 /* Load the setting in the SCC manager */
461 writel(delay, addr + (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
464 static void scc_mgr_set_dm_out1_delay(uint32_t write_group,
465 uint32_t dm, uint32_t delay)
467 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
469 /* Load the setting in the SCC manager */
471 ((RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm) << 2));
475 * USER Zero all DQS config
476 * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
478 static void scc_mgr_zero_all(void)
483 * USER Zero all DQS config settings, across all groups and all
486 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
487 NUM_RANKS_PER_SHADOW_REG) {
488 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
490 * The phases actually don't exist on a per-rank basis,
491 * but there's no harm updating them several times, so
492 * let's keep the code simple.
494 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
495 scc_mgr_set_dqs_en_phase(i, 0);
496 scc_mgr_set_dqs_en_delay(i, 0);
499 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
500 scc_mgr_set_dqdqs_output_phase(i, 0);
501 /* av/cv don't have out2 */
502 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
506 /* multicast to all DQS group enables */
507 writel(0xff, &sdr_scc_mgr->dqs_ena);
508 writel(0, &sdr_scc_mgr->update);
511 static void scc_set_bypass_mode(uint32_t write_group, uint32_t mode)
513 /* mode = 0 : Do NOT bypass - Half Rate Mode */
514 /* mode = 1 : Bypass - Full Rate Mode */
516 /* only need to set once for all groups, pins, dq, dqs, dm */
517 if (write_group == 0) {
518 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
520 scc_mgr_set_hhp_extras();
521 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
524 /* multicast to all DQ enables */
525 writel(0xff, &sdr_scc_mgr->dq_ena);
526 writel(0xff, &sdr_scc_mgr->dm_ena);
528 /* update current DQS IO enable */
529 writel(0, &sdr_scc_mgr->dqs_io_ena);
531 /* update the DQS logic */
532 writel(write_group, &sdr_scc_mgr->dqs_ena);
535 writel(0, &sdr_scc_mgr->update);
538 static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
543 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
544 NUM_RANKS_PER_SHADOW_REG) {
545 /* Zero all DQ config settings */
546 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
547 scc_mgr_set_dq_out1_delay(write_group, i, 0);
549 scc_mgr_set_dq_in_delay(write_group, i, 0);
552 /* multicast to all DQ enables */
553 writel(0xff, &sdr_scc_mgr->dq_ena);
555 /* Zero all DM config settings */
556 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
557 scc_mgr_set_dm_out1_delay(write_group, i, 0);
560 /* multicast to all DM enables */
561 writel(0xff, &sdr_scc_mgr->dm_ena);
563 /* zero all DQS io settings */
565 scc_mgr_set_dqs_io_in_delay(write_group, 0);
566 /* av/cv don't have out2 */
567 scc_mgr_set_dqs_out1_delay(write_group, IO_DQS_OUT_RESERVE);
568 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
569 scc_mgr_load_dqs_for_write_group(write_group);
571 /* multicast to all DQS IO enables (only 1) */
572 writel(0, &sdr_scc_mgr->dqs_io_ena);
574 /* hit update to zero everything */
575 writel(0, &sdr_scc_mgr->update);
579 /* load up dqs config settings */
580 static void scc_mgr_load_dqs(uint32_t dqs)
582 writel(dqs, &sdr_scc_mgr->dqs_ena);
585 static void scc_mgr_load_dqs_for_write_group(uint32_t write_group)
588 uint32_t addr = (u32)&sdr_scc_mgr->dqs_ena;
590 * Although OCT affects only write data, the OCT delay is controlled
591 * by the DQS logic block which is instantiated once per read group.
592 * For protocols where a write group consists of multiple read groups,
593 * the setting must be scanned multiple times.
595 for (read_group = write_group * RW_MGR_MEM_IF_READ_DQS_WIDTH /
596 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
597 read_group < (write_group + 1) * RW_MGR_MEM_IF_READ_DQS_WIDTH /
598 RW_MGR_MEM_IF_WRITE_DQS_WIDTH; ++read_group)
599 writel(read_group, addr);
602 /* load up dqs io config settings */
603 static void scc_mgr_load_dqs_io(void)
605 writel(0, &sdr_scc_mgr->dqs_io_ena);
608 /* load up dq config settings */
609 static void scc_mgr_load_dq(uint32_t dq_in_group)
611 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
614 /* load up dm config settings */
615 static void scc_mgr_load_dm(uint32_t dm)
617 writel(dm, &sdr_scc_mgr->dm_ena);
621 * apply and load a particular input delay for the DQ pins in a group
622 * group_bgn is the index of the first dq pin (in the write group)
624 static void scc_mgr_apply_group_dq_in_delay(uint32_t write_group,
625 uint32_t group_bgn, uint32_t delay)
629 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
630 scc_mgr_set_dq_in_delay(write_group, p, delay);
635 /* apply and load a particular output delay for the DQ pins in a group */
636 static void scc_mgr_apply_group_dq_out1_delay(uint32_t write_group,
642 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
643 scc_mgr_set_dq_out1_delay(write_group, i, delay1);
648 /* apply and load a particular output delay for the DM pins in a group */
649 static void scc_mgr_apply_group_dm_out1_delay(uint32_t write_group,
654 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
655 scc_mgr_set_dm_out1_delay(write_group, i, delay1);
661 /* apply and load delay on both DQS and OCT out1 */
662 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
665 scc_mgr_set_dqs_out1_delay(write_group, delay);
666 scc_mgr_load_dqs_io();
668 scc_mgr_set_oct_out1_delay(write_group, delay);
669 scc_mgr_load_dqs_for_write_group(write_group);
672 /* apply a delay to the entire output side: DQ, DM, DQS, OCT */
673 static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
677 uint32_t i, p, new_delay;
680 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
681 new_delay = READ_SCC_DQ_OUT2_DELAY;
684 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
685 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
686 %u > %lu => %lu", __func__, __LINE__,
687 write_group, group_bgn, delay, i, p, new_delay,
688 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
689 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
690 new_delay = IO_IO_OUT2_DELAY_MAX;
697 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
698 new_delay = READ_SCC_DM_IO_OUT2_DELAY;
701 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
702 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
703 %u > %lu => %lu\n", __func__, __LINE__,
704 write_group, group_bgn, delay, i, new_delay,
705 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
706 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
707 new_delay = IO_IO_OUT2_DELAY_MAX;
714 new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
717 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
718 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
719 " adding %u to OUT1\n", __func__, __LINE__,
720 write_group, group_bgn, delay, new_delay,
721 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
722 new_delay - IO_IO_OUT2_DELAY_MAX);
723 scc_mgr_set_dqs_out1_delay(write_group, new_delay -
724 IO_IO_OUT2_DELAY_MAX);
725 new_delay = IO_IO_OUT2_DELAY_MAX;
728 scc_mgr_load_dqs_io();
731 new_delay = READ_SCC_OCT_OUT2_DELAY;
734 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
735 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
736 " adding %u to OUT1\n", __func__, __LINE__,
737 write_group, group_bgn, delay, new_delay,
738 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
739 new_delay - IO_IO_OUT2_DELAY_MAX);
740 scc_mgr_set_oct_out1_delay(write_group, new_delay -
741 IO_IO_OUT2_DELAY_MAX);
742 new_delay = IO_IO_OUT2_DELAY_MAX;
745 scc_mgr_load_dqs_for_write_group(write_group);
749 * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
752 static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
753 uint32_t write_group, uint32_t group_bgn, uint32_t delay)
757 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
758 r += NUM_RANKS_PER_SHADOW_REG) {
759 scc_mgr_apply_group_all_out_delay_add(write_group,
761 writel(0, &sdr_scc_mgr->update);
765 /* optimization used to recover some slots in ddr3 inst_rom */
766 /* could be applied to other protocols if we wanted to */
767 static void set_jump_as_return(void)
770 * to save space, we replace return with jump to special shared
771 * RETURN instruction so we set the counter to large value so that
774 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
775 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
779 * should always use constants as argument to ensure all computations are
780 * performed at compile time
782 static void delay_for_n_mem_clocks(const uint32_t clocks)
789 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
792 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
793 /* scale (rounding up) to get afi clocks */
796 * Note, we don't bother accounting for being off a little bit
797 * because of a few extra instructions in outer loops
798 * Note, the loops have a test at the end, and do the test before
799 * the decrement, and so always perform the loop
800 * 1 time more than the counter value
802 if (afi_clocks == 0) {
804 } else if (afi_clocks <= 0x100) {
805 inner = afi_clocks-1;
808 } else if (afi_clocks <= 0x10000) {
810 outer = (afi_clocks-1) >> 8;
815 c_loop = (afi_clocks-1) >> 16;
819 * rom instructions are structured as follows:
821 * IDLE_LOOP2: jnz cntr0, TARGET_A
822 * IDLE_LOOP1: jnz cntr1, TARGET_B
825 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
826 * TARGET_B is set to IDLE_LOOP2 as well
828 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
829 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
831 * a little confusing, but it helps save precious space in the inst_rom
832 * and sequencer rom and keeps the delays more accurate and reduces
835 if (afi_clocks <= 0x100) {
836 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
837 &sdr_rw_load_mgr_regs->load_cntr1);
839 writel(RW_MGR_IDLE_LOOP1,
840 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
842 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
843 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
845 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
846 &sdr_rw_load_mgr_regs->load_cntr0);
848 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
849 &sdr_rw_load_mgr_regs->load_cntr1);
851 writel(RW_MGR_IDLE_LOOP2,
852 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
854 writel(RW_MGR_IDLE_LOOP2,
855 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
857 /* hack to get around compiler not being smart enough */
858 if (afi_clocks <= 0x10000) {
859 /* only need to run once */
860 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
861 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
864 writel(RW_MGR_IDLE_LOOP2,
865 SDR_PHYGRP_RWMGRGRP_ADDRESS |
866 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
867 } while (c_loop-- != 0);
870 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
873 static void rw_mgr_mem_initialize(void)
876 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
877 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
879 debug("%s:%d\n", __func__, __LINE__);
881 /* The reset / cke part of initialization is broadcasted to all ranks */
882 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
883 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
886 * Here's how you load register for a loop
887 * Counters are located @ 0x800
888 * Jump address are located @ 0xC00
889 * For both, registers 0 to 3 are selected using bits 3 and 2, like
890 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
891 * I know this ain't pretty, but Avalon bus throws away the 2 least
895 /* start with memory RESET activated */
900 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
901 * If a and b are the number of iteration in 2 nested loops
902 * it takes the following number of cycles to complete the operation:
903 * number_of_cycles = ((2 + n) * a + 2) * b
904 * where n is the number of instruction in the inner loop
905 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
910 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
911 &sdr_rw_load_mgr_regs->load_cntr0);
912 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
913 &sdr_rw_load_mgr_regs->load_cntr1);
914 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
915 &sdr_rw_load_mgr_regs->load_cntr2);
917 /* Load jump address */
918 writel(RW_MGR_INIT_RESET_0_CKE_0,
919 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
920 writel(RW_MGR_INIT_RESET_0_CKE_0,
921 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
922 writel(RW_MGR_INIT_RESET_0_CKE_0,
923 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
925 /* Execute count instruction */
926 writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
928 /* indicate that memory is stable */
929 writel(1, &phy_mgr_cfg->reset_mem_stbl);
932 * transition the RESET to high
937 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
938 * If a and b are the number of iteration in 2 nested loops
939 * it takes the following number of cycles to complete the operation
940 * number_of_cycles = ((2 + n) * a + 2) * b
941 * where n is the number of instruction in the inner loop
942 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
947 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
948 &sdr_rw_load_mgr_regs->load_cntr0);
949 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
950 &sdr_rw_load_mgr_regs->load_cntr1);
951 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
952 &sdr_rw_load_mgr_regs->load_cntr2);
954 /* Load jump address */
955 writel(RW_MGR_INIT_RESET_1_CKE_0,
956 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
957 writel(RW_MGR_INIT_RESET_1_CKE_0,
958 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
959 writel(RW_MGR_INIT_RESET_1_CKE_0,
960 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
962 writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
964 /* bring up clock enable */
966 /* tXRP < 250 ck cycles */
967 delay_for_n_mem_clocks(250);
969 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
970 if (param->skip_ranks[r]) {
971 /* request to skip the rank */
976 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
979 * USER Use Mirror-ed commands for odd ranks if address
982 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
983 set_jump_as_return();
984 writel(RW_MGR_MRS2_MIRR, grpaddr);
985 delay_for_n_mem_clocks(4);
986 set_jump_as_return();
987 writel(RW_MGR_MRS3_MIRR, grpaddr);
988 delay_for_n_mem_clocks(4);
989 set_jump_as_return();
990 writel(RW_MGR_MRS1_MIRR, grpaddr);
991 delay_for_n_mem_clocks(4);
992 set_jump_as_return();
993 writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
995 set_jump_as_return();
996 writel(RW_MGR_MRS2, grpaddr);
997 delay_for_n_mem_clocks(4);
998 set_jump_as_return();
999 writel(RW_MGR_MRS3, grpaddr);
1000 delay_for_n_mem_clocks(4);
1001 set_jump_as_return();
1002 writel(RW_MGR_MRS1, grpaddr);
1003 set_jump_as_return();
1004 writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
1006 set_jump_as_return();
1007 writel(RW_MGR_ZQCL, grpaddr);
1009 /* tZQinit = tDLLK = 512 ck cycles */
1010 delay_for_n_mem_clocks(512);
1015 * At the end of calibration we have to program the user settings in, and
1016 * USER hand off the memory to the user.
1018 static void rw_mgr_mem_handoff(void)
1021 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1022 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1024 debug("%s:%d\n", __func__, __LINE__);
1025 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
1026 if (param->skip_ranks[r])
1027 /* request to skip the rank */
1030 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1032 /* precharge all banks ... */
1033 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
1035 /* load up MR settings specified by user */
1038 * Use Mirror-ed commands for odd ranks if address
1041 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1042 set_jump_as_return();
1043 writel(RW_MGR_MRS2_MIRR, grpaddr);
1044 delay_for_n_mem_clocks(4);
1045 set_jump_as_return();
1046 writel(RW_MGR_MRS3_MIRR, grpaddr);
1047 delay_for_n_mem_clocks(4);
1048 set_jump_as_return();
1049 writel(RW_MGR_MRS1_MIRR, grpaddr);
1050 delay_for_n_mem_clocks(4);
1051 set_jump_as_return();
1052 writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
1054 set_jump_as_return();
1055 writel(RW_MGR_MRS2, grpaddr);
1056 delay_for_n_mem_clocks(4);
1057 set_jump_as_return();
1058 writel(RW_MGR_MRS3, grpaddr);
1059 delay_for_n_mem_clocks(4);
1060 set_jump_as_return();
1061 writel(RW_MGR_MRS1, grpaddr);
1062 delay_for_n_mem_clocks(4);
1063 set_jump_as_return();
1064 writel(RW_MGR_MRS0_USER, grpaddr);
1067 * USER need to wait tMOD (12CK or 15ns) time before issuing
1068 * other commands, but we will have plenty of NIOS cycles before
1069 * actual handoff so its okay.
1075 * performs a guaranteed read on the patterns we are going to use during a
1076 * read test to ensure memory works
1078 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1079 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1083 uint32_t correct_mask_vg;
1084 uint32_t tmp_bit_chk;
1085 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1086 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1088 uint32_t base_rw_mgr;
1090 *bit_chk = param->read_correct_mask;
1091 correct_mask_vg = param->read_correct_mask_vg;
1093 for (r = rank_bgn; r < rank_end; r++) {
1094 if (param->skip_ranks[r])
1095 /* request to skip the rank */
1099 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1101 /* Load up a constant bursts of read commands */
1102 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1103 writel(RW_MGR_GUARANTEED_READ,
1104 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1106 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1107 writel(RW_MGR_GUARANTEED_READ_CONT,
1108 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1111 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1112 /* reset the fifos to get pointers to known state */
1114 writel(0, &phy_mgr_cmd->fifo_reset);
1115 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1116 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1118 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1119 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1121 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1122 writel(RW_MGR_GUARANTEED_READ, addr +
1123 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1126 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1127 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1132 *bit_chk &= tmp_bit_chk;
1135 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1136 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1138 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1139 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1140 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1141 (long unsigned int)(*bit_chk == param->read_correct_mask));
1142 return *bit_chk == param->read_correct_mask;
1145 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1146 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1148 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1149 num_tries, bit_chk, 1);
1152 /* load up the patterns we are going to use during a read test */
1153 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1157 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1158 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1160 debug("%s:%d\n", __func__, __LINE__);
1161 for (r = rank_bgn; r < rank_end; r++) {
1162 if (param->skip_ranks[r])
1163 /* request to skip the rank */
1167 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1169 /* Load up a constant bursts */
1170 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1172 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1173 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1175 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1177 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1178 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1180 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1182 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1183 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1185 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1187 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1188 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1190 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1191 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1194 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1198 * try a read and see if it returns correct data back. has dummy reads
1199 * inserted into the mix used to align dqs enable. has more thorough checks
1200 * than the regular read test.
1202 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1203 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1204 uint32_t all_groups, uint32_t all_ranks)
1207 uint32_t correct_mask_vg;
1208 uint32_t tmp_bit_chk;
1209 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1210 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1212 uint32_t base_rw_mgr;
1214 *bit_chk = param->read_correct_mask;
1215 correct_mask_vg = param->read_correct_mask_vg;
1217 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1218 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1220 for (r = rank_bgn; r < rank_end; r++) {
1221 if (param->skip_ranks[r])
1222 /* request to skip the rank */
1226 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1228 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1230 writel(RW_MGR_READ_B2B_WAIT1,
1231 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1233 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1234 writel(RW_MGR_READ_B2B_WAIT2,
1235 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1237 if (quick_read_mode)
1238 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1239 /* need at least two (1+1) reads to capture failures */
1240 else if (all_groups)
1241 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1243 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1245 writel(RW_MGR_READ_B2B,
1246 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1248 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1249 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1250 &sdr_rw_load_mgr_regs->load_cntr3);
1252 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1254 writel(RW_MGR_READ_B2B,
1255 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1258 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1259 /* reset the fifos to get pointers to known state */
1260 writel(0, &phy_mgr_cmd->fifo_reset);
1261 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1262 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1264 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1265 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1268 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1270 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1272 writel(RW_MGR_READ_B2B, addr +
1273 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1276 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1277 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1282 *bit_chk &= tmp_bit_chk;
1285 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1286 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1289 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1290 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1291 (%u == %u) => %lu", __func__, __LINE__, group,
1292 all_groups, *bit_chk, param->read_correct_mask,
1293 (long unsigned int)(*bit_chk ==
1294 param->read_correct_mask));
1295 return *bit_chk == param->read_correct_mask;
1297 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1298 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1299 (%u != %lu) => %lu\n", __func__, __LINE__,
1300 group, all_groups, *bit_chk, (long unsigned int)0,
1301 (long unsigned int)(*bit_chk != 0x00));
1302 return *bit_chk != 0x00;
1306 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1307 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1308 uint32_t all_groups)
1310 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1311 bit_chk, all_groups, 1);
1314 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1316 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1320 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1324 for (i = 0; i < VFIFO_SIZE-1; i++)
1325 rw_mgr_incr_vfifo(grp, v);
1328 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1331 uint32_t fail_cnt = 0;
1332 uint32_t test_status;
1334 for (v = 0; v < VFIFO_SIZE; ) {
1335 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1336 __func__, __LINE__, v);
1337 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1338 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1346 /* fiddle with FIFO */
1347 rw_mgr_incr_vfifo(grp, &v);
1350 if (v >= VFIFO_SIZE) {
1351 /* no failing read found!! Something must have gone wrong */
1352 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1353 __func__, __LINE__);
1360 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1361 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1362 uint32_t *v, uint32_t *d, uint32_t *p,
1363 uint32_t *i, uint32_t *max_working_cnt)
1365 uint32_t found_begin = 0;
1366 uint32_t tmp_delay = 0;
1367 uint32_t test_status;
1369 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1370 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1371 *work_bgn = tmp_delay;
1372 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1374 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1375 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1376 IO_DELAY_PER_OPA_TAP) {
1377 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1380 rw_mgr_mem_calibrate_read_test_all_ranks
1381 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1384 *max_working_cnt = 1;
1393 if (*p > IO_DQS_EN_PHASE_MAX)
1394 /* fiddle with FIFO */
1395 rw_mgr_incr_vfifo(*grp, v);
1402 if (*i >= VFIFO_SIZE) {
1403 /* cannot find working solution */
1404 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1405 ptap/dtap\n", __func__, __LINE__);
1412 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1413 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1414 uint32_t *p, uint32_t *max_working_cnt)
1416 uint32_t found_begin = 0;
1419 /* Special case code for backing up a phase */
1421 *p = IO_DQS_EN_PHASE_MAX;
1422 rw_mgr_decr_vfifo(*grp, v);
1426 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1427 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1429 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1430 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1431 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1433 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1437 *work_bgn = tmp_delay;
1442 /* We have found a working dtap before the ptap found above */
1443 if (found_begin == 1)
1444 (*max_working_cnt)++;
1447 * Restore VFIFO to old state before we decremented it
1451 if (*p > IO_DQS_EN_PHASE_MAX) {
1453 rw_mgr_incr_vfifo(*grp, v);
1456 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1459 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1460 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1461 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1464 uint32_t found_end = 0;
1467 *work_end += IO_DELAY_PER_OPA_TAP;
1468 if (*p > IO_DQS_EN_PHASE_MAX) {
1469 /* fiddle with FIFO */
1471 rw_mgr_incr_vfifo(*grp, v);
1474 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1475 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1476 += IO_DELAY_PER_OPA_TAP) {
1477 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1479 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1480 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1484 (*max_working_cnt)++;
1491 if (*p > IO_DQS_EN_PHASE_MAX) {
1492 /* fiddle with FIFO */
1493 rw_mgr_incr_vfifo(*grp, v);
1498 if (*i >= VFIFO_SIZE + 1) {
1499 /* cannot see edge of failing read */
1500 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1501 failed\n", __func__, __LINE__);
1508 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1509 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1510 uint32_t *p, uint32_t *work_mid,
1516 *work_mid = (*work_bgn + *work_end) / 2;
1518 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1519 *work_bgn, *work_end, *work_mid);
1520 /* Get the middle delay to be less than a VFIFO delay */
1521 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1522 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1524 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1525 while (*work_mid > tmp_delay)
1526 *work_mid -= tmp_delay;
1527 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1530 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1531 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1533 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1534 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1535 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1536 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1538 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1540 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1541 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1544 * push vfifo until we can successfully calibrate. We can do this
1545 * because the largest possible margin in 1 VFIFO cycle.
1547 for (i = 0; i < VFIFO_SIZE; i++) {
1548 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1550 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1556 /* fiddle with FIFO */
1557 rw_mgr_incr_vfifo(*grp, v);
1560 if (i >= VFIFO_SIZE) {
1561 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1562 failed\n", __func__, __LINE__);
1569 /* find a good dqs enable to use */
1570 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1572 uint32_t v, d, p, i;
1573 uint32_t max_working_cnt;
1575 uint32_t dtaps_per_ptap;
1576 uint32_t work_bgn, work_mid, work_end;
1577 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1579 debug("%s:%d %u\n", __func__, __LINE__, grp);
1581 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1583 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1584 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1586 /* ************************************************************** */
1587 /* * Step 0 : Determine number of delay taps for each phase tap * */
1588 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1590 /* ********************************************************* */
1591 /* * Step 1 : First push vfifo until we get a failing read * */
1592 v = find_vfifo_read(grp, &bit_chk);
1594 max_working_cnt = 0;
1596 /* ******************************************************** */
1597 /* * step 2: find first working phase, increment in ptaps * */
1599 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1600 &p, &i, &max_working_cnt) == 0)
1603 work_end = work_bgn;
1606 * If d is 0 then the working window covers a phase tap and
1607 * we can follow the old procedure otherwise, we've found the beginning,
1608 * and we need to increment the dtaps until we find the end.
1611 /* ********************************************************* */
1612 /* * step 3a: if we have room, back off by one and
1613 increment in dtaps * */
1615 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1618 /* ********************************************************* */
1619 /* * step 4a: go forward from working phase to non working
1620 phase, increment in ptaps * */
1621 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1622 &i, &max_working_cnt, &work_end) == 0)
1625 /* ********************************************************* */
1626 /* * step 5a: back off one from last, increment in dtaps * */
1628 /* Special case code for backing up a phase */
1630 p = IO_DQS_EN_PHASE_MAX;
1631 rw_mgr_decr_vfifo(grp, &v);
1636 work_end -= IO_DELAY_PER_OPA_TAP;
1637 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1639 /* * The actual increment of dtaps is done outside of
1640 the if/else loop to share code */
1643 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1644 vfifo=%u ptap=%u\n", __func__, __LINE__,
1647 /* ******************************************************* */
1648 /* * step 3-5b: Find the right edge of the window using
1650 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1651 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1654 work_end = work_bgn;
1656 /* * The actual increment of dtaps is done outside of the
1657 if/else loop to share code */
1659 /* Only here to counterbalance a subtract later on which is
1660 not needed if this branch of the algorithm is taken */
1664 /* The dtap increment to find the failing edge is done here */
1665 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1666 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1667 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1668 end-2: dtap=%u\n", __func__, __LINE__, d);
1669 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1671 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1678 /* Go back to working dtap */
1680 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1682 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1683 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1684 v, p, d-1, work_end);
1686 if (work_end < work_bgn) {
1688 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1689 failed\n", __func__, __LINE__);
1693 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1694 __func__, __LINE__, work_bgn, work_end);
1696 /* *************************************************************** */
1698 * * We need to calculate the number of dtaps that equal a ptap
1699 * * To do that we'll back up a ptap and re-find the edge of the
1700 * * window using dtaps
1703 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1704 for tracking\n", __func__, __LINE__);
1706 /* Special case code for backing up a phase */
1708 p = IO_DQS_EN_PHASE_MAX;
1709 rw_mgr_decr_vfifo(grp, &v);
1710 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1711 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1715 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1716 phase only: v=%u p=%u", __func__, __LINE__,
1720 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1723 * Increase dtap until we first see a passing read (in case the
1724 * window is smaller than a ptap),
1725 * and then a failing read to mark the edge of the window again
1728 /* Find a passing read */
1729 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1730 __func__, __LINE__);
1731 found_passing_read = 0;
1732 found_failing_read = 0;
1733 initial_failing_dtap = d;
1734 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1735 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1736 read d=%u\n", __func__, __LINE__, d);
1737 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1739 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1742 found_passing_read = 1;
1747 if (found_passing_read) {
1748 /* Find a failing read */
1749 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1750 read\n", __func__, __LINE__);
1751 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1752 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1753 testing read d=%u\n", __func__, __LINE__, d);
1754 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1756 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1757 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1758 found_failing_read = 1;
1763 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1764 calculate dtaps", __func__, __LINE__);
1765 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1769 * The dynamically calculated dtaps_per_ptap is only valid if we
1770 * found a passing/failing read. If we didn't, it means d hit the max
1771 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1772 * statically calculated value.
1774 if (found_passing_read && found_failing_read)
1775 dtaps_per_ptap = d - initial_failing_dtap;
1777 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1778 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1779 - %u = %u", __func__, __LINE__, d,
1780 initial_failing_dtap, dtaps_per_ptap);
1782 /* ******************************************** */
1783 /* * step 6: Find the centre of the window * */
1784 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1785 &work_mid, &work_end) == 0)
1788 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1789 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1795 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1796 * dq_in_delay values
1799 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1800 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1808 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1809 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1810 /* we start at zero, so have one less dq to devide among */
1812 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1815 /* try different dq_in_delays since the dq path is shorter than dqs */
1817 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1818 r += NUM_RANKS_PER_SHADOW_REG) {
1819 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1820 i++, p++, d += delay_step) {
1821 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1822 vfifo_find_dqs_", __func__, __LINE__);
1823 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1824 write_group, read_group);
1825 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1826 scc_mgr_set_dq_in_delay(write_group, p, d);
1829 writel(0, &sdr_scc_mgr->update);
1832 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1834 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1835 en_phase_sweep_dq", __func__, __LINE__);
1836 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1837 chain to zero\n", write_group, read_group, found);
1839 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1840 r += NUM_RANKS_PER_SHADOW_REG) {
1841 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1843 scc_mgr_set_dq_in_delay(write_group, p, 0);
1846 writel(0, &sdr_scc_mgr->update);
1852 /* per-bit deskew DQ and center */
1853 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1854 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1855 uint32_t use_read_test, uint32_t update_fom)
1857 uint32_t i, p, d, min_index;
1859 * Store these as signed since there are comparisons with
1863 uint32_t sticky_bit_chk;
1864 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1865 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1866 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1868 int32_t orig_mid_min, mid_min;
1869 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1871 int32_t dq_margin, dqs_margin;
1873 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1876 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1878 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1879 start_dqs = readl(addr + (read_group << 2));
1880 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1881 start_dqs_en = readl(addr + ((read_group << 2)
1882 - IO_DQS_EN_DELAY_OFFSET));
1884 /* set the left and right edge of each bit to an illegal value */
1885 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1887 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1888 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1889 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1892 /* Search for the left edge of the window for each bit */
1893 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1894 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1896 writel(0, &sdr_scc_mgr->update);
1899 * Stop searching when the read test doesn't pass AND when
1900 * we've seen a passing read on every bit.
1902 if (use_read_test) {
1903 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1904 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1907 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1910 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1911 (read_group - (write_group *
1912 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1913 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1914 stop = (bit_chk == 0);
1916 sticky_bit_chk = sticky_bit_chk | bit_chk;
1917 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1918 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1919 && %u", __func__, __LINE__, d,
1921 param->read_correct_mask, stop);
1926 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1928 /* Remember a passing test as the
1932 /* If a left edge has not been seen yet,
1933 then a future passing test will mark
1934 this edge as the right edge */
1936 IO_IO_IN_DELAY_MAX + 1) {
1937 right_edge[i] = -(d + 1);
1940 bit_chk = bit_chk >> 1;
1945 /* Reset DQ delay chains to 0 */
1946 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, 0);
1948 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1949 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1950 %d right_edge[%u]: %d\n", __func__, __LINE__,
1951 i, left_edge[i], i, right_edge[i]);
1954 * Check for cases where we haven't found the left edge,
1955 * which makes our assignment of the the right edge invalid.
1956 * Reset it to the illegal value.
1958 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1959 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1960 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1961 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1962 right_edge[%u]: %d\n", __func__, __LINE__,
1967 * Reset sticky bit (except for bits where we have seen
1968 * both the left and right edge).
1970 sticky_bit_chk = sticky_bit_chk << 1;
1971 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1972 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1973 sticky_bit_chk = sticky_bit_chk | 1;
1980 /* Search for the right edge of the window for each bit */
1981 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1982 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1983 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1984 uint32_t delay = d + start_dqs_en;
1985 if (delay > IO_DQS_EN_DELAY_MAX)
1986 delay = IO_DQS_EN_DELAY_MAX;
1987 scc_mgr_set_dqs_en_delay(read_group, delay);
1989 scc_mgr_load_dqs(read_group);
1991 writel(0, &sdr_scc_mgr->update);
1994 * Stop searching when the read test doesn't pass AND when
1995 * we've seen a passing read on every bit.
1997 if (use_read_test) {
1998 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1999 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
2002 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2005 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
2006 (read_group - (write_group *
2007 RW_MGR_MEM_IF_READ_DQS_WIDTH /
2008 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
2009 stop = (bit_chk == 0);
2011 sticky_bit_chk = sticky_bit_chk | bit_chk;
2012 stop = stop && (sticky_bit_chk == param->read_correct_mask);
2014 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
2015 %u && %u", __func__, __LINE__, d,
2016 sticky_bit_chk, param->read_correct_mask, stop);
2021 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2023 /* Remember a passing test as
2028 /* If a right edge has not been
2029 seen yet, then a future passing
2030 test will mark this edge as the
2032 if (right_edge[i] ==
2033 IO_IO_IN_DELAY_MAX + 1) {
2034 left_edge[i] = -(d + 1);
2037 /* d = 0 failed, but it passed
2038 when testing the left edge,
2039 so it must be marginal,
2041 if (right_edge[i] ==
2042 IO_IO_IN_DELAY_MAX + 1 &&
2048 /* If a right edge has not been
2049 seen yet, then a future passing
2050 test will mark this edge as the
2052 else if (right_edge[i] ==
2053 IO_IO_IN_DELAY_MAX +
2055 left_edge[i] = -(d + 1);
2060 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2061 d=%u]: ", __func__, __LINE__, d);
2062 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2063 (int)(bit_chk & 1), i, left_edge[i]);
2064 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2066 bit_chk = bit_chk >> 1;
2071 /* Check that all bits have a window */
2072 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2073 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2074 %d right_edge[%u]: %d", __func__, __LINE__,
2075 i, left_edge[i], i, right_edge[i]);
2076 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2077 == IO_IO_IN_DELAY_MAX + 1)) {
2079 * Restore delay chain settings before letting the loop
2080 * in rw_mgr_mem_calibrate_vfifo to retry different
2081 * dqs/ck relationships.
2083 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2084 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2085 scc_mgr_set_dqs_en_delay(read_group,
2088 scc_mgr_load_dqs(read_group);
2089 writel(0, &sdr_scc_mgr->update);
2091 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2092 find edge [%u]: %d %d", __func__, __LINE__,
2093 i, left_edge[i], right_edge[i]);
2094 if (use_read_test) {
2095 set_failing_group_stage(read_group *
2096 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2098 CAL_SUBSTAGE_VFIFO_CENTER);
2100 set_failing_group_stage(read_group *
2101 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2102 CAL_STAGE_VFIFO_AFTER_WRITES,
2103 CAL_SUBSTAGE_VFIFO_CENTER);
2109 /* Find middle of window for each DQ bit */
2110 mid_min = left_edge[0] - right_edge[0];
2112 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2113 mid = left_edge[i] - right_edge[i];
2114 if (mid < mid_min) {
2121 * -mid_min/2 represents the amount that we need to move DQS.
2122 * If mid_min is odd and positive we'll need to add one to
2123 * make sure the rounding in further calculations is correct
2124 * (always bias to the right), so just add 1 for all positive values.
2129 mid_min = mid_min / 2;
2131 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2132 __func__, __LINE__, mid_min, min_index);
2134 /* Determine the amount we can change DQS (which is -mid_min) */
2135 orig_mid_min = mid_min;
2136 new_dqs = start_dqs - mid_min;
2137 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2138 new_dqs = IO_DQS_IN_DELAY_MAX;
2139 else if (new_dqs < 0)
2142 mid_min = start_dqs - new_dqs;
2143 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2146 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2147 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2148 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2149 else if (start_dqs_en - mid_min < 0)
2150 mid_min += start_dqs_en - mid_min;
2152 new_dqs = start_dqs - mid_min;
2154 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2155 new_dqs=%d mid_min=%d\n", start_dqs,
2156 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2159 /* Initialize data for export structures */
2160 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2161 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2163 /* add delay to bring centre of all DQ windows to the same "level" */
2164 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2165 /* Use values before divide by 2 to reduce round off error */
2166 shift_dq = (left_edge[i] - right_edge[i] -
2167 (left_edge[min_index] - right_edge[min_index]))/2 +
2168 (orig_mid_min - mid_min);
2170 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2171 shift_dq[%u]=%d\n", i, shift_dq);
2173 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2174 temp_dq_in_delay1 = readl(addr + (p << 2));
2175 temp_dq_in_delay2 = readl(addr + (i << 2));
2177 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2178 (int32_t)IO_IO_IN_DELAY_MAX) {
2179 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2180 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2181 shift_dq = -(int32_t)temp_dq_in_delay1;
2183 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2184 shift_dq[%u]=%d\n", i, shift_dq);
2185 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2186 scc_mgr_set_dq_in_delay(write_group, p, final_dq[i]);
2189 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2190 left_edge[i] - shift_dq + (-mid_min),
2191 right_edge[i] + shift_dq - (-mid_min));
2192 /* To determine values for export structures */
2193 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2194 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2196 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2197 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2200 final_dqs = new_dqs;
2201 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2202 final_dqs_en = start_dqs_en - mid_min;
2205 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2206 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2207 scc_mgr_load_dqs(read_group);
2211 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2212 scc_mgr_load_dqs(read_group);
2213 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2214 dqs_margin=%d", __func__, __LINE__,
2215 dq_margin, dqs_margin);
2218 * Do not remove this line as it makes sure all of our decisions
2219 * have been applied. Apply the update bit.
2221 writel(0, &sdr_scc_mgr->update);
2223 return (dq_margin >= 0) && (dqs_margin >= 0);
2227 * calibrate the read valid prediction FIFO.
2229 * - read valid prediction will consist of finding a good DQS enable phase,
2230 * DQS enable delay, DQS input phase, and DQS input delay.
2231 * - we also do a per-bit deskew on the DQ lines.
2233 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2236 uint32_t p, d, rank_bgn, sr;
2237 uint32_t dtaps_per_ptap;
2240 uint32_t grp_calibrated;
2241 uint32_t write_group, write_test_bgn;
2242 uint32_t failed_substage;
2244 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2246 /* update info for sims */
2247 reg_file_set_stage(CAL_STAGE_VFIFO);
2249 write_group = read_group;
2250 write_test_bgn = test_bgn;
2252 /* USER Determine number of delay taps for each phase tap */
2255 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2257 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2262 /* update info for sims */
2263 reg_file_set_group(read_group);
2267 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2268 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2270 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2272 * In RLDRAMX we may be messing the delay of pins in
2273 * the same write group but outside of the current read
2274 * the group, but that's ok because we haven't
2275 * calibrated output side yet.
2278 scc_mgr_apply_group_all_out_delay_add_all_ranks
2279 (write_group, write_test_bgn, d);
2282 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2284 /* set a particular dqdqs phase */
2285 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2287 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2288 p=%u d=%u\n", __func__, __LINE__,
2292 * Load up the patterns used by read calibration
2293 * using current DQDQS phase.
2295 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2296 if (!(gbl->phy_debug_mode_flags &
2297 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2298 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2299 (read_group, 1, &bit_chk)) {
2300 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2301 __func__, __LINE__);
2302 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2310 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2311 (write_group, read_group, test_bgn)) {
2313 * USER Read per-bit deskew can be done on a
2314 * per shadow register basis.
2316 for (rank_bgn = 0, sr = 0;
2317 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2318 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2321 * Determine if this set of ranks
2322 * should be skipped entirely.
2324 if (!param->skip_shadow_regs[sr]) {
2326 * If doing read after write
2327 * calibration, do not update
2328 * FOM, now - do it then.
2330 if (!rw_mgr_mem_calibrate_vfifo_center
2331 (rank_bgn, write_group,
2332 read_group, test_bgn, 1, 0)) {
2335 CAL_SUBSTAGE_VFIFO_CENTER;
2341 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2346 if (grp_calibrated == 0) {
2347 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2353 * Reset the delay chains back to zero if they have moved > 1
2354 * (check for > 1 because loop will increase d even when pass in
2358 scc_mgr_zero_group(write_group, write_test_bgn, 1);
2363 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2364 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2367 uint32_t rank_bgn, sr;
2368 uint32_t grp_calibrated;
2369 uint32_t write_group;
2371 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2373 /* update info for sims */
2375 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2376 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2378 write_group = read_group;
2380 /* update info for sims */
2381 reg_file_set_group(read_group);
2384 /* Read per-bit deskew can be done on a per shadow register basis */
2385 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2386 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2387 /* Determine if this set of ranks should be skipped entirely */
2388 if (!param->skip_shadow_regs[sr]) {
2389 /* This is the last calibration round, update FOM here */
2390 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2401 if (grp_calibrated == 0) {
2402 set_failing_group_stage(write_group,
2403 CAL_STAGE_VFIFO_AFTER_WRITES,
2404 CAL_SUBSTAGE_VFIFO_CENTER);
2411 /* Calibrate LFIFO to find smallest read latency */
2412 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2417 debug("%s:%d\n", __func__, __LINE__);
2419 /* update info for sims */
2420 reg_file_set_stage(CAL_STAGE_LFIFO);
2421 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2423 /* Load up the patterns used by read calibration for all ranks */
2424 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2428 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2429 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2430 __func__, __LINE__, gbl->curr_read_lat);
2432 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2440 /* reduce read latency and see if things are working */
2442 gbl->curr_read_lat--;
2443 } while (gbl->curr_read_lat > 0);
2445 /* reset the fifos to get pointers to known state */
2447 writel(0, &phy_mgr_cmd->fifo_reset);
2450 /* add a fudge factor to the read latency that was determined */
2451 gbl->curr_read_lat += 2;
2452 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2453 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2454 read_lat=%u\n", __func__, __LINE__,
2455 gbl->curr_read_lat);
2458 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2459 CAL_SUBSTAGE_READ_LATENCY);
2461 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2462 read_lat=%u\n", __func__, __LINE__,
2463 gbl->curr_read_lat);
2469 * issue write test command.
2470 * two variants are provided. one that just tests a write pattern and
2471 * another that tests datamask functionality.
2473 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2476 uint32_t mcc_instruction;
2477 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2478 ENABLE_SUPER_QUICK_CALIBRATION);
2479 uint32_t rw_wl_nop_cycles;
2483 * Set counter and jump addresses for the right
2484 * number of NOP cycles.
2485 * The number of supported NOP cycles can range from -1 to infinity
2486 * Three different cases are handled:
2488 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2489 * mechanism will be used to insert the right number of NOPs
2491 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2492 * issuing the write command will jump straight to the
2493 * micro-instruction that turns on DQS (for DDRx), or outputs write
2494 * data (for RLD), skipping
2495 * the NOP micro-instruction all together
2497 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2498 * turned on in the same micro-instruction that issues the write
2499 * command. Then we need
2500 * to directly jump to the micro-instruction that sends out the data
2502 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2503 * (2 and 3). One jump-counter (0) is used to perform multiple
2504 * write-read operations.
2505 * one counter left to issue this command in "multiple-group" mode
2508 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2510 if (rw_wl_nop_cycles == -1) {
2512 * CNTR 2 - We want to execute the special write operation that
2513 * turns on DQS right away and then skip directly to the
2514 * instruction that sends out the data. We set the counter to a
2515 * large number so that the jump is always taken.
2517 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2519 /* CNTR 3 - Not used */
2521 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2522 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2523 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2524 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2525 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2527 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2528 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2529 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2530 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2531 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2533 } else if (rw_wl_nop_cycles == 0) {
2535 * CNTR 2 - We want to skip the NOP operation and go straight
2536 * to the DQS enable instruction. We set the counter to a large
2537 * number so that the jump is always taken.
2539 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2541 /* CNTR 3 - Not used */
2543 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2544 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2545 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2547 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2548 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2549 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2553 * CNTR 2 - In this case we want to execute the next instruction
2554 * and NOT take the jump. So we set the counter to 0. The jump
2555 * address doesn't count.
2557 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2558 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2561 * CNTR 3 - Set the nop counter to the number of cycles we
2562 * need to loop for, minus 1.
2564 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2566 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2567 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2568 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2570 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2571 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2572 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2576 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2577 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2579 if (quick_write_mode)
2580 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2582 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2584 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2587 * CNTR 1 - This is used to ensure enough time elapses
2588 * for read data to come back.
2590 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2593 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2594 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2596 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2597 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2600 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2601 writel(mcc_instruction, addr + (group << 2));
2604 /* Test writes, can check for a single bit pass or multiple bit pass */
2605 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2606 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2607 uint32_t *bit_chk, uint32_t all_ranks)
2610 uint32_t correct_mask_vg;
2611 uint32_t tmp_bit_chk;
2613 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2614 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2615 uint32_t addr_rw_mgr;
2616 uint32_t base_rw_mgr;
2618 *bit_chk = param->write_correct_mask;
2619 correct_mask_vg = param->write_correct_mask_vg;
2621 for (r = rank_bgn; r < rank_end; r++) {
2622 if (param->skip_ranks[r]) {
2623 /* request to skip the rank */
2628 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2631 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2632 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2633 /* reset the fifos to get pointers to known state */
2634 writel(0, &phy_mgr_cmd->fifo_reset);
2636 tmp_bit_chk = tmp_bit_chk <<
2637 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2638 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2639 rw_mgr_mem_calibrate_write_test_issue(write_group *
2640 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2643 base_rw_mgr = readl(addr_rw_mgr);
2644 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2648 *bit_chk &= tmp_bit_chk;
2652 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2653 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2654 %u => %lu", write_group, use_dm,
2655 *bit_chk, param->write_correct_mask,
2656 (long unsigned int)(*bit_chk ==
2657 param->write_correct_mask));
2658 return *bit_chk == param->write_correct_mask;
2660 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2661 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2662 write_group, use_dm, *bit_chk);
2663 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2664 (long unsigned int)(*bit_chk != 0));
2665 return *bit_chk != 0x00;
2670 * center all windows. do per-bit-deskew to possibly increase size of
2673 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2674 uint32_t write_group, uint32_t test_bgn)
2676 uint32_t i, p, min_index;
2679 * Store these as signed since there are comparisons with
2683 uint32_t sticky_bit_chk;
2684 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2685 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2687 int32_t mid_min, orig_mid_min;
2688 int32_t new_dqs, start_dqs, shift_dq;
2689 int32_t dq_margin, dqs_margin, dm_margin;
2691 uint32_t temp_dq_out1_delay;
2694 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2698 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2699 start_dqs = readl(addr +
2700 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2702 /* per-bit deskew */
2705 * set the left and right edge of each bit to an illegal value
2706 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2709 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2710 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2711 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2714 /* Search for the left edge of the window for each bit */
2715 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2716 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, d);
2718 writel(0, &sdr_scc_mgr->update);
2721 * Stop searching when the read test doesn't pass AND when
2722 * we've seen a passing read on every bit.
2724 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2725 0, PASS_ONE_BIT, &bit_chk, 0);
2726 sticky_bit_chk = sticky_bit_chk | bit_chk;
2727 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2728 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2729 == %u && %u [bit_chk= %u ]\n",
2730 d, sticky_bit_chk, param->write_correct_mask,
2736 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2739 * Remember a passing test as the
2745 * If a left edge has not been seen
2746 * yet, then a future passing test will
2747 * mark this edge as the right edge.
2750 IO_IO_OUT1_DELAY_MAX + 1) {
2751 right_edge[i] = -(d + 1);
2754 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2755 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2756 (int)(bit_chk & 1), i, left_edge[i]);
2757 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2759 bit_chk = bit_chk >> 1;
2764 /* Reset DQ delay chains to 0 */
2765 scc_mgr_apply_group_dq_out1_delay(write_group, test_bgn, 0);
2767 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2768 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2769 %d right_edge[%u]: %d\n", __func__, __LINE__,
2770 i, left_edge[i], i, right_edge[i]);
2773 * Check for cases where we haven't found the left edge,
2774 * which makes our assignment of the the right edge invalid.
2775 * Reset it to the illegal value.
2777 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2778 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2779 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2780 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2781 right_edge[%u]: %d\n", __func__, __LINE__,
2786 * Reset sticky bit (except for bits where we have
2787 * seen the left edge).
2789 sticky_bit_chk = sticky_bit_chk << 1;
2790 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2791 sticky_bit_chk = sticky_bit_chk | 1;
2797 /* Search for the right edge of the window for each bit */
2798 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2799 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2802 writel(0, &sdr_scc_mgr->update);
2805 * Stop searching when the read test doesn't pass AND when
2806 * we've seen a passing read on every bit.
2808 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2809 0, PASS_ONE_BIT, &bit_chk, 0);
2811 sticky_bit_chk = sticky_bit_chk | bit_chk;
2812 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2814 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2815 %u && %u\n", d, sticky_bit_chk,
2816 param->write_correct_mask, stop);
2820 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2822 /* d = 0 failed, but it passed when
2823 testing the left edge, so it must be
2824 marginal, set it to -1 */
2825 if (right_edge[i] ==
2826 IO_IO_OUT1_DELAY_MAX + 1 &&
2828 IO_IO_OUT1_DELAY_MAX + 1) {
2835 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2838 * Remember a passing test as
2845 * If a right edge has not
2846 * been seen yet, then a future
2847 * passing test will mark this
2848 * edge as the left edge.
2850 if (right_edge[i] ==
2851 IO_IO_OUT1_DELAY_MAX + 1)
2852 left_edge[i] = -(d + 1);
2855 * d = 0 failed, but it passed
2856 * when testing the left edge,
2857 * so it must be marginal, set
2860 if (right_edge[i] ==
2861 IO_IO_OUT1_DELAY_MAX + 1 &&
2863 IO_IO_OUT1_DELAY_MAX + 1)
2866 * If a right edge has not been
2867 * seen yet, then a future
2868 * passing test will mark this
2869 * edge as the left edge.
2871 else if (right_edge[i] ==
2872 IO_IO_OUT1_DELAY_MAX +
2874 left_edge[i] = -(d + 1);
2877 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2878 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2879 (int)(bit_chk & 1), i, left_edge[i]);
2880 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2882 bit_chk = bit_chk >> 1;
2887 /* Check that all bits have a window */
2888 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2889 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2890 %d right_edge[%u]: %d", __func__, __LINE__,
2891 i, left_edge[i], i, right_edge[i]);
2892 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2893 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2894 set_failing_group_stage(test_bgn + i,
2896 CAL_SUBSTAGE_WRITES_CENTER);
2901 /* Find middle of window for each DQ bit */
2902 mid_min = left_edge[0] - right_edge[0];
2904 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2905 mid = left_edge[i] - right_edge[i];
2906 if (mid < mid_min) {
2913 * -mid_min/2 represents the amount that we need to move DQS.
2914 * If mid_min is odd and positive we'll need to add one to
2915 * make sure the rounding in further calculations is correct
2916 * (always bias to the right), so just add 1 for all positive values.
2920 mid_min = mid_min / 2;
2921 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2924 /* Determine the amount we can change DQS (which is -mid_min) */
2925 orig_mid_min = mid_min;
2926 new_dqs = start_dqs;
2928 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2929 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2930 /* Initialize data for export structures */
2931 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2932 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2934 /* add delay to bring centre of all DQ windows to the same "level" */
2935 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2936 /* Use values before divide by 2 to reduce round off error */
2937 shift_dq = (left_edge[i] - right_edge[i] -
2938 (left_edge[min_index] - right_edge[min_index]))/2 +
2939 (orig_mid_min - mid_min);
2941 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2942 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2944 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2945 temp_dq_out1_delay = readl(addr + (i << 2));
2946 if (shift_dq + (int32_t)temp_dq_out1_delay >
2947 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2948 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2949 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2950 shift_dq = -(int32_t)temp_dq_out1_delay;
2952 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2954 scc_mgr_set_dq_out1_delay(write_group, i, temp_dq_out1_delay +
2958 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2959 left_edge[i] - shift_dq + (-mid_min),
2960 right_edge[i] + shift_dq - (-mid_min));
2961 /* To determine values for export structures */
2962 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2963 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2965 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2966 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2970 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2971 writel(0, &sdr_scc_mgr->update);
2974 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2977 * set the left and right edge of each bit to an illegal value,
2978 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2980 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2981 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2982 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2983 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2984 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2985 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2986 int32_t win_best = 0;
2988 /* Search for the/part of the window with DM shift */
2989 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2990 scc_mgr_apply_group_dm_out1_delay(write_group, d);
2991 writel(0, &sdr_scc_mgr->update);
2993 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2994 PASS_ALL_BITS, &bit_chk,
2996 /* USE Set current end of the window */
2999 * If a starting edge of our window has not been seen
3000 * this is our current start of the DM window.
3002 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3006 * If current window is bigger than best seen.
3007 * Set best seen to be current window.
3009 if ((end_curr-bgn_curr+1) > win_best) {
3010 win_best = end_curr-bgn_curr+1;
3011 bgn_best = bgn_curr;
3012 end_best = end_curr;
3015 /* We just saw a failing test. Reset temp edge */
3016 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3017 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3022 /* Reset DM delay chains to 0 */
3023 scc_mgr_apply_group_dm_out1_delay(write_group, 0);
3026 * Check to see if the current window nudges up aganist 0 delay.
3027 * If so we need to continue the search by shifting DQS otherwise DQS
3028 * search begins as a new search. */
3029 if (end_curr != 0) {
3030 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3031 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3034 /* Search for the/part of the window with DQS shifts */
3035 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3037 * Note: This only shifts DQS, so are we limiting ourselve to
3038 * width of DQ unnecessarily.
3040 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3043 writel(0, &sdr_scc_mgr->update);
3044 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3045 PASS_ALL_BITS, &bit_chk,
3047 /* USE Set current end of the window */
3050 * If a beginning edge of our window has not been seen
3051 * this is our current begin of the DM window.
3053 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3057 * If current window is bigger than best seen. Set best
3058 * seen to be current window.
3060 if ((end_curr-bgn_curr+1) > win_best) {
3061 win_best = end_curr-bgn_curr+1;
3062 bgn_best = bgn_curr;
3063 end_best = end_curr;
3066 /* We just saw a failing test. Reset temp edge */
3067 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3068 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3070 /* Early exit optimization: if ther remaining delay
3071 chain space is less than already seen largest window
3074 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3080 /* assign left and right edge for cal and reporting; */
3081 left_edge[0] = -1*bgn_best;
3082 right_edge[0] = end_best;
3084 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3085 __LINE__, left_edge[0], right_edge[0]);
3087 /* Move DQS (back to orig) */
3088 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3092 /* Find middle of window for the DM bit */
3093 mid = (left_edge[0] - right_edge[0]) / 2;
3095 /* only move right, since we are not moving DQS/DQ */
3099 /* dm_marign should fail if we never find a window */
3103 dm_margin = left_edge[0] - mid;
3105 scc_mgr_apply_group_dm_out1_delay(write_group, mid);
3106 writel(0, &sdr_scc_mgr->update);
3108 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3109 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3110 right_edge[0], mid, dm_margin);
3112 gbl->fom_out += dq_margin + dqs_margin;
3114 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3115 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3116 dq_margin, dqs_margin, dm_margin);
3119 * Do not remove this line as it makes sure all of our
3120 * decisions have been applied.
3122 writel(0, &sdr_scc_mgr->update);
3123 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3126 /* calibrate the write operations */
3127 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3130 /* update info for sims */
3131 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3133 reg_file_set_stage(CAL_STAGE_WRITES);
3134 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3136 reg_file_set_group(g);
3138 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3139 set_failing_group_stage(g, CAL_STAGE_WRITES,
3140 CAL_SUBSTAGE_WRITES_CENTER);
3147 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3148 static void mem_precharge_and_activate(void)
3152 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3153 if (param->skip_ranks[r]) {
3154 /* request to skip the rank */
3159 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3161 /* precharge all banks ... */
3162 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3163 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3165 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3166 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3167 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3169 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3170 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3171 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3174 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3175 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3179 /* Configure various memory related parameters. */
3180 static void mem_config(void)
3182 uint32_t rlat, wlat;
3183 uint32_t rw_wl_nop_cycles;
3184 uint32_t max_latency;
3186 debug("%s:%d\n", __func__, __LINE__);
3187 /* read in write and read latency */
3188 wlat = readl(&data_mgr->t_wl_add);
3189 wlat += readl(&data_mgr->mem_t_add);
3191 /* WL for hard phy does not include additive latency */
3194 * add addtional write latency to offset the address/command extra
3195 * clock cycle. We change the AC mux setting causing AC to be delayed
3196 * by one mem clock cycle. Only do this for DDR3
3200 rlat = readl(&data_mgr->t_rl_add);
3202 rw_wl_nop_cycles = wlat - 2;
3203 gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3206 * For AV/CV, lfifo is hardened and always runs at full rate so
3207 * max latency in AFI clocks, used here, is correspondingly smaller.
3209 max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3210 /* configure for a burst length of 8 */
3213 /* Adjust Write Latency for Hard PHY */
3216 /* set a pretty high read latency initially */
3217 gbl->curr_read_lat = rlat + 16;
3219 if (gbl->curr_read_lat > max_latency)
3220 gbl->curr_read_lat = max_latency;
3222 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3224 /* advertise write latency */
3225 gbl->curr_write_lat = wlat;
3226 writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3228 /* initialize bit slips */
3229 mem_precharge_and_activate();
3232 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3233 static void mem_skip_calibrate(void)
3235 uint32_t vfifo_offset;
3238 debug("%s:%d\n", __func__, __LINE__);
3239 /* Need to update every shadow register set used by the interface */
3240 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3241 r += NUM_RANKS_PER_SHADOW_REG) {
3243 * Set output phase alignment settings appropriate for
3246 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3247 scc_mgr_set_dqs_en_phase(i, 0);
3248 #if IO_DLL_CHAIN_LENGTH == 6
3249 scc_mgr_set_dqdqs_output_phase(i, 6);
3251 scc_mgr_set_dqdqs_output_phase(i, 7);
3256 * Write data arrives to the I/O two cycles before write
3257 * latency is reached (720 deg).
3258 * -> due to bit-slip in a/c bus
3259 * -> to allow board skew where dqs is longer than ck
3260 * -> how often can this happen!?
3261 * -> can claim back some ptaps for high freq
3262 * support if we can relax this, but i digress...
3264 * The write_clk leads mem_ck by 90 deg
3265 * The minimum ptap of the OPA is 180 deg
3266 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3267 * The write_clk is always delayed by 2 ptaps
3269 * Hence, to make DQS aligned to CK, we need to delay
3271 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3273 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3274 * gives us the number of ptaps, which simplies to:
3276 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3278 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3279 IO_DLL_CHAIN_LENGTH - 2));
3281 writel(0xff, &sdr_scc_mgr->dqs_ena);
3282 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3284 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3285 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3286 SCC_MGR_GROUP_COUNTER_OFFSET);
3288 writel(0xff, &sdr_scc_mgr->dq_ena);
3289 writel(0xff, &sdr_scc_mgr->dm_ena);
3290 writel(0, &sdr_scc_mgr->update);
3293 /* Compensate for simulation model behaviour */
3294 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3295 scc_mgr_set_dqs_bus_in_delay(i, 10);
3296 scc_mgr_load_dqs(i);
3298 writel(0, &sdr_scc_mgr->update);
3301 * ArriaV has hard FIFOs that can only be initialized by incrementing
3304 vfifo_offset = CALIB_VFIFO_OFFSET;
3305 for (j = 0; j < vfifo_offset; j++) {
3306 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3308 writel(0, &phy_mgr_cmd->fifo_reset);
3311 * For ACV with hard lfifo, we get the skip-cal setting from
3312 * generation-time constant.
3314 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3315 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3318 /* Memory calibration entry point */
3319 static uint32_t mem_calibrate(void)
3322 uint32_t rank_bgn, sr;
3323 uint32_t write_group, write_test_bgn;
3324 uint32_t read_group, read_test_bgn;
3325 uint32_t run_groups, current_run;
3326 uint32_t failing_groups = 0;
3327 uint32_t group_failed = 0;
3328 uint32_t sr_failed = 0;
3330 debug("%s:%d\n", __func__, __LINE__);
3331 /* Initialize the data settings */
3333 gbl->error_substage = CAL_SUBSTAGE_NIL;
3334 gbl->error_stage = CAL_STAGE_NIL;
3335 gbl->error_group = 0xff;
3341 uint32_t bypass_mode = 0x1;
3342 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3343 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3344 SCC_MGR_GROUP_COUNTER_OFFSET);
3345 scc_set_bypass_mode(i, bypass_mode);
3348 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3350 * Set VFIFO and LFIFO to instant-on settings in skip
3353 mem_skip_calibrate();
3355 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3357 * Zero all delay chain/phase settings for all
3358 * groups and all shadow register sets.
3362 run_groups = ~param->skip_groups;
3364 for (write_group = 0, write_test_bgn = 0; write_group
3365 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3366 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3367 /* Initialized the group failure */
3370 current_run = run_groups & ((1 <<
3371 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3372 run_groups = run_groups >>
3373 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3375 if (current_run == 0)
3378 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3379 SCC_MGR_GROUP_COUNTER_OFFSET);
3380 scc_mgr_zero_group(write_group, write_test_bgn,
3383 for (read_group = write_group *
3384 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3385 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3387 read_group < (write_group + 1) *
3388 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3389 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3391 read_group++, read_test_bgn +=
3392 RW_MGR_MEM_DQ_PER_READ_DQS) {
3393 /* Calibrate the VFIFO */
3394 if (!((STATIC_CALIB_STEPS) &
3395 CALIB_SKIP_VFIFO)) {
3396 if (!rw_mgr_mem_calibrate_vfifo
3402 phy_debug_mode_flags &
3403 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3410 /* Calibrate the output side */
3411 if (group_failed == 0) {
3412 for (rank_bgn = 0, sr = 0; rank_bgn
3413 < RW_MGR_MEM_NUMBER_OF_RANKS;
3415 NUM_RANKS_PER_SHADOW_REG,
3418 if (!((STATIC_CALIB_STEPS) &
3419 CALIB_SKIP_WRITES)) {
3420 if ((STATIC_CALIB_STEPS)
3421 & CALIB_SKIP_DELAY_SWEEPS) {
3422 /* not needed in quick mode! */
3425 * Determine if this set of
3426 * ranks should be skipped
3429 if (!param->skip_shadow_regs[sr]) {
3430 if (!rw_mgr_mem_calibrate_writes
3431 (rank_bgn, write_group,
3435 phy_debug_mode_flags &
3436 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3448 if (group_failed == 0) {
3449 for (read_group = write_group *
3450 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3453 read_group < (write_group + 1)
3454 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3455 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3457 read_group++, read_test_bgn +=
3458 RW_MGR_MEM_DQ_PER_READ_DQS) {
3459 if (!((STATIC_CALIB_STEPS) &
3460 CALIB_SKIP_WRITES)) {
3461 if (!rw_mgr_mem_calibrate_vfifo_end
3462 (read_group, read_test_bgn)) {
3465 if (!(gbl->phy_debug_mode_flags
3466 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3474 if (group_failed != 0)
3479 * USER If there are any failing groups then report
3482 if (failing_groups != 0)
3485 /* Calibrate the LFIFO */
3486 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3488 * If we're skipping groups as part of debug,
3489 * don't calibrate LFIFO.
3491 if (param->skip_groups == 0) {
3492 if (!rw_mgr_mem_calibrate_lfifo())
3500 * Do not remove this line as it makes sure all of our decisions
3501 * have been applied.
3503 writel(0, &sdr_scc_mgr->update);
3507 static uint32_t run_mem_calibrate(void)
3510 uint32_t debug_info;
3512 debug("%s:%d\n", __func__, __LINE__);
3514 /* Reset pass/fail status shown on afi_cal_success/fail */
3515 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3517 /* stop tracking manger */
3518 uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3520 writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3523 rw_mgr_mem_initialize();
3525 pass = mem_calibrate();
3527 mem_precharge_and_activate();
3528 writel(0, &phy_mgr_cmd->fifo_reset);
3532 * Don't return control of the PHY back to AFI when in debug mode.
3534 if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3535 rw_mgr_mem_handoff();
3537 * In Hard PHY this is a 2-bit control:
3539 * 1: DDIO Mux Select
3541 writel(0x2, &phy_mgr_cfg->mux_sel);
3544 writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3547 printf("%s: CALIBRATION PASSED\n", __FILE__);
3552 if (gbl->fom_in > 0xff)
3555 if (gbl->fom_out > 0xff)
3556 gbl->fom_out = 0xff;
3558 /* Update the FOM in the register file */
3559 debug_info = gbl->fom_in;
3560 debug_info |= gbl->fom_out << 8;
3561 writel(debug_info, &sdr_reg_file->fom);
3563 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3564 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3566 printf("%s: CALIBRATION FAILED\n", __FILE__);
3568 debug_info = gbl->error_stage;
3569 debug_info |= gbl->error_substage << 8;
3570 debug_info |= gbl->error_group << 16;
3572 writel(debug_info, &sdr_reg_file->failing_stage);
3573 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3574 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3576 /* Update the failing group/stage in the register file */
3577 debug_info = gbl->error_stage;
3578 debug_info |= gbl->error_substage << 8;
3579 debug_info |= gbl->error_group << 16;
3580 writel(debug_info, &sdr_reg_file->failing_stage);
3587 * hc_initialize_rom_data() - Initialize ROM data
3589 * Initialize ROM data.
3591 static void hc_initialize_rom_data(void)
3595 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3596 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3597 writel(inst_rom_init[i], addr + (i << 2));
3599 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3600 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3601 writel(ac_rom_init[i], addr + (i << 2));
3605 * initialize_reg_file() - Initialize SDR register file
3607 * Initialize SDR register file.
3609 static void initialize_reg_file(void)
3611 /* Initialize the register file with the correct data */
3612 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3613 writel(0, &sdr_reg_file->debug_data_addr);
3614 writel(0, &sdr_reg_file->cur_stage);
3615 writel(0, &sdr_reg_file->fom);
3616 writel(0, &sdr_reg_file->failing_stage);
3617 writel(0, &sdr_reg_file->debug1);
3618 writel(0, &sdr_reg_file->debug2);
3622 * initialize_hps_phy() - Initialize HPS PHY
3624 * Initialize HPS PHY.
3626 static void initialize_hps_phy(void)
3630 * Tracking also gets configured here because it's in the
3633 uint32_t trk_sample_count = 7500;
3634 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3636 * Format is number of outer loops in the 16 MSB, sample
3641 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3642 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3643 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3644 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3645 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3646 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3648 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3649 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3651 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3652 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3654 writel(reg, &sdr_ctrl->phy_ctrl0);
3657 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3659 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3660 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3661 trk_long_idle_sample_count);
3662 writel(reg, &sdr_ctrl->phy_ctrl1);
3665 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3666 trk_long_idle_sample_count >>
3667 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3668 writel(reg, &sdr_ctrl->phy_ctrl2);
3671 static void initialize_tracking(void)
3673 uint32_t concatenated_longidle = 0x0;
3674 uint32_t concatenated_delays = 0x0;
3675 uint32_t concatenated_rw_addr = 0x0;
3676 uint32_t concatenated_refresh = 0x0;
3677 uint32_t trk_sample_count = 7500;
3678 uint32_t dtaps_per_ptap;
3682 * compute usable version of value in case we skip full
3687 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3689 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3693 concatenated_longidle = concatenated_longidle ^ 10;
3694 /*longidle outer loop */
3695 concatenated_longidle = concatenated_longidle << 16;
3696 concatenated_longidle = concatenated_longidle ^ 100;
3697 /*longidle sample count */
3698 concatenated_delays = concatenated_delays ^ 243;
3699 /* trfc, worst case of 933Mhz 4Gb */
3700 concatenated_delays = concatenated_delays << 8;
3701 concatenated_delays = concatenated_delays ^ 14;
3702 /* trcd, worst case */
3703 concatenated_delays = concatenated_delays << 8;
3704 concatenated_delays = concatenated_delays ^ 10;
3706 concatenated_delays = concatenated_delays << 8;
3707 concatenated_delays = concatenated_delays ^ 4;
3710 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3711 concatenated_rw_addr = concatenated_rw_addr << 8;
3712 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3713 concatenated_rw_addr = concatenated_rw_addr << 8;
3714 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3715 concatenated_rw_addr = concatenated_rw_addr << 8;
3716 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3718 concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3719 concatenated_refresh = concatenated_refresh << 24;
3720 concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3722 /* Initialize the register file with the correct data */
3723 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3724 writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3725 writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3726 writel(concatenated_delays, &sdr_reg_file->delays);
3727 writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3728 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3729 writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3732 int sdram_calibration_full(void)
3734 struct param_type my_param;
3735 struct gbl_type my_gbl;
3742 /* Initialize the debug mode flags */
3743 gbl->phy_debug_mode_flags = 0;
3744 /* Set the calibration enabled by default */
3745 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3747 * Only sweep all groups (regardless of fail state) by default
3748 * Set enabled read test by default.
3750 #if DISABLE_GUARANTEED_READ
3751 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3753 /* Initialize the register file */
3754 initialize_reg_file();
3756 /* Initialize any PHY CSR */
3757 initialize_hps_phy();
3759 scc_mgr_initialize();
3761 initialize_tracking();
3763 /* USER Enable all ranks, groups */
3764 for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3765 param->skip_ranks[i] = 0;
3766 for (i = 0; i < NUM_SHADOW_REGS; ++i)
3767 param->skip_shadow_regs[i] = 0;
3768 param->skip_groups = 0;
3770 printf("%s: Preparing to start memory calibration\n", __FILE__);
3772 debug("%s:%d\n", __func__, __LINE__);
3773 debug_cond(DLEVEL == 1,
3774 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3775 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3776 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3777 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3778 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3779 debug_cond(DLEVEL == 1,
3780 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3781 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3782 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3783 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3784 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3785 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3786 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3787 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3788 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3789 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3790 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3791 IO_IO_OUT2_DELAY_MAX);
3792 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3793 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3795 hc_initialize_rom_data();
3797 /* update info for sims */
3798 reg_file_set_stage(CAL_STAGE_NIL);
3799 reg_file_set_group(0);
3802 * Load global needed for those actions that require
3803 * some dynamic calibration support.
3805 dyn_calib_steps = STATIC_CALIB_STEPS;
3807 * Load global to allow dynamic selection of delay loop settings
3808 * based on calibration mode.
3810 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3811 skip_delay_mask = 0xff;
3813 skip_delay_mask = 0x0;
3815 pass = run_mem_calibrate();
3817 printf("%s: Calibration complete\n", __FILE__);