drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179         uint32_t all_groups, uint32_t all_ranks)
1180 {
1181         uint32_t r, vg;
1182         uint32_t correct_mask_vg;
1183         uint32_t tmp_bit_chk;
1184         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1186         uint32_t addr;
1187         uint32_t base_rw_mgr;
1188
1189         *bit_chk = param->read_correct_mask;
1190         correct_mask_vg = param->read_correct_mask_vg;
1191
1192         uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193                 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1194
1195         for (r = rank_bgn; r < rank_end; r++) {
1196                 if (param->skip_ranks[r])
1197                         /* request to skip the rank */
1198                         continue;
1199
1200                 /* set rank */
1201                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1202
1203                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1204
1205                 writel(RW_MGR_READ_B2B_WAIT1,
1206                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1207
1208                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209                 writel(RW_MGR_READ_B2B_WAIT2,
1210                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1211
1212                 if (quick_read_mode)
1213                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214                         /* need at least two (1+1) reads to capture failures */
1215                 else if (all_groups)
1216                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1217                 else
1218                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1219
1220                 writel(RW_MGR_READ_B2B,
1221                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1222                 if (all_groups)
1223                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225                                &sdr_rw_load_mgr_regs->load_cntr3);
1226                 else
1227                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1228
1229                 writel(RW_MGR_READ_B2B,
1230                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1231
1232                 tmp_bit_chk = 0;
1233                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234                         /* reset the fifos to get pointers to known state */
1235                         writel(0, &phy_mgr_cmd->fifo_reset);
1236                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1238
1239                         tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240                                 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1241
1242                         if (all_groups)
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1244                         else
1245                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1246
1247                         writel(RW_MGR_READ_B2B, addr +
1248                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1249                                vg) << 2));
1250
1251                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1253
1254                         if (vg == 0)
1255                                 break;
1256                 }
1257                 *bit_chk &= tmp_bit_chk;
1258         }
1259
1260         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1262
1263         if (all_correct) {
1264                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266                            (%u == %u) => %lu", __func__, __LINE__, group,
1267                            all_groups, *bit_chk, param->read_correct_mask,
1268                            (long unsigned int)(*bit_chk ==
1269                            param->read_correct_mask));
1270                 return *bit_chk == param->read_correct_mask;
1271         } else  {
1272                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273                 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274                            (%u != %lu) => %lu\n", __func__, __LINE__,
1275                            group, all_groups, *bit_chk, (long unsigned int)0,
1276                            (long unsigned int)(*bit_chk != 0x00));
1277                 return *bit_chk != 0x00;
1278         }
1279 }
1280
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282         uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283         uint32_t all_groups)
1284 {
1285         return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286                                               bit_chk, all_groups, 1);
1287 }
1288
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1290 {
1291         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1292         (*v)++;
1293 }
1294
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1296 {
1297         uint32_t i;
1298
1299         for (i = 0; i < VFIFO_SIZE-1; i++)
1300                 rw_mgr_incr_vfifo(grp, v);
1301 }
1302
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1304 {
1305         uint32_t  v;
1306         uint32_t fail_cnt = 0;
1307         uint32_t test_status;
1308
1309         for (v = 0; v < VFIFO_SIZE; ) {
1310                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311                            __func__, __LINE__, v);
1312                 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313                         (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1314                 if (!test_status) {
1315                         fail_cnt++;
1316
1317                         if (fail_cnt == 2)
1318                                 break;
1319                 }
1320
1321                 /* fiddle with FIFO */
1322                 rw_mgr_incr_vfifo(grp, &v);
1323         }
1324
1325         if (v >= VFIFO_SIZE) {
1326                 /* no failing read found!! Something must have gone wrong */
1327                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328                            __func__, __LINE__);
1329                 return 0;
1330         } else {
1331                 return v;
1332         }
1333 }
1334
1335 /**
1336  * sdr_find_phase() - Find DQS enable phase
1337  * @working:    If 1, look for working phase, if 0, look for non-working phase
1338  * @grp:        Read/Write group
1339  * @v:          VFIFO value
1340  * @work:       Working window position
1341  * @i:          Iterator
1342  * @p:          DQS Phase Iterator
1343  *
1344  * Find working or non-working DQS enable phase setting.
1345  */
1346 static int sdr_find_phase(int working, const u32 grp, u32 *v, u32 *work,
1347                           u32 *i, u32 *p)
1348 {
1349         u32 ret, bit_chk;
1350         const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1351
1352         for (; *i < end; (*i)++) {
1353                 if (working)
1354                         *p = 0;
1355
1356                 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++) {
1357                         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1358
1359                         ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1360                                                 PASS_ONE_BIT, &bit_chk, 0);
1361                         if (!working)
1362                                 ret = !ret;
1363
1364                         if (ret)
1365                                 return 0;
1366
1367                         *work += IO_DELAY_PER_OPA_TAP;
1368                 }
1369
1370                 if (*p > IO_DQS_EN_PHASE_MAX) {
1371                         /* Fiddle with FIFO. */
1372                         rw_mgr_incr_vfifo(grp, v);
1373                         if (!working)
1374                                 *p = 0;
1375                 }
1376         }
1377
1378         return -EINVAL;
1379 }
1380
1381 static int sdr_working_phase(uint32_t grp, uint32_t *work_bgn,
1382                              uint32_t *v, uint32_t *d, uint32_t *p,
1383                              uint32_t *i)
1384 {
1385         const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1386                                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1387         int ret;
1388
1389         *work_bgn = 0;
1390
1391         for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1392                 *i = 0;
1393                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1394                 ret = sdr_find_phase(1, grp, v, work_bgn, i, p);
1395                 if (!ret)
1396                         return 0;
1397                 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1398         }
1399
1400         /* Cannot find working solution */
1401         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1402                    __func__, __LINE__);
1403         return -EINVAL;
1404 }
1405
1406 static void sdr_backup_phase(uint32_t grp,
1407                              uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1408                              uint32_t *p)
1409 {
1410         uint32_t tmp_delay;
1411         u32 bit_chk;
1412
1413         /* Special case code for backing up a phase */
1414         if (*p == 0) {
1415                 *p = IO_DQS_EN_PHASE_MAX;
1416                 rw_mgr_decr_vfifo(grp, v);
1417         } else {
1418                 (*p)--;
1419         }
1420         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1421         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1422
1423         for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1424                 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1425                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1426
1427                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1428                                                              PASS_ONE_BIT,
1429                                                              &bit_chk, 0)) {
1430                         *work_bgn = tmp_delay;
1431                         break;
1432                 }
1433         }
1434
1435         /*
1436          * Restore VFIFO to old state before we decremented it
1437          * (if needed).
1438          */
1439         (*p)++;
1440         if (*p > IO_DQS_EN_PHASE_MAX) {
1441                 *p = 0;
1442                 rw_mgr_incr_vfifo(grp, v);
1443         }
1444
1445         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1446 }
1447
1448 static int sdr_nonworking_phase(uint32_t grp, uint32_t *v, uint32_t *d,
1449                                 uint32_t *p, uint32_t *i, uint32_t *work_end)
1450 {
1451         int ret;
1452
1453         (*p)++;
1454         *work_end += IO_DELAY_PER_OPA_TAP;
1455         if (*p > IO_DQS_EN_PHASE_MAX) {
1456                 /* Fiddle with FIFO. */
1457                 *p = 0;
1458                 rw_mgr_incr_vfifo(grp, v);
1459         }
1460
1461         ret = sdr_find_phase(0, grp, v, work_end, i, p);
1462         if (ret) {
1463                 /* Cannot see edge of failing read. */
1464                 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1465                            __func__, __LINE__);
1466         }
1467
1468         return ret;
1469 }
1470
1471 /**
1472  * sdr_find_window_center() - Find center of the working DQS window.
1473  * @grp:        Read/Write group
1474  * @work_bgn:   First working settings
1475  * @work_end:   Last working settings
1476  * @val:        VFIFO value
1477  *
1478  * Find center of the working DQS enable window.
1479  */
1480 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1481                                   const u32 work_end, const u32 val)
1482 {
1483         u32 bit_chk, work_mid, v = val;
1484         int tmp_delay = 0;
1485         int i, p, d;
1486
1487         work_mid = (work_bgn + work_end) / 2;
1488
1489         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1490                    work_bgn, work_end, work_mid);
1491         /* Get the middle delay to be less than a VFIFO delay */
1492         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1493
1494         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1495         work_mid %= tmp_delay;
1496         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1497
1498         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1499         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1500                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1501         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1502
1503         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1504
1505         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1506         if (d > IO_DQS_EN_DELAY_MAX)
1507                 d = IO_DQS_EN_DELAY_MAX;
1508         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1509
1510         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1511
1512         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1513         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1514
1515         /*
1516          * push vfifo until we can successfully calibrate. We can do this
1517          * because the largest possible margin in 1 VFIFO cycle.
1518          */
1519         for (i = 0; i < VFIFO_SIZE; i++) {
1520                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1521                            v);
1522                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1523                                                              PASS_ONE_BIT,
1524                                                              &bit_chk, 0)) {
1525                         debug_cond(DLEVEL == 2,
1526                                    "%s:%d center: found: vfifo=%u ptap=%u dtap=%u\n",
1527                                    __func__, __LINE__, v, p, d);
1528                         return 0;
1529                 }
1530
1531                 /* Fiddle with FIFO. */
1532                 rw_mgr_incr_vfifo(grp, &v);
1533         }
1534
1535         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1536                    __func__, __LINE__);
1537         return -EINVAL;
1538 }
1539
1540 /* find a good dqs enable to use */
1541 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1542 {
1543         uint32_t v, d, p, i;
1544         uint32_t bit_chk;
1545         uint32_t dtaps_per_ptap;
1546         uint32_t work_bgn, work_end;
1547         uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1548
1549         debug("%s:%d %u\n", __func__, __LINE__, grp);
1550
1551         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1552
1553         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1554         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1555
1556         /* ************************************************************** */
1557         /* * Step 0 : Determine number of delay taps for each phase tap * */
1558         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1559
1560         /* ********************************************************* */
1561         /* * Step 1 : First push vfifo until we get a failing read * */
1562         v = find_vfifo_read(grp, &bit_chk);
1563
1564         /* ******************************************************** */
1565         /* * step 2: find first working phase, increment in ptaps * */
1566         work_bgn = 0;
1567         if (sdr_working_phase(grp, &work_bgn, &v, &d, &p, &i))
1568                 return 0;
1569
1570         work_end = work_bgn;
1571
1572         /*
1573          * If d is 0 then the working window covers a phase tap and
1574          * we can follow the old procedure otherwise, we've found the beginning,
1575          * and we need to increment the dtaps until we find the end.
1576          */
1577         if (d == 0) {
1578                 /* ********************************************************* */
1579                 /* * step 3a: if we have room, back off by one and
1580                 increment in dtaps * */
1581
1582                 sdr_backup_phase(grp, &work_bgn, &v, &d, &p);
1583
1584                 /* ********************************************************* */
1585                 /* * step 4a: go forward from working phase to non working
1586                 phase, increment in ptaps * */
1587                 if (sdr_nonworking_phase(grp, &v, &d, &p, &i, &work_end))
1588                         return 0;
1589
1590                 /* ********************************************************* */
1591                 /* * step 5a:  back off one from last, increment in dtaps  * */
1592
1593                 /* Special case code for backing up a phase */
1594                 if (p == 0) {
1595                         p = IO_DQS_EN_PHASE_MAX;
1596                         rw_mgr_decr_vfifo(grp, &v);
1597                 } else {
1598                         p = p - 1;
1599                 }
1600
1601                 work_end -= IO_DELAY_PER_OPA_TAP;
1602                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1603
1604                 /* * The actual increment of dtaps is done outside of
1605                 the if/else loop to share code */
1606                 d = 0;
1607
1608                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1609                            vfifo=%u ptap=%u\n", __func__, __LINE__,
1610                            v, p);
1611         } else {
1612                 /* ******************************************************* */
1613                 /* * step 3-5b:  Find the right edge of the window using
1614                 delay taps   * */
1615                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1616                            ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1617                            v, p, d, work_bgn);
1618
1619                 work_end = work_bgn;
1620         }
1621
1622         /* The dtap increment to find the failing edge is done here */
1623         for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1624                 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1625                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1626                                    end-2: dtap=%u\n", __func__, __LINE__, d);
1627                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1628
1629                         if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1630                                                                       PASS_ONE_BIT,
1631                                                                       &bit_chk, 0)) {
1632                                 break;
1633                         }
1634         }
1635
1636         /* Go back to working dtap */
1637         if (d != 0)
1638                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1639
1640         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1641                    ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1642                    v, p, d-1, work_end);
1643
1644         if (work_end < work_bgn) {
1645                 /* nil range */
1646                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1647                            failed\n", __func__, __LINE__);
1648                 return 0;
1649         }
1650
1651         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1652                    __func__, __LINE__, work_bgn, work_end);
1653
1654         /* *************************************************************** */
1655         /*
1656          * * We need to calculate the number of dtaps that equal a ptap
1657          * * To do that we'll back up a ptap and re-find the edge of the
1658          * * window using dtaps
1659          */
1660
1661         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1662                    for tracking\n", __func__, __LINE__);
1663
1664         /* Special case code for backing up a phase */
1665         if (p == 0) {
1666                 p = IO_DQS_EN_PHASE_MAX;
1667                 rw_mgr_decr_vfifo(grp, &v);
1668                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1669                            cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1670                            v, p);
1671         } else {
1672                 p = p - 1;
1673                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1674                            phase only: v=%u p=%u", __func__, __LINE__,
1675                            v, p);
1676         }
1677
1678         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1679
1680         /*
1681          * Increase dtap until we first see a passing read (in case the
1682          * window is smaller than a ptap),
1683          * and then a failing read to mark the edge of the window again
1684          */
1685
1686         /* Find a passing read */
1687         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1688                    __func__, __LINE__);
1689         found_passing_read = 0;
1690         found_failing_read = 0;
1691         initial_failing_dtap = d;
1692         for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1693                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1694                            read d=%u\n", __func__, __LINE__, d);
1695                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1696
1697                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1698                                                              PASS_ONE_BIT,
1699                                                              &bit_chk, 0)) {
1700                         found_passing_read = 1;
1701                         break;
1702                 }
1703         }
1704
1705         if (found_passing_read) {
1706                 /* Find a failing read */
1707                 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1708                            read\n", __func__, __LINE__);
1709                 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1710                         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1711                                    testing read d=%u\n", __func__, __LINE__, d);
1712                         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1713
1714                         if (!rw_mgr_mem_calibrate_read_test_all_ranks
1715                                 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1716                                 found_failing_read = 1;
1717                                 break;
1718                         }
1719                 }
1720         } else {
1721                 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1722                            calculate dtaps", __func__, __LINE__);
1723                 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1724         }
1725
1726         /*
1727          * The dynamically calculated dtaps_per_ptap is only valid if we
1728          * found a passing/failing read. If we didn't, it means d hit the max
1729          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1730          * statically calculated value.
1731          */
1732         if (found_passing_read && found_failing_read)
1733                 dtaps_per_ptap = d - initial_failing_dtap;
1734
1735         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1736         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1737                    - %u = %u",  __func__, __LINE__, d,
1738                    initial_failing_dtap, dtaps_per_ptap);
1739
1740         /* ******************************************** */
1741         /* * step 6:  Find the centre of the window   * */
1742         if (sdr_find_window_centre(grp, work_bgn, work_end, v))
1743                 return 0; /* FIXME: Old code, return 0 means failure :-( */
1744
1745         return 1;
1746 }
1747
1748 /* per-bit deskew DQ and center */
1749 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1750         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1751         uint32_t use_read_test, uint32_t update_fom)
1752 {
1753         uint32_t i, p, d, min_index;
1754         /*
1755          * Store these as signed since there are comparisons with
1756          * signed numbers.
1757          */
1758         uint32_t bit_chk;
1759         uint32_t sticky_bit_chk;
1760         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1761         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1762         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1763         int32_t mid;
1764         int32_t orig_mid_min, mid_min;
1765         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1766                 final_dqs_en;
1767         int32_t dq_margin, dqs_margin;
1768         uint32_t stop;
1769         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1770         uint32_t addr;
1771
1772         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1773
1774         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1775         start_dqs = readl(addr + (read_group << 2));
1776         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1777                 start_dqs_en = readl(addr + ((read_group << 2)
1778                                      - IO_DQS_EN_DELAY_OFFSET));
1779
1780         /* set the left and right edge of each bit to an illegal value */
1781         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1782         sticky_bit_chk = 0;
1783         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1784                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1785                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1786         }
1787
1788         /* Search for the left edge of the window for each bit */
1789         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1790                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1791
1792                 writel(0, &sdr_scc_mgr->update);
1793
1794                 /*
1795                  * Stop searching when the read test doesn't pass AND when
1796                  * we've seen a passing read on every bit.
1797                  */
1798                 if (use_read_test) {
1799                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1800                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1801                                 &bit_chk, 0, 0);
1802                 } else {
1803                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1804                                                         0, PASS_ONE_BIT,
1805                                                         &bit_chk, 0);
1806                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1807                                 (read_group - (write_group *
1808                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1809                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1810                         stop = (bit_chk == 0);
1811                 }
1812                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1813                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1814                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1815                            && %u", __func__, __LINE__, d,
1816                            sticky_bit_chk,
1817                         param->read_correct_mask, stop);
1818
1819                 if (stop == 1) {
1820                         break;
1821                 } else {
1822                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1823                                 if (bit_chk & 1) {
1824                                         /* Remember a passing test as the
1825                                         left_edge */
1826                                         left_edge[i] = d;
1827                                 } else {
1828                                         /* If a left edge has not been seen yet,
1829                                         then a future passing test will mark
1830                                         this edge as the right edge */
1831                                         if (left_edge[i] ==
1832                                                 IO_IO_IN_DELAY_MAX + 1) {
1833                                                 right_edge[i] = -(d + 1);
1834                                         }
1835                                 }
1836                                 bit_chk = bit_chk >> 1;
1837                         }
1838                 }
1839         }
1840
1841         /* Reset DQ delay chains to 0 */
1842         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1843         sticky_bit_chk = 0;
1844         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1845                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1846                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1847                            i, left_edge[i], i, right_edge[i]);
1848
1849                 /*
1850                  * Check for cases where we haven't found the left edge,
1851                  * which makes our assignment of the the right edge invalid.
1852                  * Reset it to the illegal value.
1853                  */
1854                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1855                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1856                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1857                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1858                                    right_edge[%u]: %d\n", __func__, __LINE__,
1859                                    i, right_edge[i]);
1860                 }
1861
1862                 /*
1863                  * Reset sticky bit (except for bits where we have seen
1864                  * both the left and right edge).
1865                  */
1866                 sticky_bit_chk = sticky_bit_chk << 1;
1867                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1868                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1869                         sticky_bit_chk = sticky_bit_chk | 1;
1870                 }
1871
1872                 if (i == 0)
1873                         break;
1874         }
1875
1876         /* Search for the right edge of the window for each bit */
1877         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1878                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1879                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1880                         uint32_t delay = d + start_dqs_en;
1881                         if (delay > IO_DQS_EN_DELAY_MAX)
1882                                 delay = IO_DQS_EN_DELAY_MAX;
1883                         scc_mgr_set_dqs_en_delay(read_group, delay);
1884                 }
1885                 scc_mgr_load_dqs(read_group);
1886
1887                 writel(0, &sdr_scc_mgr->update);
1888
1889                 /*
1890                  * Stop searching when the read test doesn't pass AND when
1891                  * we've seen a passing read on every bit.
1892                  */
1893                 if (use_read_test) {
1894                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1895                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1896                                 &bit_chk, 0, 0);
1897                 } else {
1898                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1899                                                         0, PASS_ONE_BIT,
1900                                                         &bit_chk, 0);
1901                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1902                                 (read_group - (write_group *
1903                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1904                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1905                         stop = (bit_chk == 0);
1906                 }
1907                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1908                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1909
1910                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1911                            %u && %u", __func__, __LINE__, d,
1912                            sticky_bit_chk, param->read_correct_mask, stop);
1913
1914                 if (stop == 1) {
1915                         break;
1916                 } else {
1917                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1918                                 if (bit_chk & 1) {
1919                                         /* Remember a passing test as
1920                                         the right_edge */
1921                                         right_edge[i] = d;
1922                                 } else {
1923                                         if (d != 0) {
1924                                                 /* If a right edge has not been
1925                                                 seen yet, then a future passing
1926                                                 test will mark this edge as the
1927                                                 left edge */
1928                                                 if (right_edge[i] ==
1929                                                 IO_IO_IN_DELAY_MAX + 1) {
1930                                                         left_edge[i] = -(d + 1);
1931                                                 }
1932                                         } else {
1933                                                 /* d = 0 failed, but it passed
1934                                                 when testing the left edge,
1935                                                 so it must be marginal,
1936                                                 set it to -1 */
1937                                                 if (right_edge[i] ==
1938                                                         IO_IO_IN_DELAY_MAX + 1 &&
1939                                                         left_edge[i] !=
1940                                                         IO_IO_IN_DELAY_MAX
1941                                                         + 1) {
1942                                                         right_edge[i] = -1;
1943                                                 }
1944                                                 /* If a right edge has not been
1945                                                 seen yet, then a future passing
1946                                                 test will mark this edge as the
1947                                                 left edge */
1948                                                 else if (right_edge[i] ==
1949                                                         IO_IO_IN_DELAY_MAX +
1950                                                         1) {
1951                                                         left_edge[i] = -(d + 1);
1952                                                 }
1953                                         }
1954                                 }
1955
1956                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1957                                            d=%u]: ", __func__, __LINE__, d);
1958                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1959                                            (int)(bit_chk & 1), i, left_edge[i]);
1960                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1961                                            right_edge[i]);
1962                                 bit_chk = bit_chk >> 1;
1963                         }
1964                 }
1965         }
1966
1967         /* Check that all bits have a window */
1968         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1969                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1970                            %d right_edge[%u]: %d", __func__, __LINE__,
1971                            i, left_edge[i], i, right_edge[i]);
1972                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1973                         == IO_IO_IN_DELAY_MAX + 1)) {
1974                         /*
1975                          * Restore delay chain settings before letting the loop
1976                          * in rw_mgr_mem_calibrate_vfifo to retry different
1977                          * dqs/ck relationships.
1978                          */
1979                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
1980                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1981                                 scc_mgr_set_dqs_en_delay(read_group,
1982                                                          start_dqs_en);
1983                         }
1984                         scc_mgr_load_dqs(read_group);
1985                         writel(0, &sdr_scc_mgr->update);
1986
1987                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
1988                                    find edge [%u]: %d %d", __func__, __LINE__,
1989                                    i, left_edge[i], right_edge[i]);
1990                         if (use_read_test) {
1991                                 set_failing_group_stage(read_group *
1992                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
1993                                         CAL_STAGE_VFIFO,
1994                                         CAL_SUBSTAGE_VFIFO_CENTER);
1995                         } else {
1996                                 set_failing_group_stage(read_group *
1997                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
1998                                         CAL_STAGE_VFIFO_AFTER_WRITES,
1999                                         CAL_SUBSTAGE_VFIFO_CENTER);
2000                         }
2001                         return 0;
2002                 }
2003         }
2004
2005         /* Find middle of window for each DQ bit */
2006         mid_min = left_edge[0] - right_edge[0];
2007         min_index = 0;
2008         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2009                 mid = left_edge[i] - right_edge[i];
2010                 if (mid < mid_min) {
2011                         mid_min = mid;
2012                         min_index = i;
2013                 }
2014         }
2015
2016         /*
2017          * -mid_min/2 represents the amount that we need to move DQS.
2018          * If mid_min is odd and positive we'll need to add one to
2019          * make sure the rounding in further calculations is correct
2020          * (always bias to the right), so just add 1 for all positive values.
2021          */
2022         if (mid_min > 0)
2023                 mid_min++;
2024
2025         mid_min = mid_min / 2;
2026
2027         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2028                    __func__, __LINE__, mid_min, min_index);
2029
2030         /* Determine the amount we can change DQS (which is -mid_min) */
2031         orig_mid_min = mid_min;
2032         new_dqs = start_dqs - mid_min;
2033         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2034                 new_dqs = IO_DQS_IN_DELAY_MAX;
2035         else if (new_dqs < 0)
2036                 new_dqs = 0;
2037
2038         mid_min = start_dqs - new_dqs;
2039         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2040                    mid_min, new_dqs);
2041
2042         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2043                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2044                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2045                 else if (start_dqs_en - mid_min < 0)
2046                         mid_min += start_dqs_en - mid_min;
2047         }
2048         new_dqs = start_dqs - mid_min;
2049
2050         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2051                    new_dqs=%d mid_min=%d\n", start_dqs,
2052                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2053                    new_dqs, mid_min);
2054
2055         /* Initialize data for export structures */
2056         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2057         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2058
2059         /* add delay to bring centre of all DQ windows to the same "level" */
2060         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2061                 /* Use values before divide by 2 to reduce round off error */
2062                 shift_dq = (left_edge[i] - right_edge[i] -
2063                         (left_edge[min_index] - right_edge[min_index]))/2  +
2064                         (orig_mid_min - mid_min);
2065
2066                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2067                            shift_dq[%u]=%d\n", i, shift_dq);
2068
2069                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2070                 temp_dq_in_delay1 = readl(addr + (p << 2));
2071                 temp_dq_in_delay2 = readl(addr + (i << 2));
2072
2073                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2074                         (int32_t)IO_IO_IN_DELAY_MAX) {
2075                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2076                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2077                         shift_dq = -(int32_t)temp_dq_in_delay1;
2078                 }
2079                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2080                            shift_dq[%u]=%d\n", i, shift_dq);
2081                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2082                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2083                 scc_mgr_load_dq(p);
2084
2085                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2086                            left_edge[i] - shift_dq + (-mid_min),
2087                            right_edge[i] + shift_dq - (-mid_min));
2088                 /* To determine values for export structures */
2089                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2090                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2091
2092                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2093                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2094         }
2095
2096         final_dqs = new_dqs;
2097         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2098                 final_dqs_en = start_dqs_en - mid_min;
2099
2100         /* Move DQS-en */
2101         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2102                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2103                 scc_mgr_load_dqs(read_group);
2104         }
2105
2106         /* Move DQS */
2107         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2108         scc_mgr_load_dqs(read_group);
2109         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2110                    dqs_margin=%d", __func__, __LINE__,
2111                    dq_margin, dqs_margin);
2112
2113         /*
2114          * Do not remove this line as it makes sure all of our decisions
2115          * have been applied. Apply the update bit.
2116          */
2117         writel(0, &sdr_scc_mgr->update);
2118
2119         return (dq_margin >= 0) && (dqs_margin >= 0);
2120 }
2121
2122 /**
2123  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2124  * @rw_group:   Read/Write Group
2125  * @phase:      DQ/DQS phase
2126  *
2127  * Because initially no communication ca be reliably performed with the memory
2128  * device, the sequencer uses a guaranteed write mechanism to write data into
2129  * the memory device.
2130  */
2131 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2132                                                  const u32 phase)
2133 {
2134         int ret;
2135
2136         /* Set a particular DQ/DQS phase. */
2137         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2138
2139         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2140                    __func__, __LINE__, rw_group, phase);
2141
2142         /*
2143          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2144          * Load up the patterns used by read calibration using the
2145          * current DQDQS phase.
2146          */
2147         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2148
2149         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2150                 return 0;
2151
2152         /*
2153          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2154          * Back-to-Back reads of the patterns used for calibration.
2155          */
2156         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2157         if (ret)
2158                 debug_cond(DLEVEL == 1,
2159                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2160                            __func__, __LINE__, rw_group, phase);
2161         return ret;
2162 }
2163
2164 /**
2165  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2166  * @rw_group:   Read/Write Group
2167  * @test_bgn:   Rank at which the test begins
2168  *
2169  * DQS enable calibration ensures reliable capture of the DQ signal without
2170  * glitches on the DQS line.
2171  */
2172 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2173                                                        const u32 test_bgn)
2174 {
2175         /*
2176          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2177          * DQS and DQS Eanble Signal Relationships.
2178          */
2179
2180         /* We start at zero, so have one less dq to devide among */
2181         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2182                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2183         int found;
2184         u32 i, p, d, r;
2185
2186         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2187
2188         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2189         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2190              r += NUM_RANKS_PER_SHADOW_REG) {
2191                 for (i = 0, p = test_bgn, d = 0;
2192                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2193                      i++, p++, d += delay_step) {
2194                         debug_cond(DLEVEL == 1,
2195                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2196                                    __func__, __LINE__, rw_group, r, i, p, d);
2197
2198                         scc_mgr_set_dq_in_delay(p, d);
2199                         scc_mgr_load_dq(p);
2200                 }
2201
2202                 writel(0, &sdr_scc_mgr->update);
2203         }
2204
2205         /*
2206          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2207          * dq_in_delay values
2208          */
2209         found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2210
2211         debug_cond(DLEVEL == 1,
2212                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2213                    __func__, __LINE__, rw_group, found);
2214
2215         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2216              r += NUM_RANKS_PER_SHADOW_REG) {
2217                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2218                 writel(0, &sdr_scc_mgr->update);
2219         }
2220
2221         if (!found)
2222                 return -EINVAL;
2223
2224         return 0;
2225
2226 }
2227
2228 /**
2229  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2230  * @rw_group:           Read/Write Group
2231  * @test_bgn:           Rank at which the test begins
2232  * @use_read_test:      Perform a read test
2233  * @update_fom:         Update FOM
2234  *
2235  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2236  * within a group.
2237  */
2238 static int
2239 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2240                                       const int use_read_test,
2241                                       const int update_fom)
2242
2243 {
2244         int ret, grp_calibrated;
2245         u32 rank_bgn, sr;
2246
2247         /*
2248          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2249          * Read per-bit deskew can be done on a per shadow register basis.
2250          */
2251         grp_calibrated = 1;
2252         for (rank_bgn = 0, sr = 0;
2253              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2254              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2255                 /* Check if this set of ranks should be skipped entirely. */
2256                 if (param->skip_shadow_regs[sr])
2257                         continue;
2258
2259                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2260                                                         rw_group, test_bgn,
2261                                                         use_read_test,
2262                                                         update_fom);
2263                 if (ret)
2264                         continue;
2265
2266                 grp_calibrated = 0;
2267         }
2268
2269         if (!grp_calibrated)
2270                 return -EIO;
2271
2272         return 0;
2273 }
2274
2275 /**
2276  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2277  * @rw_group:           Read/Write Group
2278  * @test_bgn:           Rank at which the test begins
2279  *
2280  * Stage 1: Calibrate the read valid prediction FIFO.
2281  *
2282  * This function implements UniPHY calibration Stage 1, as explained in
2283  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2284  *
2285  * - read valid prediction will consist of finding:
2286  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2287  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2288  *  - we also do a per-bit deskew on the DQ lines.
2289  */
2290 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2291 {
2292         uint32_t p, d;
2293         uint32_t dtaps_per_ptap;
2294         uint32_t failed_substage;
2295
2296         int ret;
2297
2298         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2299
2300         /* Update info for sims */
2301         reg_file_set_group(rw_group);
2302         reg_file_set_stage(CAL_STAGE_VFIFO);
2303         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2304
2305         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2306
2307         /* USER Determine number of delay taps for each phase tap. */
2308         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2309                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2310
2311         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2312                 /*
2313                  * In RLDRAMX we may be messing the delay of pins in
2314                  * the same write rw_group but outside of the current read
2315                  * the rw_group, but that's ok because we haven't calibrated
2316                  * output side yet.
2317                  */
2318                 if (d > 0) {
2319                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2320                                                                 rw_group, d);
2321                 }
2322
2323                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2324                         /* 1) Guaranteed Write */
2325                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2326                         if (ret)
2327                                 break;
2328
2329                         /* 2) DQS Enable Calibration */
2330                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2331                                                                           test_bgn);
2332                         if (ret) {
2333                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2334                                 continue;
2335                         }
2336
2337                         /* 3) Centering DQ/DQS */
2338                         /*
2339                          * If doing read after write calibration, do not update
2340                          * FOM now. Do it then.
2341                          */
2342                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2343                                                                 test_bgn, 1, 0);
2344                         if (ret) {
2345                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2346                                 continue;
2347                         }
2348
2349                         /* All done. */
2350                         goto cal_done_ok;
2351                 }
2352         }
2353
2354         /* Calibration Stage 1 failed. */
2355         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2356         return 0;
2357
2358         /* Calibration Stage 1 completed OK. */
2359 cal_done_ok:
2360         /*
2361          * Reset the delay chains back to zero if they have moved > 1
2362          * (check for > 1 because loop will increase d even when pass in
2363          * first case).
2364          */
2365         if (d > 2)
2366                 scc_mgr_zero_group(rw_group, 1);
2367
2368         return 1;
2369 }
2370
2371 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2372 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2373                                                uint32_t test_bgn)
2374 {
2375         uint32_t rank_bgn, sr;
2376         uint32_t grp_calibrated;
2377         uint32_t write_group;
2378
2379         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2380
2381         /* update info for sims */
2382
2383         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2384         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2385
2386         write_group = read_group;
2387
2388         /* update info for sims */
2389         reg_file_set_group(read_group);
2390
2391         grp_calibrated = 1;
2392         /* Read per-bit deskew can be done on a per shadow register basis */
2393         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2394                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2395                 /* Determine if this set of ranks should be skipped entirely */
2396                 if (!param->skip_shadow_regs[sr]) {
2397                 /* This is the last calibration round, update FOM here */
2398                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2399                                                                 write_group,
2400                                                                 read_group,
2401                                                                 test_bgn, 0,
2402                                                                 1)) {
2403                                 grp_calibrated = 0;
2404                         }
2405                 }
2406         }
2407
2408
2409         if (grp_calibrated == 0) {
2410                 set_failing_group_stage(write_group,
2411                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2412                                         CAL_SUBSTAGE_VFIFO_CENTER);
2413                 return 0;
2414         }
2415
2416         return 1;
2417 }
2418
2419 /* Calibrate LFIFO to find smallest read latency */
2420 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2421 {
2422         uint32_t found_one;
2423         uint32_t bit_chk;
2424
2425         debug("%s:%d\n", __func__, __LINE__);
2426
2427         /* update info for sims */
2428         reg_file_set_stage(CAL_STAGE_LFIFO);
2429         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2430
2431         /* Load up the patterns used by read calibration for all ranks */
2432         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2433         found_one = 0;
2434
2435         do {
2436                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2437                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2438                            __func__, __LINE__, gbl->curr_read_lat);
2439
2440                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2441                                                               NUM_READ_TESTS,
2442                                                               PASS_ALL_BITS,
2443                                                               &bit_chk, 1)) {
2444                         break;
2445                 }
2446
2447                 found_one = 1;
2448                 /* reduce read latency and see if things are working */
2449                 /* correctly */
2450                 gbl->curr_read_lat--;
2451         } while (gbl->curr_read_lat > 0);
2452
2453         /* reset the fifos to get pointers to known state */
2454
2455         writel(0, &phy_mgr_cmd->fifo_reset);
2456
2457         if (found_one) {
2458                 /* add a fudge factor to the read latency that was determined */
2459                 gbl->curr_read_lat += 2;
2460                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2461                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2462                            read_lat=%u\n", __func__, __LINE__,
2463                            gbl->curr_read_lat);
2464                 return 1;
2465         } else {
2466                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2467                                         CAL_SUBSTAGE_READ_LATENCY);
2468
2469                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2470                            read_lat=%u\n", __func__, __LINE__,
2471                            gbl->curr_read_lat);
2472                 return 0;
2473         }
2474 }
2475
2476 /*
2477  * issue write test command.
2478  * two variants are provided. one that just tests a write pattern and
2479  * another that tests datamask functionality.
2480  */
2481 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2482                                                   uint32_t test_dm)
2483 {
2484         uint32_t mcc_instruction;
2485         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2486                 ENABLE_SUPER_QUICK_CALIBRATION);
2487         uint32_t rw_wl_nop_cycles;
2488         uint32_t addr;
2489
2490         /*
2491          * Set counter and jump addresses for the right
2492          * number of NOP cycles.
2493          * The number of supported NOP cycles can range from -1 to infinity
2494          * Three different cases are handled:
2495          *
2496          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2497          *    mechanism will be used to insert the right number of NOPs
2498          *
2499          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2500          *    issuing the write command will jump straight to the
2501          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2502          *    data (for RLD), skipping
2503          *    the NOP micro-instruction all together
2504          *
2505          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2506          *    turned on in the same micro-instruction that issues the write
2507          *    command. Then we need
2508          *    to directly jump to the micro-instruction that sends out the data
2509          *
2510          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2511          *       (2 and 3). One jump-counter (0) is used to perform multiple
2512          *       write-read operations.
2513          *       one counter left to issue this command in "multiple-group" mode
2514          */
2515
2516         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2517
2518         if (rw_wl_nop_cycles == -1) {
2519                 /*
2520                  * CNTR 2 - We want to execute the special write operation that
2521                  * turns on DQS right away and then skip directly to the
2522                  * instruction that sends out the data. We set the counter to a
2523                  * large number so that the jump is always taken.
2524                  */
2525                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2526
2527                 /* CNTR 3 - Not used */
2528                 if (test_dm) {
2529                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2530                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2531                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2532                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2533                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2534                 } else {
2535                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2536                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2537                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2538                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2539                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2540                 }
2541         } else if (rw_wl_nop_cycles == 0) {
2542                 /*
2543                  * CNTR 2 - We want to skip the NOP operation and go straight
2544                  * to the DQS enable instruction. We set the counter to a large
2545                  * number so that the jump is always taken.
2546                  */
2547                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2548
2549                 /* CNTR 3 - Not used */
2550                 if (test_dm) {
2551                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2552                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2553                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2554                 } else {
2555                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2556                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2557                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2558                 }
2559         } else {
2560                 /*
2561                  * CNTR 2 - In this case we want to execute the next instruction
2562                  * and NOT take the jump. So we set the counter to 0. The jump
2563                  * address doesn't count.
2564                  */
2565                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2566                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2567
2568                 /*
2569                  * CNTR 3 - Set the nop counter to the number of cycles we
2570                  * need to loop for, minus 1.
2571                  */
2572                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2573                 if (test_dm) {
2574                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2575                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2576                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2577                 } else {
2578                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2579                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2580                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2581                 }
2582         }
2583
2584         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2585                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2586
2587         if (quick_write_mode)
2588                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2589         else
2590                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2591
2592         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2593
2594         /*
2595          * CNTR 1 - This is used to ensure enough time elapses
2596          * for read data to come back.
2597          */
2598         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2599
2600         if (test_dm) {
2601                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2602                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2603         } else {
2604                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2605                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2606         }
2607
2608         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2609         writel(mcc_instruction, addr + (group << 2));
2610 }
2611
2612 /* Test writes, can check for a single bit pass or multiple bit pass */
2613 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2614         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2615         uint32_t *bit_chk, uint32_t all_ranks)
2616 {
2617         uint32_t r;
2618         uint32_t correct_mask_vg;
2619         uint32_t tmp_bit_chk;
2620         uint32_t vg;
2621         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2622                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2623         uint32_t addr_rw_mgr;
2624         uint32_t base_rw_mgr;
2625
2626         *bit_chk = param->write_correct_mask;
2627         correct_mask_vg = param->write_correct_mask_vg;
2628
2629         for (r = rank_bgn; r < rank_end; r++) {
2630                 if (param->skip_ranks[r]) {
2631                         /* request to skip the rank */
2632                         continue;
2633                 }
2634
2635                 /* set rank */
2636                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2637
2638                 tmp_bit_chk = 0;
2639                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2640                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2641                         /* reset the fifos to get pointers to known state */
2642                         writel(0, &phy_mgr_cmd->fifo_reset);
2643
2644                         tmp_bit_chk = tmp_bit_chk <<
2645                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2646                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2647                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2648                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2649                                 use_dm);
2650
2651                         base_rw_mgr = readl(addr_rw_mgr);
2652                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2653                         if (vg == 0)
2654                                 break;
2655                 }
2656                 *bit_chk &= tmp_bit_chk;
2657         }
2658
2659         if (all_correct) {
2660                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2661                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2662                            %u => %lu", write_group, use_dm,
2663                            *bit_chk, param->write_correct_mask,
2664                            (long unsigned int)(*bit_chk ==
2665                            param->write_correct_mask));
2666                 return *bit_chk == param->write_correct_mask;
2667         } else {
2668                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2669                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2670                        write_group, use_dm, *bit_chk);
2671                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2672                         (long unsigned int)(*bit_chk != 0));
2673                 return *bit_chk != 0x00;
2674         }
2675 }
2676
2677 /*
2678  * center all windows. do per-bit-deskew to possibly increase size of
2679  * certain windows.
2680  */
2681 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2682         uint32_t write_group, uint32_t test_bgn)
2683 {
2684         uint32_t i, p, min_index;
2685         int32_t d;
2686         /*
2687          * Store these as signed since there are comparisons with
2688          * signed numbers.
2689          */
2690         uint32_t bit_chk;
2691         uint32_t sticky_bit_chk;
2692         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2693         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2694         int32_t mid;
2695         int32_t mid_min, orig_mid_min;
2696         int32_t new_dqs, start_dqs, shift_dq;
2697         int32_t dq_margin, dqs_margin, dm_margin;
2698         uint32_t stop;
2699         uint32_t temp_dq_out1_delay;
2700         uint32_t addr;
2701
2702         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2703
2704         dm_margin = 0;
2705
2706         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2707         start_dqs = readl(addr +
2708                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2709
2710         /* per-bit deskew */
2711
2712         /*
2713          * set the left and right edge of each bit to an illegal value
2714          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2715          */
2716         sticky_bit_chk = 0;
2717         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2718                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2719                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2720         }
2721
2722         /* Search for the left edge of the window for each bit */
2723         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2724                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2725
2726                 writel(0, &sdr_scc_mgr->update);
2727
2728                 /*
2729                  * Stop searching when the read test doesn't pass AND when
2730                  * we've seen a passing read on every bit.
2731                  */
2732                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2733                         0, PASS_ONE_BIT, &bit_chk, 0);
2734                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2735                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2736                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2737                            == %u && %u [bit_chk= %u ]\n",
2738                         d, sticky_bit_chk, param->write_correct_mask,
2739                         stop, bit_chk);
2740
2741                 if (stop == 1) {
2742                         break;
2743                 } else {
2744                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2745                                 if (bit_chk & 1) {
2746                                         /*
2747                                          * Remember a passing test as the
2748                                          * left_edge.
2749                                          */
2750                                         left_edge[i] = d;
2751                                 } else {
2752                                         /*
2753                                          * If a left edge has not been seen
2754                                          * yet, then a future passing test will
2755                                          * mark this edge as the right edge.
2756                                          */
2757                                         if (left_edge[i] ==
2758                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2759                                                 right_edge[i] = -(d + 1);
2760                                         }
2761                                 }
2762                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2763                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2764                                            (int)(bit_chk & 1), i, left_edge[i]);
2765                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2766                                        right_edge[i]);
2767                                 bit_chk = bit_chk >> 1;
2768                         }
2769                 }
2770         }
2771
2772         /* Reset DQ delay chains to 0 */
2773         scc_mgr_apply_group_dq_out1_delay(0);
2774         sticky_bit_chk = 0;
2775         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2776                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2777                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2778                            i, left_edge[i], i, right_edge[i]);
2779
2780                 /*
2781                  * Check for cases where we haven't found the left edge,
2782                  * which makes our assignment of the the right edge invalid.
2783                  * Reset it to the illegal value.
2784                  */
2785                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2786                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2787                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2788                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2789                                    right_edge[%u]: %d\n", __func__, __LINE__,
2790                                    i, right_edge[i]);
2791                 }
2792
2793                 /*
2794                  * Reset sticky bit (except for bits where we have
2795                  * seen the left edge).
2796                  */
2797                 sticky_bit_chk = sticky_bit_chk << 1;
2798                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2799                         sticky_bit_chk = sticky_bit_chk | 1;
2800
2801                 if (i == 0)
2802                         break;
2803         }
2804
2805         /* Search for the right edge of the window for each bit */
2806         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2807                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2808                                                         d + start_dqs);
2809
2810                 writel(0, &sdr_scc_mgr->update);
2811
2812                 /*
2813                  * Stop searching when the read test doesn't pass AND when
2814                  * we've seen a passing read on every bit.
2815                  */
2816                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2817                         0, PASS_ONE_BIT, &bit_chk, 0);
2818
2819                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2820                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2821
2822                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2823                            %u && %u\n", d, sticky_bit_chk,
2824                            param->write_correct_mask, stop);
2825
2826                 if (stop == 1) {
2827                         if (d == 0) {
2828                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2829                                         i++) {
2830                                         /* d = 0 failed, but it passed when
2831                                         testing the left edge, so it must be
2832                                         marginal, set it to -1 */
2833                                         if (right_edge[i] ==
2834                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2835                                                 left_edge[i] !=
2836                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2837                                                 right_edge[i] = -1;
2838                                         }
2839                                 }
2840                         }
2841                         break;
2842                 } else {
2843                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2844                                 if (bit_chk & 1) {
2845                                         /*
2846                                          * Remember a passing test as
2847                                          * the right_edge.
2848                                          */
2849                                         right_edge[i] = d;
2850                                 } else {
2851                                         if (d != 0) {
2852                                                 /*
2853                                                  * If a right edge has not
2854                                                  * been seen yet, then a future
2855                                                  * passing test will mark this
2856                                                  * edge as the left edge.
2857                                                  */
2858                                                 if (right_edge[i] ==
2859                                                     IO_IO_OUT1_DELAY_MAX + 1)
2860                                                         left_edge[i] = -(d + 1);
2861                                         } else {
2862                                                 /*
2863                                                  * d = 0 failed, but it passed
2864                                                  * when testing the left edge,
2865                                                  * so it must be marginal, set
2866                                                  * it to -1.
2867                                                  */
2868                                                 if (right_edge[i] ==
2869                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2870                                                     left_edge[i] !=
2871                                                     IO_IO_OUT1_DELAY_MAX + 1)
2872                                                         right_edge[i] = -1;
2873                                                 /*
2874                                                  * If a right edge has not been
2875                                                  * seen yet, then a future
2876                                                  * passing test will mark this
2877                                                  * edge as the left edge.
2878                                                  */
2879                                                 else if (right_edge[i] ==
2880                                                         IO_IO_OUT1_DELAY_MAX +
2881                                                         1)
2882                                                         left_edge[i] = -(d + 1);
2883                                         }
2884                                 }
2885                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2886                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2887                                            (int)(bit_chk & 1), i, left_edge[i]);
2888                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2889                                            right_edge[i]);
2890                                 bit_chk = bit_chk >> 1;
2891                         }
2892                 }
2893         }
2894
2895         /* Check that all bits have a window */
2896         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2897                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2898                            %d right_edge[%u]: %d", __func__, __LINE__,
2899                            i, left_edge[i], i, right_edge[i]);
2900                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2901                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2902                         set_failing_group_stage(test_bgn + i,
2903                                                 CAL_STAGE_WRITES,
2904                                                 CAL_SUBSTAGE_WRITES_CENTER);
2905                         return 0;
2906                 }
2907         }
2908
2909         /* Find middle of window for each DQ bit */
2910         mid_min = left_edge[0] - right_edge[0];
2911         min_index = 0;
2912         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2913                 mid = left_edge[i] - right_edge[i];
2914                 if (mid < mid_min) {
2915                         mid_min = mid;
2916                         min_index = i;
2917                 }
2918         }
2919
2920         /*
2921          * -mid_min/2 represents the amount that we need to move DQS.
2922          * If mid_min is odd and positive we'll need to add one to
2923          * make sure the rounding in further calculations is correct
2924          * (always bias to the right), so just add 1 for all positive values.
2925          */
2926         if (mid_min > 0)
2927                 mid_min++;
2928         mid_min = mid_min / 2;
2929         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2930                    __LINE__, mid_min);
2931
2932         /* Determine the amount we can change DQS (which is -mid_min) */
2933         orig_mid_min = mid_min;
2934         new_dqs = start_dqs;
2935         mid_min = 0;
2936         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2937                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2938         /* Initialize data for export structures */
2939         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2940         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2941
2942         /* add delay to bring centre of all DQ windows to the same "level" */
2943         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2944                 /* Use values before divide by 2 to reduce round off error */
2945                 shift_dq = (left_edge[i] - right_edge[i] -
2946                         (left_edge[min_index] - right_edge[min_index]))/2  +
2947                 (orig_mid_min - mid_min);
2948
2949                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2950                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2951
2952                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2953                 temp_dq_out1_delay = readl(addr + (i << 2));
2954                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2955                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2956                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2957                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2958                         shift_dq = -(int32_t)temp_dq_out1_delay;
2959                 }
2960                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2961                            i, shift_dq);
2962                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2963                 scc_mgr_load_dq(i);
2964
2965                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2966                            left_edge[i] - shift_dq + (-mid_min),
2967                            right_edge[i] + shift_dq - (-mid_min));
2968                 /* To determine values for export structures */
2969                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2970                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2971
2972                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2973                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2974         }
2975
2976         /* Move DQS */
2977         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2978         writel(0, &sdr_scc_mgr->update);
2979
2980         /* Centre DM */
2981         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2982
2983         /*
2984          * set the left and right edge of each bit to an illegal value,
2985          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2986          */
2987         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
2988         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2989         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2990         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2991         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2992         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2993         int32_t win_best = 0;
2994
2995         /* Search for the/part of the window with DM shift */
2996         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2997                 scc_mgr_apply_group_dm_out1_delay(d);
2998                 writel(0, &sdr_scc_mgr->update);
2999
3000                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3001                                                     PASS_ALL_BITS, &bit_chk,
3002                                                     0)) {
3003                         /* USE Set current end of the window */
3004                         end_curr = -d;
3005                         /*
3006                          * If a starting edge of our window has not been seen
3007                          * this is our current start of the DM window.
3008                          */
3009                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3010                                 bgn_curr = -d;
3011
3012                         /*
3013                          * If current window is bigger than best seen.
3014                          * Set best seen to be current window.
3015                          */
3016                         if ((end_curr-bgn_curr+1) > win_best) {
3017                                 win_best = end_curr-bgn_curr+1;
3018                                 bgn_best = bgn_curr;
3019                                 end_best = end_curr;
3020                         }
3021                 } else {
3022                         /* We just saw a failing test. Reset temp edge */
3023                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3024                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3025                         }
3026                 }
3027
3028
3029         /* Reset DM delay chains to 0 */
3030         scc_mgr_apply_group_dm_out1_delay(0);
3031
3032         /*
3033          * Check to see if the current window nudges up aganist 0 delay.
3034          * If so we need to continue the search by shifting DQS otherwise DQS
3035          * search begins as a new search. */
3036         if (end_curr != 0) {
3037                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3038                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3039         }
3040
3041         /* Search for the/part of the window with DQS shifts */
3042         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3043                 /*
3044                  * Note: This only shifts DQS, so are we limiting ourselve to
3045                  * width of DQ unnecessarily.
3046                  */
3047                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3048                                                         d + new_dqs);
3049
3050                 writel(0, &sdr_scc_mgr->update);
3051                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3052                                                     PASS_ALL_BITS, &bit_chk,
3053                                                     0)) {
3054                         /* USE Set current end of the window */
3055                         end_curr = d;
3056                         /*
3057                          * If a beginning edge of our window has not been seen
3058                          * this is our current begin of the DM window.
3059                          */
3060                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3061                                 bgn_curr = d;
3062
3063                         /*
3064                          * If current window is bigger than best seen. Set best
3065                          * seen to be current window.
3066                          */
3067                         if ((end_curr-bgn_curr+1) > win_best) {
3068                                 win_best = end_curr-bgn_curr+1;
3069                                 bgn_best = bgn_curr;
3070                                 end_best = end_curr;
3071                         }
3072                 } else {
3073                         /* We just saw a failing test. Reset temp edge */
3074                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3075                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3076
3077                         /* Early exit optimization: if ther remaining delay
3078                         chain space is less than already seen largest window
3079                         we can exit */
3080                         if ((win_best-1) >
3081                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3082                                         break;
3083                                 }
3084                         }
3085                 }
3086
3087         /* assign left and right edge for cal and reporting; */
3088         left_edge[0] = -1*bgn_best;
3089         right_edge[0] = end_best;
3090
3091         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3092                    __LINE__, left_edge[0], right_edge[0]);
3093
3094         /* Move DQS (back to orig) */
3095         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3096
3097         /* Move DM */
3098
3099         /* Find middle of window for the DM bit */
3100         mid = (left_edge[0] - right_edge[0]) / 2;
3101
3102         /* only move right, since we are not moving DQS/DQ */
3103         if (mid < 0)
3104                 mid = 0;
3105
3106         /* dm_marign should fail if we never find a window */
3107         if (win_best == 0)
3108                 dm_margin = -1;
3109         else
3110                 dm_margin = left_edge[0] - mid;
3111
3112         scc_mgr_apply_group_dm_out1_delay(mid);
3113         writel(0, &sdr_scc_mgr->update);
3114
3115         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3116                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3117                    right_edge[0], mid, dm_margin);
3118         /* Export values */
3119         gbl->fom_out += dq_margin + dqs_margin;
3120
3121         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3122                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3123                    dq_margin, dqs_margin, dm_margin);
3124
3125         /*
3126          * Do not remove this line as it makes sure all of our
3127          * decisions have been applied.
3128          */
3129         writel(0, &sdr_scc_mgr->update);
3130         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3131 }
3132
3133 /* calibrate the write operations */
3134 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3135         uint32_t test_bgn)
3136 {
3137         /* update info for sims */
3138         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3139
3140         reg_file_set_stage(CAL_STAGE_WRITES);
3141         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3142
3143         reg_file_set_group(g);
3144
3145         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3146                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3147                                         CAL_SUBSTAGE_WRITES_CENTER);
3148                 return 0;
3149         }
3150
3151         return 1;
3152 }
3153
3154 /**
3155  * mem_precharge_and_activate() - Precharge all banks and activate
3156  *
3157  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3158  */
3159 static void mem_precharge_and_activate(void)
3160 {
3161         int r;
3162
3163         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3164                 /* Test if the rank should be skipped. */
3165                 if (param->skip_ranks[r])
3166                         continue;
3167
3168                 /* Set rank. */
3169                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3170
3171                 /* Precharge all banks. */
3172                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3173                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3174
3175                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3176                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3177                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3178
3179                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3180                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3181                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3182
3183                 /* Activate rows. */
3184                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3185                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3186         }
3187 }
3188
3189 /**
3190  * mem_init_latency() - Configure memory RLAT and WLAT settings
3191  *
3192  * Configure memory RLAT and WLAT parameters.
3193  */
3194 static void mem_init_latency(void)
3195 {
3196         /*
3197          * For AV/CV, LFIFO is hardened and always runs at full rate
3198          * so max latency in AFI clocks, used here, is correspondingly
3199          * smaller.
3200          */
3201         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3202         u32 rlat, wlat;
3203
3204         debug("%s:%d\n", __func__, __LINE__);
3205
3206         /*
3207          * Read in write latency.
3208          * WL for Hard PHY does not include additive latency.
3209          */
3210         wlat = readl(&data_mgr->t_wl_add);
3211         wlat += readl(&data_mgr->mem_t_add);
3212
3213         gbl->rw_wl_nop_cycles = wlat - 1;
3214
3215         /* Read in readl latency. */
3216         rlat = readl(&data_mgr->t_rl_add);
3217
3218         /* Set a pretty high read latency initially. */
3219         gbl->curr_read_lat = rlat + 16;
3220         if (gbl->curr_read_lat > max_latency)
3221                 gbl->curr_read_lat = max_latency;
3222
3223         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3224
3225         /* Advertise write latency. */
3226         writel(wlat, &phy_mgr_cfg->afi_wlat);
3227 }
3228
3229 /**
3230  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3231  *
3232  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3233  */
3234 static void mem_skip_calibrate(void)
3235 {
3236         uint32_t vfifo_offset;
3237         uint32_t i, j, r;
3238
3239         debug("%s:%d\n", __func__, __LINE__);
3240         /* Need to update every shadow register set used by the interface */
3241         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3242              r += NUM_RANKS_PER_SHADOW_REG) {
3243                 /*
3244                  * Set output phase alignment settings appropriate for
3245                  * skip calibration.
3246                  */
3247                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3248                         scc_mgr_set_dqs_en_phase(i, 0);
3249 #if IO_DLL_CHAIN_LENGTH == 6
3250                         scc_mgr_set_dqdqs_output_phase(i, 6);
3251 #else
3252                         scc_mgr_set_dqdqs_output_phase(i, 7);
3253 #endif
3254                         /*
3255                          * Case:33398
3256                          *
3257                          * Write data arrives to the I/O two cycles before write
3258                          * latency is reached (720 deg).
3259                          *   -> due to bit-slip in a/c bus
3260                          *   -> to allow board skew where dqs is longer than ck
3261                          *      -> how often can this happen!?
3262                          *      -> can claim back some ptaps for high freq
3263                          *       support if we can relax this, but i digress...
3264                          *
3265                          * The write_clk leads mem_ck by 90 deg
3266                          * The minimum ptap of the OPA is 180 deg
3267                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3268                          * The write_clk is always delayed by 2 ptaps
3269                          *
3270                          * Hence, to make DQS aligned to CK, we need to delay
3271                          * DQS by:
3272                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3273                          *
3274                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3275                          * gives us the number of ptaps, which simplies to:
3276                          *
3277                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3278                          */
3279                         scc_mgr_set_dqdqs_output_phase(i,
3280                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3281                 }
3282                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3283                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3284
3285                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3286                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3287                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3288                 }
3289                 writel(0xff, &sdr_scc_mgr->dq_ena);
3290                 writel(0xff, &sdr_scc_mgr->dm_ena);
3291                 writel(0, &sdr_scc_mgr->update);
3292         }
3293
3294         /* Compensate for simulation model behaviour */
3295         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3296                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3297                 scc_mgr_load_dqs(i);
3298         }
3299         writel(0, &sdr_scc_mgr->update);
3300
3301         /*
3302          * ArriaV has hard FIFOs that can only be initialized by incrementing
3303          * in sequencer.
3304          */
3305         vfifo_offset = CALIB_VFIFO_OFFSET;
3306         for (j = 0; j < vfifo_offset; j++)
3307                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3308         writel(0, &phy_mgr_cmd->fifo_reset);
3309
3310         /*
3311          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3312          * setting from generation-time constant.
3313          */
3314         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3315         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3316 }
3317
3318 /**
3319  * mem_calibrate() - Memory calibration entry point.
3320  *
3321  * Perform memory calibration.
3322  */
3323 static uint32_t mem_calibrate(void)
3324 {
3325         uint32_t i;
3326         uint32_t rank_bgn, sr;
3327         uint32_t write_group, write_test_bgn;
3328         uint32_t read_group, read_test_bgn;
3329         uint32_t run_groups, current_run;
3330         uint32_t failing_groups = 0;
3331         uint32_t group_failed = 0;
3332
3333         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3334                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3335
3336         debug("%s:%d\n", __func__, __LINE__);
3337
3338         /* Initialize the data settings */
3339         gbl->error_substage = CAL_SUBSTAGE_NIL;
3340         gbl->error_stage = CAL_STAGE_NIL;
3341         gbl->error_group = 0xff;
3342         gbl->fom_in = 0;
3343         gbl->fom_out = 0;
3344
3345         /* Initialize WLAT and RLAT. */
3346         mem_init_latency();
3347
3348         /* Initialize bit slips. */
3349         mem_precharge_and_activate();
3350
3351         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3352                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3353                           SCC_MGR_GROUP_COUNTER_OFFSET);
3354                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3355                 if (i == 0)
3356                         scc_mgr_set_hhp_extras();
3357
3358                 scc_set_bypass_mode(i);
3359         }
3360
3361         /* Calibration is skipped. */
3362         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3363                 /*
3364                  * Set VFIFO and LFIFO to instant-on settings in skip
3365                  * calibration mode.
3366                  */
3367                 mem_skip_calibrate();
3368
3369                 /*
3370                  * Do not remove this line as it makes sure all of our
3371                  * decisions have been applied.
3372                  */
3373                 writel(0, &sdr_scc_mgr->update);
3374                 return 1;
3375         }
3376
3377         /* Calibration is not skipped. */
3378         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3379                 /*
3380                  * Zero all delay chain/phase settings for all
3381                  * groups and all shadow register sets.
3382                  */
3383                 scc_mgr_zero_all();
3384
3385                 run_groups = ~param->skip_groups;
3386
3387                 for (write_group = 0, write_test_bgn = 0; write_group
3388                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3389                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3390
3391                         /* Initialize the group failure */
3392                         group_failed = 0;
3393
3394                         current_run = run_groups & ((1 <<
3395                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3396                         run_groups = run_groups >>
3397                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3398
3399                         if (current_run == 0)
3400                                 continue;
3401
3402                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3403                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3404                         scc_mgr_zero_group(write_group, 0);
3405
3406                         for (read_group = write_group * rwdqs_ratio,
3407                              read_test_bgn = 0;
3408                              read_group < (write_group + 1) * rwdqs_ratio;
3409                              read_group++,
3410                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3411                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3412                                         continue;
3413
3414                                 /* Calibrate the VFIFO */
3415                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3416                                                                read_test_bgn))
3417                                         continue;
3418
3419                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3420                                         return 0;
3421
3422                                 /* The group failed, we're done. */
3423                                 goto grp_failed;
3424                         }
3425
3426                         /* Calibrate the output side */
3427                         for (rank_bgn = 0, sr = 0;
3428                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3429                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3430                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3431                                         continue;
3432
3433                                 /* Not needed in quick mode! */
3434                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3435                                         continue;
3436
3437                                 /*
3438                                  * Determine if this set of ranks
3439                                  * should be skipped entirely.
3440                                  */
3441                                 if (param->skip_shadow_regs[sr])
3442                                         continue;
3443
3444                                 /* Calibrate WRITEs */
3445                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3446                                                 write_group, write_test_bgn))
3447                                         continue;
3448
3449                                 group_failed = 1;
3450                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3451                                         return 0;
3452                         }
3453
3454                         /* Some group failed, we're done. */
3455                         if (group_failed)
3456                                 goto grp_failed;
3457
3458                         for (read_group = write_group * rwdqs_ratio,
3459                              read_test_bgn = 0;
3460                              read_group < (write_group + 1) * rwdqs_ratio;
3461                              read_group++,
3462                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3463                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3464                                         continue;
3465
3466                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3467                                                                 read_test_bgn))
3468                                         continue;
3469
3470                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3471                                         return 0;
3472
3473                                 /* The group failed, we're done. */
3474                                 goto grp_failed;
3475                         }
3476
3477                         /* No group failed, continue as usual. */
3478                         continue;
3479
3480 grp_failed:             /* A group failed, increment the counter. */
3481                         failing_groups++;
3482                 }
3483
3484                 /*
3485                  * USER If there are any failing groups then report
3486                  * the failure.
3487                  */
3488                 if (failing_groups != 0)
3489                         return 0;
3490
3491                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3492                         continue;
3493
3494                 /*
3495                  * If we're skipping groups as part of debug,
3496                  * don't calibrate LFIFO.
3497                  */
3498                 if (param->skip_groups != 0)
3499                         continue;
3500
3501                 /* Calibrate the LFIFO */
3502                 if (!rw_mgr_mem_calibrate_lfifo())
3503                         return 0;
3504         }
3505
3506         /*
3507          * Do not remove this line as it makes sure all of our decisions
3508          * have been applied.
3509          */
3510         writel(0, &sdr_scc_mgr->update);
3511         return 1;
3512 }
3513
3514 /**
3515  * run_mem_calibrate() - Perform memory calibration
3516  *
3517  * This function triggers the entire memory calibration procedure.
3518  */
3519 static int run_mem_calibrate(void)
3520 {
3521         int pass;
3522
3523         debug("%s:%d\n", __func__, __LINE__);
3524
3525         /* Reset pass/fail status shown on afi_cal_success/fail */
3526         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3527
3528         /* Stop tracking manager. */
3529         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3530
3531         phy_mgr_initialize();
3532         rw_mgr_mem_initialize();
3533
3534         /* Perform the actual memory calibration. */
3535         pass = mem_calibrate();
3536
3537         mem_precharge_and_activate();
3538         writel(0, &phy_mgr_cmd->fifo_reset);
3539
3540         /* Handoff. */
3541         rw_mgr_mem_handoff();
3542         /*
3543          * In Hard PHY this is a 2-bit control:
3544          * 0: AFI Mux Select
3545          * 1: DDIO Mux Select
3546          */
3547         writel(0x2, &phy_mgr_cfg->mux_sel);
3548
3549         /* Start tracking manager. */
3550         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3551
3552         return pass;
3553 }
3554
3555 /**
3556  * debug_mem_calibrate() - Report result of memory calibration
3557  * @pass:       Value indicating whether calibration passed or failed
3558  *
3559  * This function reports the results of the memory calibration
3560  * and writes debug information into the register file.
3561  */
3562 static void debug_mem_calibrate(int pass)
3563 {
3564         uint32_t debug_info;
3565
3566         if (pass) {
3567                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3568
3569                 gbl->fom_in /= 2;
3570                 gbl->fom_out /= 2;
3571
3572                 if (gbl->fom_in > 0xff)
3573                         gbl->fom_in = 0xff;
3574
3575                 if (gbl->fom_out > 0xff)
3576                         gbl->fom_out = 0xff;
3577
3578                 /* Update the FOM in the register file */
3579                 debug_info = gbl->fom_in;
3580                 debug_info |= gbl->fom_out << 8;
3581                 writel(debug_info, &sdr_reg_file->fom);
3582
3583                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3584                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3585         } else {
3586                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3587
3588                 debug_info = gbl->error_stage;
3589                 debug_info |= gbl->error_substage << 8;
3590                 debug_info |= gbl->error_group << 16;
3591
3592                 writel(debug_info, &sdr_reg_file->failing_stage);
3593                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3594                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3595
3596                 /* Update the failing group/stage in the register file */
3597                 debug_info = gbl->error_stage;
3598                 debug_info |= gbl->error_substage << 8;
3599                 debug_info |= gbl->error_group << 16;
3600                 writel(debug_info, &sdr_reg_file->failing_stage);
3601         }
3602
3603         printf("%s: Calibration complete\n", __FILE__);
3604 }
3605
3606 /**
3607  * hc_initialize_rom_data() - Initialize ROM data
3608  *
3609  * Initialize ROM data.
3610  */
3611 static void hc_initialize_rom_data(void)
3612 {
3613         u32 i, addr;
3614
3615         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3616         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3617                 writel(inst_rom_init[i], addr + (i << 2));
3618
3619         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3620         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3621                 writel(ac_rom_init[i], addr + (i << 2));
3622 }
3623
3624 /**
3625  * initialize_reg_file() - Initialize SDR register file
3626  *
3627  * Initialize SDR register file.
3628  */
3629 static void initialize_reg_file(void)
3630 {
3631         /* Initialize the register file with the correct data */
3632         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3633         writel(0, &sdr_reg_file->debug_data_addr);
3634         writel(0, &sdr_reg_file->cur_stage);
3635         writel(0, &sdr_reg_file->fom);
3636         writel(0, &sdr_reg_file->failing_stage);
3637         writel(0, &sdr_reg_file->debug1);
3638         writel(0, &sdr_reg_file->debug2);
3639 }
3640
3641 /**
3642  * initialize_hps_phy() - Initialize HPS PHY
3643  *
3644  * Initialize HPS PHY.
3645  */
3646 static void initialize_hps_phy(void)
3647 {
3648         uint32_t reg;
3649         /*
3650          * Tracking also gets configured here because it's in the
3651          * same register.
3652          */
3653         uint32_t trk_sample_count = 7500;
3654         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3655         /*
3656          * Format is number of outer loops in the 16 MSB, sample
3657          * count in 16 LSB.
3658          */
3659
3660         reg = 0;
3661         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3662         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3663         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3664         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3665         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3666         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3667         /*
3668          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3669          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3670          */
3671         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3672         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3673                 trk_sample_count);
3674         writel(reg, &sdr_ctrl->phy_ctrl0);
3675
3676         reg = 0;
3677         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3678                 trk_sample_count >>
3679                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3680         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3681                 trk_long_idle_sample_count);
3682         writel(reg, &sdr_ctrl->phy_ctrl1);
3683
3684         reg = 0;
3685         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3686                 trk_long_idle_sample_count >>
3687                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3688         writel(reg, &sdr_ctrl->phy_ctrl2);
3689 }
3690
3691 /**
3692  * initialize_tracking() - Initialize tracking
3693  *
3694  * Initialize the register file with usable initial data.
3695  */
3696 static void initialize_tracking(void)
3697 {
3698         /*
3699          * Initialize the register file with the correct data.
3700          * Compute usable version of value in case we skip full
3701          * computation later.
3702          */
3703         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3704                &sdr_reg_file->dtaps_per_ptap);
3705
3706         /* trk_sample_count */
3707         writel(7500, &sdr_reg_file->trk_sample_count);
3708
3709         /* longidle outer loop [15:0] */
3710         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3711
3712         /*
3713          * longidle sample count [31:24]
3714          * trfc, worst case of 933Mhz 4Gb [23:16]
3715          * trcd, worst case [15:8]
3716          * vfifo wait [7:0]
3717          */
3718         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3719                &sdr_reg_file->delays);
3720
3721         /* mux delay */
3722         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3723                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3724                &sdr_reg_file->trk_rw_mgr_addr);
3725
3726         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3727                &sdr_reg_file->trk_read_dqs_width);
3728
3729         /* trefi [7:0] */
3730         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3731                &sdr_reg_file->trk_rfsh);
3732 }
3733
3734 int sdram_calibration_full(void)
3735 {
3736         struct param_type my_param;
3737         struct gbl_type my_gbl;
3738         uint32_t pass;
3739
3740         memset(&my_param, 0, sizeof(my_param));
3741         memset(&my_gbl, 0, sizeof(my_gbl));
3742
3743         param = &my_param;
3744         gbl = &my_gbl;
3745
3746         /* Set the calibration enabled by default */
3747         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3748         /*
3749          * Only sweep all groups (regardless of fail state) by default
3750          * Set enabled read test by default.
3751          */
3752 #if DISABLE_GUARANTEED_READ
3753         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3754 #endif
3755         /* Initialize the register file */
3756         initialize_reg_file();
3757
3758         /* Initialize any PHY CSR */
3759         initialize_hps_phy();
3760
3761         scc_mgr_initialize();
3762
3763         initialize_tracking();
3764
3765         printf("%s: Preparing to start memory calibration\n", __FILE__);
3766
3767         debug("%s:%d\n", __func__, __LINE__);
3768         debug_cond(DLEVEL == 1,
3769                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3770                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3771                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3772                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3773                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3774         debug_cond(DLEVEL == 1,
3775                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3776                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3777                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3778                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3779         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3780                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3781         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3782                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3783                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3784         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3785                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3786                    IO_IO_OUT2_DELAY_MAX);
3787         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3788                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3789
3790         hc_initialize_rom_data();
3791
3792         /* update info for sims */
3793         reg_file_set_stage(CAL_STAGE_NIL);
3794         reg_file_set_group(0);
3795
3796         /*
3797          * Load global needed for those actions that require
3798          * some dynamic calibration support.
3799          */
3800         dyn_calib_steps = STATIC_CALIB_STEPS;
3801         /*
3802          * Load global to allow dynamic selection of delay loop settings
3803          * based on calibration mode.
3804          */
3805         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3806                 skip_delay_mask = 0xff;
3807         else
3808                 skip_delay_mask = 0x0;
3809
3810         pass = run_mem_calibrate();
3811         debug_mem_calibrate(pass);
3812         return pass;
3813 }