2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
12 #include "sequencer_auto.h"
13 #include "sequencer_auto_ac_init.h"
14 #include "sequencer_auto_inst_init.h"
15 #include "sequencer_defines.h"
17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
18 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
21 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
23 static struct socfpga_sdr_reg_file *sdr_reg_file =
24 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
27 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
30 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
33 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
35 static struct socfpga_data_mgr *data_mgr =
36 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
38 static struct socfpga_sdr_ctrl *sdr_ctrl =
39 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
44 * In order to reduce ROM size, most of the selectable calibration steps are
45 * decided at compile time based on the user's calibration mode selection,
46 * as captured by the STATIC_CALIB_STEPS selection below.
48 * However, to support simulation-time selection of fast simulation mode, where
49 * we skip everything except the bare minimum, we need a few of the steps to
50 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
51 * check, which is based on the rtl-supplied value, or we dynamically compute
52 * the value to use based on the dynamically-chosen calibration mode
56 #define STATIC_IN_RTL_SIM 0
57 #define STATIC_SKIP_DELAY_LOOPS 0
59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
60 STATIC_SKIP_DELAY_LOOPS)
62 /* calibration steps requested by the rtl */
63 uint16_t dyn_calib_steps;
66 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
67 * instead of static, we use boolean logic to select between
68 * non-skip and skip values
70 * The mask is set to include all bits when not-skipping, but is
74 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
77 ((non_skip_value) & skip_delay_mask)
80 struct param_type *param;
81 uint32_t curr_shadow_reg;
83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
84 uint32_t write_group, uint32_t use_dm,
85 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
91 * Only set the global stage if there was not been any other
94 if (gbl->error_stage == CAL_STAGE_NIL) {
95 gbl->error_substage = substage;
96 gbl->error_stage = stage;
97 gbl->error_group = group;
101 static void reg_file_set_group(u16 set_group)
103 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
106 static void reg_file_set_stage(u8 set_stage)
108 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
111 static void reg_file_set_sub_stage(u8 set_sub_stage)
113 set_sub_stage &= 0xff;
114 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
118 * phy_mgr_initialize() - Initialize PHY Manager
120 * Initialize PHY Manager.
122 static void phy_mgr_initialize(void)
126 debug("%s:%d\n", __func__, __LINE__);
127 /* Calibration has control over path to memory */
129 * In Hard PHY this is a 2-bit control:
133 writel(0x3, &phy_mgr_cfg->mux_sel);
135 /* USER memory clock is not stable we begin initialization */
136 writel(0, &phy_mgr_cfg->reset_mem_stbl);
138 /* USER calibration status all set to zero */
139 writel(0, &phy_mgr_cfg->cal_status);
141 writel(0, &phy_mgr_cfg->cal_debug_info);
143 /* Init params only if we do NOT skip calibration. */
144 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
147 ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
148 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
149 param->read_correct_mask_vg = (1 << ratio) - 1;
150 param->write_correct_mask_vg = (1 << ratio) - 1;
151 param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
152 param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
153 ratio = RW_MGR_MEM_DATA_WIDTH /
154 RW_MGR_MEM_DATA_MASK_WIDTH;
155 param->dm_correct_mask = (1 << ratio) - 1;
159 * set_rank_and_odt_mask() - Set Rank and ODT mask
161 * @odt_mode: ODT mode, OFF or READ_WRITE
163 * Set Rank and ODT mask (On-Die Termination).
165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
171 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
174 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
175 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
177 /* Read: ODT = 0 ; Write: ODT = 1 */
181 case 2: /* 2 Ranks */
182 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
184 * - Dual-Slot , Single-Rank (1 CS per DIMM)
186 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
188 * Since MEM_NUMBER_OF_RANKS is 2, they
189 * are both single rank with 2 CS each
190 * (special for RDIMM).
192 * Read: Turn on ODT on the opposite rank
193 * Write: Turn on ODT on all ranks
195 odt_mask_0 = 0x3 & ~(1 << rank);
199 * - Single-Slot , Dual-Rank (2 CS per DIMM)
201 * Read: Turn on ODT off on all ranks
202 * Write: Turn on ODT on active rank
205 odt_mask_1 = 0x3 & (1 << rank);
208 case 4: /* 4 Ranks */
210 * ----------+-----------------------+
212 * Read From +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 0 |
216 * 1 | 1 | 0 | 0 | 0 |
217 * 2 | 0 | 0 | 0 | 1 |
218 * 3 | 0 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
222 * ----------+-----------------------+
224 * Write To +-----------------------+
225 * Rank | 3 | 2 | 1 | 0 |
226 * ----------+-----+-----+-----+-----+
227 * 0 | 0 | 1 | 0 | 1 |
228 * 1 | 1 | 0 | 1 | 0 |
229 * 2 | 0 | 1 | 0 | 1 |
230 * 3 | 1 | 0 | 1 | 0 |
231 * ----------+-----+-----+-----+-----+
255 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
256 ((0xFF & odt_mask_0) << 8) |
257 ((0xFF & odt_mask_1) << 16);
258 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
259 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
263 * scc_mgr_set() - Set SCC Manager register
264 * @off: Base offset in SCC Manager space
265 * @grp: Read/Write group
266 * @val: Value to be set
268 * This function sets the SCC Manager (Scan Chain Control Manager) register.
270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
272 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
276 * scc_mgr_initialize() - Initialize SCC Manager registers
278 * Initialize SCC Manager registers.
280 static void scc_mgr_initialize(void)
283 * Clear register file for HPS. 16 (2^4) is the size of the
284 * full register file in the scc mgr:
285 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
286 * MEM_IF_READ_DQS_WIDTH - 1);
290 for (i = 0; i < 16; i++) {
291 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
292 __func__, __LINE__, i);
293 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
299 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
304 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
309 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
314 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
325 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
330 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
335 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
341 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
342 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
346 /* load up dqs config settings */
347 static void scc_mgr_load_dqs(uint32_t dqs)
349 writel(dqs, &sdr_scc_mgr->dqs_ena);
352 /* load up dqs io config settings */
353 static void scc_mgr_load_dqs_io(void)
355 writel(0, &sdr_scc_mgr->dqs_io_ena);
358 /* load up dq config settings */
359 static void scc_mgr_load_dq(uint32_t dq_in_group)
361 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
364 /* load up dm config settings */
365 static void scc_mgr_load_dm(uint32_t dm)
367 writel(dm, &sdr_scc_mgr->dm_ena);
371 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
372 * @off: Base offset in SCC Manager space
373 * @grp: Read/Write group
374 * @val: Value to be set
375 * @update: If non-zero, trigger SCC Manager update for all ranks
377 * This function sets the SCC Manager (Scan Chain Control Manager) register
378 * and optionally triggers the SCC update for all ranks.
380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
385 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
386 r += NUM_RANKS_PER_SHADOW_REG) {
387 scc_mgr_set(off, grp, val);
389 if (update || (r == 0)) {
390 writel(grp, &sdr_scc_mgr->dqs_ena);
391 writel(0, &sdr_scc_mgr->update);
396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
399 * USER although the h/w doesn't support different phases per
400 * shadow register, for simplicity our scc manager modeling
401 * keeps different phase settings per shadow reg, and it's
402 * important for us to keep them in sync to match h/w.
403 * for efficiency, the scan chain update should occur only
406 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
407 read_group, phase, 0);
410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
414 * USER although the h/w doesn't support different phases per
415 * shadow register, for simplicity our scc manager modeling
416 * keeps different phase settings per shadow reg, and it's
417 * important for us to keep them in sync to match h/w.
418 * for efficiency, the scan chain update should occur only
421 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
422 write_group, phase, 0);
425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
429 * In shadow register mode, the T11 settings are stored in
430 * registers in the core, which are updated by the DQS_ENA
431 * signals. Not issuing the SCC_MGR_UPD command allows us to
432 * save lots of rank switching overhead, by calling
433 * select_shadow_regs_for_update with update_scan_chains
436 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
437 read_group, delay, 1);
438 writel(0, &sdr_scc_mgr->update);
442 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
443 * @write_group: Write group
444 * @delay: Delay value
446 * This function sets the OCT output delay in SCC manager.
448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
450 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
451 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
452 const int base = write_group * ratio;
455 * Load the setting in the SCC manager
456 * Although OCT affects only write data, the OCT delay is controlled
457 * by the DQS logic block which is instantiated once per read group.
458 * For protocols where a write group consists of multiple read groups,
459 * the setting must be set multiple times.
461 for (i = 0; i < ratio; i++)
462 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
466 * scc_mgr_set_hhp_extras() - Set HHP extras.
468 * Load the fixed setting in the SCC manager HHP extras.
470 static void scc_mgr_set_hhp_extras(void)
473 * Load the fixed setting in the SCC manager
474 * bits: 0:0 = 1'b1 - DQS bypass
475 * bits: 1:1 = 1'b1 - DQ bypass
476 * bits: 4:2 = 3'b001 - rfifo_mode
477 * bits: 6:5 = 2'b01 - rfifo clock_select
478 * bits: 7:7 = 1'b0 - separate gating from ungating setting
479 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
481 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
482 (1 << 2) | (1 << 1) | (1 << 0);
483 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
484 SCC_MGR_HHP_GLOBALS_OFFSET |
485 SCC_MGR_HHP_EXTRAS_OFFSET;
487 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
490 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
495 * scc_mgr_zero_all() - Zero all DQS config
497 * Zero all DQS config.
499 static void scc_mgr_zero_all(void)
504 * USER Zero all DQS config settings, across all groups and all
507 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
508 r += NUM_RANKS_PER_SHADOW_REG) {
509 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
511 * The phases actually don't exist on a per-rank basis,
512 * but there's no harm updating them several times, so
513 * let's keep the code simple.
515 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
516 scc_mgr_set_dqs_en_phase(i, 0);
517 scc_mgr_set_dqs_en_delay(i, 0);
520 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
521 scc_mgr_set_dqdqs_output_phase(i, 0);
522 /* Arria V/Cyclone V don't have out2. */
523 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
527 /* Multicast to all DQS group enables. */
528 writel(0xff, &sdr_scc_mgr->dqs_ena);
529 writel(0, &sdr_scc_mgr->update);
533 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
534 * @write_group: Write group
536 * Set bypass mode and trigger SCC update.
538 static void scc_set_bypass_mode(const u32 write_group)
540 /* Multicast to all DQ enables. */
541 writel(0xff, &sdr_scc_mgr->dq_ena);
542 writel(0xff, &sdr_scc_mgr->dm_ena);
544 /* Update current DQS IO enable. */
545 writel(0, &sdr_scc_mgr->dqs_io_ena);
547 /* Update the DQS logic. */
548 writel(write_group, &sdr_scc_mgr->dqs_ena);
551 writel(0, &sdr_scc_mgr->update);
555 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
556 * @write_group: Write group
558 * Load DQS settings for Write Group, do not trigger SCC update.
560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
562 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
563 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
564 const int base = write_group * ratio;
567 * Load the setting in the SCC manager
568 * Although OCT affects only write data, the OCT delay is controlled
569 * by the DQS logic block which is instantiated once per read group.
570 * For protocols where a write group consists of multiple read groups,
571 * the setting must be set multiple times.
573 for (i = 0; i < ratio; i++)
574 writel(base + i, &sdr_scc_mgr->dqs_ena);
578 * scc_mgr_zero_group() - Zero all configs for a group
580 * Zero DQ, DM, DQS and OCT configs for a group.
582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
586 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
587 r += NUM_RANKS_PER_SHADOW_REG) {
588 /* Zero all DQ config settings. */
589 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
590 scc_mgr_set_dq_out1_delay(i, 0);
592 scc_mgr_set_dq_in_delay(i, 0);
595 /* Multicast to all DQ enables. */
596 writel(0xff, &sdr_scc_mgr->dq_ena);
598 /* Zero all DM config settings. */
599 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
600 scc_mgr_set_dm_out1_delay(i, 0);
602 /* Multicast to all DM enables. */
603 writel(0xff, &sdr_scc_mgr->dm_ena);
605 /* Zero all DQS IO settings. */
607 scc_mgr_set_dqs_io_in_delay(0);
609 /* Arria V/Cyclone V don't have out2. */
610 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
611 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
612 scc_mgr_load_dqs_for_write_group(write_group);
614 /* Multicast to all DQS IO enables (only 1 in total). */
615 writel(0, &sdr_scc_mgr->dqs_io_ena);
617 /* Hit update to zero everything. */
618 writel(0, &sdr_scc_mgr->update);
623 * apply and load a particular input delay for the DQ pins in a group
624 * group_bgn is the index of the first dq pin (in the write group)
626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
630 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
631 scc_mgr_set_dq_in_delay(p, delay);
637 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
638 * @delay: Delay value
640 * Apply and load a particular output delay for the DQ pins in a group.
642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
646 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
647 scc_mgr_set_dq_out1_delay(i, delay);
652 /* apply and load a particular output delay for the DM pins in a group */
653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
657 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
658 scc_mgr_set_dm_out1_delay(i, delay1);
664 /* apply and load delay on both DQS and OCT out1 */
665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
668 scc_mgr_set_dqs_out1_delay(delay);
669 scc_mgr_load_dqs_io();
671 scc_mgr_set_oct_out1_delay(write_group, delay);
672 scc_mgr_load_dqs_for_write_group(write_group);
676 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
677 * @write_group: Write group
678 * @delay: Delay value
680 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
688 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
692 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
696 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
697 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
698 debug_cond(DLEVEL == 1,
699 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
700 __func__, __LINE__, write_group, delay, new_delay,
701 IO_IO_OUT2_DELAY_MAX,
702 new_delay - IO_IO_OUT2_DELAY_MAX);
703 new_delay -= IO_IO_OUT2_DELAY_MAX;
704 scc_mgr_set_dqs_out1_delay(new_delay);
707 scc_mgr_load_dqs_io();
710 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
711 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
712 debug_cond(DLEVEL == 1,
713 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
714 __func__, __LINE__, write_group, delay,
715 new_delay, IO_IO_OUT2_DELAY_MAX,
716 new_delay - IO_IO_OUT2_DELAY_MAX);
717 new_delay -= IO_IO_OUT2_DELAY_MAX;
718 scc_mgr_set_oct_out1_delay(write_group, new_delay);
721 scc_mgr_load_dqs_for_write_group(write_group);
725 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
726 * @write_group: Write group
727 * @delay: Delay value
729 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
737 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
738 r += NUM_RANKS_PER_SHADOW_REG) {
739 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
740 writel(0, &sdr_scc_mgr->update);
745 * set_jump_as_return() - Return instruction optimization
747 * Optimization used to recover some slots in ddr3 inst_rom could be
748 * applied to other protocols if we wanted to
750 static void set_jump_as_return(void)
753 * To save space, we replace return with jump to special shared
754 * RETURN instruction so we set the counter to large value so that
757 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
758 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
762 * should always use constants as argument to ensure all computations are
763 * performed at compile time
765 static void delay_for_n_mem_clocks(const uint32_t clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
775 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
776 /* scale (rounding up) to get afi clocks */
779 * Note, we don't bother accounting for being off a little bit
780 * because of a few extra instructions in outer loops
781 * Note, the loops have a test at the end, and do the test before
782 * the decrement, and so always perform the loop
783 * 1 time more than the counter value
785 if (afi_clocks == 0) {
787 } else if (afi_clocks <= 0x100) {
788 inner = afi_clocks-1;
791 } else if (afi_clocks <= 0x10000) {
793 outer = (afi_clocks-1) >> 8;
798 c_loop = (afi_clocks-1) >> 16;
802 * rom instructions are structured as follows:
804 * IDLE_LOOP2: jnz cntr0, TARGET_A
805 * IDLE_LOOP1: jnz cntr1, TARGET_B
808 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
809 * TARGET_B is set to IDLE_LOOP2 as well
811 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
812 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
814 * a little confusing, but it helps save precious space in the inst_rom
815 * and sequencer rom and keeps the delays more accurate and reduces
818 if (afi_clocks <= 0x100) {
819 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
820 &sdr_rw_load_mgr_regs->load_cntr1);
822 writel(RW_MGR_IDLE_LOOP1,
823 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
825 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
826 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
828 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
829 &sdr_rw_load_mgr_regs->load_cntr0);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
832 &sdr_rw_load_mgr_regs->load_cntr1);
834 writel(RW_MGR_IDLE_LOOP2,
835 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
840 /* hack to get around compiler not being smart enough */
841 if (afi_clocks <= 0x10000) {
842 /* only need to run once */
843 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
844 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
847 writel(RW_MGR_IDLE_LOOP2,
848 SDR_PHYGRP_RWMGRGRP_ADDRESS |
849 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 } while (c_loop-- != 0);
853 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
857 * rw_mgr_mem_init_load_regs() - Load instruction registers
858 * @cntr0: Counter 0 value
859 * @cntr1: Counter 1 value
860 * @cntr2: Counter 2 value
861 * @jump: Jump instruction value
863 * Load instruction registers.
865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
867 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
868 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
871 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
872 &sdr_rw_load_mgr_regs->load_cntr0);
873 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
874 &sdr_rw_load_mgr_regs->load_cntr1);
875 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
876 &sdr_rw_load_mgr_regs->load_cntr2);
878 /* Load jump address */
879 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
880 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
881 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
883 /* Execute count instruction */
884 writel(jump, grpaddr);
888 * rw_mgr_mem_load_user() - Load user calibration values
889 * @fin1: Final instruction 1
890 * @fin2: Final instruction 2
891 * @precharge: If 1, precharge the banks at the end
893 * Load user calibration values and optionally precharge the banks.
895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
898 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
899 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
902 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
903 if (param->skip_ranks[r]) {
904 /* request to skip the rank */
909 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
911 /* precharge all banks ... */
913 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
916 * USER Use Mirror-ed commands for odd ranks if address
919 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
920 set_jump_as_return();
921 writel(RW_MGR_MRS2_MIRR, grpaddr);
922 delay_for_n_mem_clocks(4);
923 set_jump_as_return();
924 writel(RW_MGR_MRS3_MIRR, grpaddr);
925 delay_for_n_mem_clocks(4);
926 set_jump_as_return();
927 writel(RW_MGR_MRS1_MIRR, grpaddr);
928 delay_for_n_mem_clocks(4);
929 set_jump_as_return();
930 writel(fin1, grpaddr);
932 set_jump_as_return();
933 writel(RW_MGR_MRS2, grpaddr);
934 delay_for_n_mem_clocks(4);
935 set_jump_as_return();
936 writel(RW_MGR_MRS3, grpaddr);
937 delay_for_n_mem_clocks(4);
938 set_jump_as_return();
939 writel(RW_MGR_MRS1, grpaddr);
940 set_jump_as_return();
941 writel(fin2, grpaddr);
947 set_jump_as_return();
948 writel(RW_MGR_ZQCL, grpaddr);
950 /* tZQinit = tDLLK = 512 ck cycles */
951 delay_for_n_mem_clocks(512);
956 * rw_mgr_mem_initialize() - Initialize RW Manager
958 * Initialize RW Manager.
960 static void rw_mgr_mem_initialize(void)
962 debug("%s:%d\n", __func__, __LINE__);
964 /* The reset / cke part of initialization is broadcasted to all ranks */
965 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
966 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
969 * Here's how you load register for a loop
970 * Counters are located @ 0x800
971 * Jump address are located @ 0xC00
972 * For both, registers 0 to 3 are selected using bits 3 and 2, like
973 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
974 * I know this ain't pretty, but Avalon bus throws away the 2 least
978 /* Start with memory RESET activated */
983 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
984 * If a and b are the number of iteration in 2 nested loops
985 * it takes the following number of cycles to complete the operation:
986 * number_of_cycles = ((2 + n) * a + 2) * b
987 * where n is the number of instruction in the inner loop
988 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
991 rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
993 RW_MGR_INIT_RESET_0_CKE_0);
995 /* Indicate that memory is stable. */
996 writel(1, &phy_mgr_cfg->reset_mem_stbl);
999 * transition the RESET to high
1004 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005 * If a and b are the number of iteration in 2 nested loops
1006 * it takes the following number of cycles to complete the operation
1007 * number_of_cycles = ((2 + n) * a + 2) * b
1008 * where n is the number of instruction in the inner loop
1009 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1012 rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013 SEQ_TRESET_CNTR2_VAL,
1014 RW_MGR_INIT_RESET_1_CKE_0);
1016 /* Bring up clock enable. */
1018 /* tXRP < 250 ck cycles */
1019 delay_for_n_mem_clocks(250);
1021 rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1026 * At the end of calibration we have to program the user settings in, and
1027 * USER hand off the memory to the user.
1029 static void rw_mgr_mem_handoff(void)
1031 rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1033 * USER need to wait tMOD (12CK or 15ns) time before issuing
1034 * other commands, but we will have plenty of NIOS cycles before
1035 * actual handoff so its okay.
1040 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041 * @rank_bgn: Rank number
1042 * @group: Read/Write Group
1043 * @all_ranks: Test all ranks
1045 * Performs a guaranteed read on the patterns we are going to use during a
1046 * read test to ensure memory works.
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050 const u32 all_ranks)
1052 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054 const u32 addr_offset =
1055 (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056 const u32 rank_end = all_ranks ?
1057 RW_MGR_MEM_NUMBER_OF_RANKS :
1058 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059 const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061 const u32 correct_mask_vg = param->read_correct_mask_vg;
1063 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1067 bit_chk = param->read_correct_mask;
1069 for (r = rank_bgn; r < rank_end; r++) {
1070 /* Request to skip the rank */
1071 if (param->skip_ranks[r])
1075 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1077 /* Load up a constant bursts of read commands */
1078 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079 writel(RW_MGR_GUARANTEED_READ,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1082 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083 writel(RW_MGR_GUARANTEED_READ_CONT,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1087 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1089 /* Reset the FIFOs to get pointers to known state. */
1090 writel(0, &phy_mgr_cmd->fifo_reset);
1091 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093 writel(RW_MGR_GUARANTEED_READ,
1094 addr + addr_offset + (vg << 2));
1096 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097 tmp_bit_chk <<= shift_ratio;
1098 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1101 bit_chk &= tmp_bit_chk;
1104 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1106 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1108 if (bit_chk != param->read_correct_mask)
1111 debug_cond(DLEVEL == 1,
1112 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113 __func__, __LINE__, group, bit_chk,
1114 param->read_correct_mask, ret);
1120 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121 * @rank_bgn: Rank number
1122 * @all_ranks: Test all ranks
1124 * Load up the patterns we are going to use during a read test.
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127 const int all_ranks)
1129 const u32 rank_end = all_ranks ?
1130 RW_MGR_MEM_NUMBER_OF_RANKS :
1131 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1134 debug("%s:%d\n", __func__, __LINE__);
1136 for (r = rank_bgn; r < rank_end; r++) {
1137 if (param->skip_ranks[r])
1138 /* request to skip the rank */
1142 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1144 /* Load up a constant bursts */
1145 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1147 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1150 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1152 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1157 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1160 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1162 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1165 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1169 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1173 * try a read and see if it returns correct data back. has dummy reads
1174 * inserted into the mix used to align dqs enable. has more thorough checks
1175 * than the regular read test.
1177 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1178 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1179 uint32_t all_groups, uint32_t all_ranks)
1182 uint32_t correct_mask_vg;
1183 uint32_t tmp_bit_chk;
1184 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1185 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1187 uint32_t base_rw_mgr;
1189 *bit_chk = param->read_correct_mask;
1190 correct_mask_vg = param->read_correct_mask_vg;
1192 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1193 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1195 for (r = rank_bgn; r < rank_end; r++) {
1196 if (param->skip_ranks[r])
1197 /* request to skip the rank */
1201 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1203 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1205 writel(RW_MGR_READ_B2B_WAIT1,
1206 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1208 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1209 writel(RW_MGR_READ_B2B_WAIT2,
1210 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1212 if (quick_read_mode)
1213 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1214 /* need at least two (1+1) reads to capture failures */
1215 else if (all_groups)
1216 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1218 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1220 writel(RW_MGR_READ_B2B,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1223 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1224 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1225 &sdr_rw_load_mgr_regs->load_cntr3);
1227 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1229 writel(RW_MGR_READ_B2B,
1230 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1234 /* reset the fifos to get pointers to known state */
1235 writel(0, &phy_mgr_cmd->fifo_reset);
1236 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1237 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1239 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1240 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1243 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1245 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1247 writel(RW_MGR_READ_B2B, addr +
1248 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1251 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1252 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1257 *bit_chk &= tmp_bit_chk;
1260 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1261 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1264 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1265 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1266 (%u == %u) => %lu", __func__, __LINE__, group,
1267 all_groups, *bit_chk, param->read_correct_mask,
1268 (long unsigned int)(*bit_chk ==
1269 param->read_correct_mask));
1270 return *bit_chk == param->read_correct_mask;
1272 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1273 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1274 (%u != %lu) => %lu\n", __func__, __LINE__,
1275 group, all_groups, *bit_chk, (long unsigned int)0,
1276 (long unsigned int)(*bit_chk != 0x00));
1277 return *bit_chk != 0x00;
1281 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1282 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1283 uint32_t all_groups)
1285 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1286 bit_chk, all_groups, 1);
1289 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1291 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1295 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1299 for (i = 0; i < VFIFO_SIZE-1; i++)
1300 rw_mgr_incr_vfifo(grp, v);
1303 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1306 uint32_t fail_cnt = 0;
1307 uint32_t test_status;
1309 for (v = 0; v < VFIFO_SIZE; ) {
1310 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1311 __func__, __LINE__, v);
1312 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1313 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1321 /* fiddle with FIFO */
1322 rw_mgr_incr_vfifo(grp, &v);
1325 if (v >= VFIFO_SIZE) {
1326 /* no failing read found!! Something must have gone wrong */
1327 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1328 __func__, __LINE__);
1335 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1336 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1337 uint32_t *v, uint32_t *d, uint32_t *p,
1338 uint32_t *i, uint32_t *max_working_cnt)
1340 uint32_t found_begin = 0;
1341 uint32_t tmp_delay = 0;
1342 uint32_t test_status;
1344 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1345 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1346 *work_bgn = tmp_delay;
1347 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1349 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1350 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1351 IO_DELAY_PER_OPA_TAP) {
1352 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1355 rw_mgr_mem_calibrate_read_test_all_ranks
1356 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1359 *max_working_cnt = 1;
1368 if (*p > IO_DQS_EN_PHASE_MAX)
1369 /* fiddle with FIFO */
1370 rw_mgr_incr_vfifo(*grp, v);
1377 if (*i >= VFIFO_SIZE) {
1378 /* cannot find working solution */
1379 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1380 ptap/dtap\n", __func__, __LINE__);
1387 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1388 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1389 uint32_t *p, uint32_t *max_working_cnt)
1391 uint32_t found_begin = 0;
1394 /* Special case code for backing up a phase */
1396 *p = IO_DQS_EN_PHASE_MAX;
1397 rw_mgr_decr_vfifo(*grp, v);
1401 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1402 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1404 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1405 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1406 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1408 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1412 *work_bgn = tmp_delay;
1417 /* We have found a working dtap before the ptap found above */
1418 if (found_begin == 1)
1419 (*max_working_cnt)++;
1422 * Restore VFIFO to old state before we decremented it
1426 if (*p > IO_DQS_EN_PHASE_MAX) {
1428 rw_mgr_incr_vfifo(*grp, v);
1431 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1434 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1435 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1436 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1439 uint32_t found_end = 0;
1442 *work_end += IO_DELAY_PER_OPA_TAP;
1443 if (*p > IO_DQS_EN_PHASE_MAX) {
1444 /* fiddle with FIFO */
1446 rw_mgr_incr_vfifo(*grp, v);
1449 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1450 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1451 += IO_DELAY_PER_OPA_TAP) {
1452 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1454 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1455 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1459 (*max_working_cnt)++;
1466 if (*p > IO_DQS_EN_PHASE_MAX) {
1467 /* fiddle with FIFO */
1468 rw_mgr_incr_vfifo(*grp, v);
1473 if (*i >= VFIFO_SIZE + 1) {
1474 /* cannot see edge of failing read */
1475 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1476 failed\n", __func__, __LINE__);
1483 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1484 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1485 uint32_t *p, uint32_t *work_mid,
1491 *work_mid = (*work_bgn + *work_end) / 2;
1493 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1494 *work_bgn, *work_end, *work_mid);
1495 /* Get the middle delay to be less than a VFIFO delay */
1496 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1497 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1499 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1500 while (*work_mid > tmp_delay)
1501 *work_mid -= tmp_delay;
1502 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1505 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1506 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1508 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1509 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1510 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1511 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1513 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1515 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1516 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1519 * push vfifo until we can successfully calibrate. We can do this
1520 * because the largest possible margin in 1 VFIFO cycle.
1522 for (i = 0; i < VFIFO_SIZE; i++) {
1523 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1525 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1531 /* fiddle with FIFO */
1532 rw_mgr_incr_vfifo(*grp, v);
1535 if (i >= VFIFO_SIZE) {
1536 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1537 failed\n", __func__, __LINE__);
1544 /* find a good dqs enable to use */
1545 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1547 uint32_t v, d, p, i;
1548 uint32_t max_working_cnt;
1550 uint32_t dtaps_per_ptap;
1551 uint32_t work_bgn, work_mid, work_end;
1552 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1554 debug("%s:%d %u\n", __func__, __LINE__, grp);
1556 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1558 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1559 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1561 /* ************************************************************** */
1562 /* * Step 0 : Determine number of delay taps for each phase tap * */
1563 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1565 /* ********************************************************* */
1566 /* * Step 1 : First push vfifo until we get a failing read * */
1567 v = find_vfifo_read(grp, &bit_chk);
1569 max_working_cnt = 0;
1571 /* ******************************************************** */
1572 /* * step 2: find first working phase, increment in ptaps * */
1574 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1575 &p, &i, &max_working_cnt) == 0)
1578 work_end = work_bgn;
1581 * If d is 0 then the working window covers a phase tap and
1582 * we can follow the old procedure otherwise, we've found the beginning,
1583 * and we need to increment the dtaps until we find the end.
1586 /* ********************************************************* */
1587 /* * step 3a: if we have room, back off by one and
1588 increment in dtaps * */
1590 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1593 /* ********************************************************* */
1594 /* * step 4a: go forward from working phase to non working
1595 phase, increment in ptaps * */
1596 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1597 &i, &max_working_cnt, &work_end) == 0)
1600 /* ********************************************************* */
1601 /* * step 5a: back off one from last, increment in dtaps * */
1603 /* Special case code for backing up a phase */
1605 p = IO_DQS_EN_PHASE_MAX;
1606 rw_mgr_decr_vfifo(grp, &v);
1611 work_end -= IO_DELAY_PER_OPA_TAP;
1612 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1614 /* * The actual increment of dtaps is done outside of
1615 the if/else loop to share code */
1618 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1619 vfifo=%u ptap=%u\n", __func__, __LINE__,
1622 /* ******************************************************* */
1623 /* * step 3-5b: Find the right edge of the window using
1625 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1626 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1629 work_end = work_bgn;
1631 /* * The actual increment of dtaps is done outside of the
1632 if/else loop to share code */
1634 /* Only here to counterbalance a subtract later on which is
1635 not needed if this branch of the algorithm is taken */
1639 /* The dtap increment to find the failing edge is done here */
1640 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1641 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1642 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1643 end-2: dtap=%u\n", __func__, __LINE__, d);
1644 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1646 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1653 /* Go back to working dtap */
1655 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1657 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1658 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1659 v, p, d-1, work_end);
1661 if (work_end < work_bgn) {
1663 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1664 failed\n", __func__, __LINE__);
1668 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1669 __func__, __LINE__, work_bgn, work_end);
1671 /* *************************************************************** */
1673 * * We need to calculate the number of dtaps that equal a ptap
1674 * * To do that we'll back up a ptap and re-find the edge of the
1675 * * window using dtaps
1678 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1679 for tracking\n", __func__, __LINE__);
1681 /* Special case code for backing up a phase */
1683 p = IO_DQS_EN_PHASE_MAX;
1684 rw_mgr_decr_vfifo(grp, &v);
1685 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1686 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1690 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1691 phase only: v=%u p=%u", __func__, __LINE__,
1695 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1698 * Increase dtap until we first see a passing read (in case the
1699 * window is smaller than a ptap),
1700 * and then a failing read to mark the edge of the window again
1703 /* Find a passing read */
1704 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1705 __func__, __LINE__);
1706 found_passing_read = 0;
1707 found_failing_read = 0;
1708 initial_failing_dtap = d;
1709 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1710 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1711 read d=%u\n", __func__, __LINE__, d);
1712 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1714 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1717 found_passing_read = 1;
1722 if (found_passing_read) {
1723 /* Find a failing read */
1724 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1725 read\n", __func__, __LINE__);
1726 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1727 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1728 testing read d=%u\n", __func__, __LINE__, d);
1729 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1731 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1732 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1733 found_failing_read = 1;
1738 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1739 calculate dtaps", __func__, __LINE__);
1740 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1744 * The dynamically calculated dtaps_per_ptap is only valid if we
1745 * found a passing/failing read. If we didn't, it means d hit the max
1746 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1747 * statically calculated value.
1749 if (found_passing_read && found_failing_read)
1750 dtaps_per_ptap = d - initial_failing_dtap;
1752 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1753 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1754 - %u = %u", __func__, __LINE__, d,
1755 initial_failing_dtap, dtaps_per_ptap);
1757 /* ******************************************** */
1758 /* * step 6: Find the centre of the window * */
1759 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1760 &work_mid, &work_end) == 0)
1763 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1764 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1770 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1771 * dq_in_delay values
1774 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1775 (const u32 rw_group, const u32 test_bgn)
1777 /* We start at zero, so have one less dq to devide among */
1778 const u32 delay_step = IO_IO_IN_DELAY_MAX /
1779 (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
1783 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
1785 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
1786 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1787 r += NUM_RANKS_PER_SHADOW_REG) {
1788 for (i = 0, p = test_bgn, d = 0;
1789 i < RW_MGR_MEM_DQ_PER_READ_DQS;
1790 i++, p++, d += delay_step) {
1791 debug_cond(DLEVEL == 1,
1792 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
1793 __func__, __LINE__, rw_group, r, i, p, d);
1795 scc_mgr_set_dq_in_delay(p, d);
1799 writel(0, &sdr_scc_mgr->update);
1802 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
1804 debug_cond(DLEVEL == 1,
1805 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
1806 __func__, __LINE__, rw_group, found);
1808 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1809 r += NUM_RANKS_PER_SHADOW_REG) {
1810 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1811 writel(0, &sdr_scc_mgr->update);
1820 /* per-bit deskew DQ and center */
1821 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1822 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1823 uint32_t use_read_test, uint32_t update_fom)
1825 uint32_t i, p, d, min_index;
1827 * Store these as signed since there are comparisons with
1831 uint32_t sticky_bit_chk;
1832 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1833 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1834 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1836 int32_t orig_mid_min, mid_min;
1837 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1839 int32_t dq_margin, dqs_margin;
1841 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1844 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1846 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1847 start_dqs = readl(addr + (read_group << 2));
1848 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1849 start_dqs_en = readl(addr + ((read_group << 2)
1850 - IO_DQS_EN_DELAY_OFFSET));
1852 /* set the left and right edge of each bit to an illegal value */
1853 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1855 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1856 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1857 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1860 /* Search for the left edge of the window for each bit */
1861 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1862 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1864 writel(0, &sdr_scc_mgr->update);
1867 * Stop searching when the read test doesn't pass AND when
1868 * we've seen a passing read on every bit.
1870 if (use_read_test) {
1871 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1872 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1875 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1878 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1879 (read_group - (write_group *
1880 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1881 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1882 stop = (bit_chk == 0);
1884 sticky_bit_chk = sticky_bit_chk | bit_chk;
1885 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1886 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1887 && %u", __func__, __LINE__, d,
1889 param->read_correct_mask, stop);
1894 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1896 /* Remember a passing test as the
1900 /* If a left edge has not been seen yet,
1901 then a future passing test will mark
1902 this edge as the right edge */
1904 IO_IO_IN_DELAY_MAX + 1) {
1905 right_edge[i] = -(d + 1);
1908 bit_chk = bit_chk >> 1;
1913 /* Reset DQ delay chains to 0 */
1914 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1916 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1917 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1918 %d right_edge[%u]: %d\n", __func__, __LINE__,
1919 i, left_edge[i], i, right_edge[i]);
1922 * Check for cases where we haven't found the left edge,
1923 * which makes our assignment of the the right edge invalid.
1924 * Reset it to the illegal value.
1926 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1927 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1928 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1929 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1930 right_edge[%u]: %d\n", __func__, __LINE__,
1935 * Reset sticky bit (except for bits where we have seen
1936 * both the left and right edge).
1938 sticky_bit_chk = sticky_bit_chk << 1;
1939 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1940 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1941 sticky_bit_chk = sticky_bit_chk | 1;
1948 /* Search for the right edge of the window for each bit */
1949 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1950 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1951 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1952 uint32_t delay = d + start_dqs_en;
1953 if (delay > IO_DQS_EN_DELAY_MAX)
1954 delay = IO_DQS_EN_DELAY_MAX;
1955 scc_mgr_set_dqs_en_delay(read_group, delay);
1957 scc_mgr_load_dqs(read_group);
1959 writel(0, &sdr_scc_mgr->update);
1962 * Stop searching when the read test doesn't pass AND when
1963 * we've seen a passing read on every bit.
1965 if (use_read_test) {
1966 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1967 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1970 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1973 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1974 (read_group - (write_group *
1975 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1976 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1977 stop = (bit_chk == 0);
1979 sticky_bit_chk = sticky_bit_chk | bit_chk;
1980 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1982 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1983 %u && %u", __func__, __LINE__, d,
1984 sticky_bit_chk, param->read_correct_mask, stop);
1989 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1991 /* Remember a passing test as
1996 /* If a right edge has not been
1997 seen yet, then a future passing
1998 test will mark this edge as the
2000 if (right_edge[i] ==
2001 IO_IO_IN_DELAY_MAX + 1) {
2002 left_edge[i] = -(d + 1);
2005 /* d = 0 failed, but it passed
2006 when testing the left edge,
2007 so it must be marginal,
2009 if (right_edge[i] ==
2010 IO_IO_IN_DELAY_MAX + 1 &&
2016 /* If a right edge has not been
2017 seen yet, then a future passing
2018 test will mark this edge as the
2020 else if (right_edge[i] ==
2021 IO_IO_IN_DELAY_MAX +
2023 left_edge[i] = -(d + 1);
2028 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2029 d=%u]: ", __func__, __LINE__, d);
2030 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2031 (int)(bit_chk & 1), i, left_edge[i]);
2032 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2034 bit_chk = bit_chk >> 1;
2039 /* Check that all bits have a window */
2040 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2041 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2042 %d right_edge[%u]: %d", __func__, __LINE__,
2043 i, left_edge[i], i, right_edge[i]);
2044 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2045 == IO_IO_IN_DELAY_MAX + 1)) {
2047 * Restore delay chain settings before letting the loop
2048 * in rw_mgr_mem_calibrate_vfifo to retry different
2049 * dqs/ck relationships.
2051 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2052 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2053 scc_mgr_set_dqs_en_delay(read_group,
2056 scc_mgr_load_dqs(read_group);
2057 writel(0, &sdr_scc_mgr->update);
2059 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2060 find edge [%u]: %d %d", __func__, __LINE__,
2061 i, left_edge[i], right_edge[i]);
2062 if (use_read_test) {
2063 set_failing_group_stage(read_group *
2064 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2066 CAL_SUBSTAGE_VFIFO_CENTER);
2068 set_failing_group_stage(read_group *
2069 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2070 CAL_STAGE_VFIFO_AFTER_WRITES,
2071 CAL_SUBSTAGE_VFIFO_CENTER);
2077 /* Find middle of window for each DQ bit */
2078 mid_min = left_edge[0] - right_edge[0];
2080 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2081 mid = left_edge[i] - right_edge[i];
2082 if (mid < mid_min) {
2089 * -mid_min/2 represents the amount that we need to move DQS.
2090 * If mid_min is odd and positive we'll need to add one to
2091 * make sure the rounding in further calculations is correct
2092 * (always bias to the right), so just add 1 for all positive values.
2097 mid_min = mid_min / 2;
2099 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2100 __func__, __LINE__, mid_min, min_index);
2102 /* Determine the amount we can change DQS (which is -mid_min) */
2103 orig_mid_min = mid_min;
2104 new_dqs = start_dqs - mid_min;
2105 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2106 new_dqs = IO_DQS_IN_DELAY_MAX;
2107 else if (new_dqs < 0)
2110 mid_min = start_dqs - new_dqs;
2111 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2114 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2115 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2116 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2117 else if (start_dqs_en - mid_min < 0)
2118 mid_min += start_dqs_en - mid_min;
2120 new_dqs = start_dqs - mid_min;
2122 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2123 new_dqs=%d mid_min=%d\n", start_dqs,
2124 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2127 /* Initialize data for export structures */
2128 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2129 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2131 /* add delay to bring centre of all DQ windows to the same "level" */
2132 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2133 /* Use values before divide by 2 to reduce round off error */
2134 shift_dq = (left_edge[i] - right_edge[i] -
2135 (left_edge[min_index] - right_edge[min_index]))/2 +
2136 (orig_mid_min - mid_min);
2138 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2139 shift_dq[%u]=%d\n", i, shift_dq);
2141 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2142 temp_dq_in_delay1 = readl(addr + (p << 2));
2143 temp_dq_in_delay2 = readl(addr + (i << 2));
2145 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2146 (int32_t)IO_IO_IN_DELAY_MAX) {
2147 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2148 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2149 shift_dq = -(int32_t)temp_dq_in_delay1;
2151 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2152 shift_dq[%u]=%d\n", i, shift_dq);
2153 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2154 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2157 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2158 left_edge[i] - shift_dq + (-mid_min),
2159 right_edge[i] + shift_dq - (-mid_min));
2160 /* To determine values for export structures */
2161 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2162 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2164 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2165 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2168 final_dqs = new_dqs;
2169 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2170 final_dqs_en = start_dqs_en - mid_min;
2173 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2174 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2175 scc_mgr_load_dqs(read_group);
2179 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2180 scc_mgr_load_dqs(read_group);
2181 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2182 dqs_margin=%d", __func__, __LINE__,
2183 dq_margin, dqs_margin);
2186 * Do not remove this line as it makes sure all of our decisions
2187 * have been applied. Apply the update bit.
2189 writel(0, &sdr_scc_mgr->update);
2191 return (dq_margin >= 0) && (dqs_margin >= 0);
2195 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2196 * @rw_group: Read/Write Group
2197 * @phase: DQ/DQS phase
2199 * Because initially no communication ca be reliably performed with the memory
2200 * device, the sequencer uses a guaranteed write mechanism to write data into
2201 * the memory device.
2203 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2208 /* Set a particular DQ/DQS phase. */
2209 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2211 debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2212 __func__, __LINE__, rw_group, phase);
2215 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2216 * Load up the patterns used by read calibration using the
2217 * current DQDQS phase.
2219 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2221 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2225 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2226 * Back-to-Back reads of the patterns used for calibration.
2228 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2230 debug_cond(DLEVEL == 1,
2231 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2232 __func__, __LINE__, rw_group, phase);
2237 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2238 * @rw_group: Read/Write Group
2239 * @test_bgn: Rank at which the test begins
2241 * DQS enable calibration ensures reliable capture of the DQ signal without
2242 * glitches on the DQS line.
2244 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2250 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2251 * DQS and DQS Eanble Signal Relationships.
2253 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay(
2254 rw_group, test_bgn);
2259 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2260 * @rw_group: Read/Write Group
2261 * @test_bgn: Rank at which the test begins
2262 * @use_read_test: Perform a read test
2263 * @update_fom: Update FOM
2265 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2269 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2270 const int use_read_test,
2271 const int update_fom)
2274 int ret, grp_calibrated;
2278 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2279 * Read per-bit deskew can be done on a per shadow register basis.
2282 for (rank_bgn = 0, sr = 0;
2283 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2284 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2285 /* Check if this set of ranks should be skipped entirely. */
2286 if (param->skip_shadow_regs[sr])
2289 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2299 if (!grp_calibrated)
2306 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2307 * @rw_group: Read/Write Group
2308 * @test_bgn: Rank at which the test begins
2310 * Stage 1: Calibrate the read valid prediction FIFO.
2312 * This function implements UniPHY calibration Stage 1, as explained in
2313 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2315 * - read valid prediction will consist of finding:
2316 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2317 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2318 * - we also do a per-bit deskew on the DQ lines.
2320 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2323 uint32_t dtaps_per_ptap;
2324 uint32_t failed_substage;
2328 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2330 /* Update info for sims */
2331 reg_file_set_group(rw_group);
2332 reg_file_set_stage(CAL_STAGE_VFIFO);
2333 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2335 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2337 /* USER Determine number of delay taps for each phase tap. */
2338 dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2339 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2341 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2343 * In RLDRAMX we may be messing the delay of pins in
2344 * the same write rw_group but outside of the current read
2345 * the rw_group, but that's ok because we haven't calibrated
2349 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2353 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2354 /* 1) Guaranteed Write */
2355 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2359 /* 2) DQS Enable Calibration */
2360 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2363 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2367 /* 3) Centering DQ/DQS */
2369 * If doing read after write calibration, do not update
2370 * FOM now. Do it then.
2372 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2375 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2384 /* Calibration Stage 1 failed. */
2385 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2388 /* Calibration Stage 1 completed OK. */
2391 * Reset the delay chains back to zero if they have moved > 1
2392 * (check for > 1 because loop will increase d even when pass in
2396 scc_mgr_zero_group(rw_group, 1);
2401 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2402 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2405 uint32_t rank_bgn, sr;
2406 uint32_t grp_calibrated;
2407 uint32_t write_group;
2409 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2411 /* update info for sims */
2413 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2414 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2416 write_group = read_group;
2418 /* update info for sims */
2419 reg_file_set_group(read_group);
2422 /* Read per-bit deskew can be done on a per shadow register basis */
2423 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2424 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2425 /* Determine if this set of ranks should be skipped entirely */
2426 if (!param->skip_shadow_regs[sr]) {
2427 /* This is the last calibration round, update FOM here */
2428 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2439 if (grp_calibrated == 0) {
2440 set_failing_group_stage(write_group,
2441 CAL_STAGE_VFIFO_AFTER_WRITES,
2442 CAL_SUBSTAGE_VFIFO_CENTER);
2449 /* Calibrate LFIFO to find smallest read latency */
2450 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2455 debug("%s:%d\n", __func__, __LINE__);
2457 /* update info for sims */
2458 reg_file_set_stage(CAL_STAGE_LFIFO);
2459 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2461 /* Load up the patterns used by read calibration for all ranks */
2462 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2466 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2467 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2468 __func__, __LINE__, gbl->curr_read_lat);
2470 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2478 /* reduce read latency and see if things are working */
2480 gbl->curr_read_lat--;
2481 } while (gbl->curr_read_lat > 0);
2483 /* reset the fifos to get pointers to known state */
2485 writel(0, &phy_mgr_cmd->fifo_reset);
2488 /* add a fudge factor to the read latency that was determined */
2489 gbl->curr_read_lat += 2;
2490 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2491 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2492 read_lat=%u\n", __func__, __LINE__,
2493 gbl->curr_read_lat);
2496 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2497 CAL_SUBSTAGE_READ_LATENCY);
2499 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2500 read_lat=%u\n", __func__, __LINE__,
2501 gbl->curr_read_lat);
2507 * issue write test command.
2508 * two variants are provided. one that just tests a write pattern and
2509 * another that tests datamask functionality.
2511 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2514 uint32_t mcc_instruction;
2515 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2516 ENABLE_SUPER_QUICK_CALIBRATION);
2517 uint32_t rw_wl_nop_cycles;
2521 * Set counter and jump addresses for the right
2522 * number of NOP cycles.
2523 * The number of supported NOP cycles can range from -1 to infinity
2524 * Three different cases are handled:
2526 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2527 * mechanism will be used to insert the right number of NOPs
2529 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2530 * issuing the write command will jump straight to the
2531 * micro-instruction that turns on DQS (for DDRx), or outputs write
2532 * data (for RLD), skipping
2533 * the NOP micro-instruction all together
2535 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2536 * turned on in the same micro-instruction that issues the write
2537 * command. Then we need
2538 * to directly jump to the micro-instruction that sends out the data
2540 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2541 * (2 and 3). One jump-counter (0) is used to perform multiple
2542 * write-read operations.
2543 * one counter left to issue this command in "multiple-group" mode
2546 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2548 if (rw_wl_nop_cycles == -1) {
2550 * CNTR 2 - We want to execute the special write operation that
2551 * turns on DQS right away and then skip directly to the
2552 * instruction that sends out the data. We set the counter to a
2553 * large number so that the jump is always taken.
2555 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2557 /* CNTR 3 - Not used */
2559 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2560 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2561 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2562 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2563 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2565 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2566 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2567 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2568 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2569 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2571 } else if (rw_wl_nop_cycles == 0) {
2573 * CNTR 2 - We want to skip the NOP operation and go straight
2574 * to the DQS enable instruction. We set the counter to a large
2575 * number so that the jump is always taken.
2577 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2579 /* CNTR 3 - Not used */
2581 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2582 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2583 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2585 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2586 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2587 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2591 * CNTR 2 - In this case we want to execute the next instruction
2592 * and NOT take the jump. So we set the counter to 0. The jump
2593 * address doesn't count.
2595 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2596 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2599 * CNTR 3 - Set the nop counter to the number of cycles we
2600 * need to loop for, minus 1.
2602 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2604 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2605 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2606 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2608 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2609 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2610 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2614 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2615 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2617 if (quick_write_mode)
2618 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2620 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2622 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2625 * CNTR 1 - This is used to ensure enough time elapses
2626 * for read data to come back.
2628 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2631 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2632 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2634 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2635 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2638 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2639 writel(mcc_instruction, addr + (group << 2));
2642 /* Test writes, can check for a single bit pass or multiple bit pass */
2643 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2644 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2645 uint32_t *bit_chk, uint32_t all_ranks)
2648 uint32_t correct_mask_vg;
2649 uint32_t tmp_bit_chk;
2651 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2652 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2653 uint32_t addr_rw_mgr;
2654 uint32_t base_rw_mgr;
2656 *bit_chk = param->write_correct_mask;
2657 correct_mask_vg = param->write_correct_mask_vg;
2659 for (r = rank_bgn; r < rank_end; r++) {
2660 if (param->skip_ranks[r]) {
2661 /* request to skip the rank */
2666 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2669 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2670 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2671 /* reset the fifos to get pointers to known state */
2672 writel(0, &phy_mgr_cmd->fifo_reset);
2674 tmp_bit_chk = tmp_bit_chk <<
2675 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2676 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2677 rw_mgr_mem_calibrate_write_test_issue(write_group *
2678 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2681 base_rw_mgr = readl(addr_rw_mgr);
2682 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2686 *bit_chk &= tmp_bit_chk;
2690 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2691 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2692 %u => %lu", write_group, use_dm,
2693 *bit_chk, param->write_correct_mask,
2694 (long unsigned int)(*bit_chk ==
2695 param->write_correct_mask));
2696 return *bit_chk == param->write_correct_mask;
2698 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2699 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2700 write_group, use_dm, *bit_chk);
2701 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2702 (long unsigned int)(*bit_chk != 0));
2703 return *bit_chk != 0x00;
2708 * center all windows. do per-bit-deskew to possibly increase size of
2711 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2712 uint32_t write_group, uint32_t test_bgn)
2714 uint32_t i, p, min_index;
2717 * Store these as signed since there are comparisons with
2721 uint32_t sticky_bit_chk;
2722 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2723 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2725 int32_t mid_min, orig_mid_min;
2726 int32_t new_dqs, start_dqs, shift_dq;
2727 int32_t dq_margin, dqs_margin, dm_margin;
2729 uint32_t temp_dq_out1_delay;
2732 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2736 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2737 start_dqs = readl(addr +
2738 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2740 /* per-bit deskew */
2743 * set the left and right edge of each bit to an illegal value
2744 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2747 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2748 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2749 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2752 /* Search for the left edge of the window for each bit */
2753 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2754 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2756 writel(0, &sdr_scc_mgr->update);
2759 * Stop searching when the read test doesn't pass AND when
2760 * we've seen a passing read on every bit.
2762 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2763 0, PASS_ONE_BIT, &bit_chk, 0);
2764 sticky_bit_chk = sticky_bit_chk | bit_chk;
2765 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2766 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2767 == %u && %u [bit_chk= %u ]\n",
2768 d, sticky_bit_chk, param->write_correct_mask,
2774 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2777 * Remember a passing test as the
2783 * If a left edge has not been seen
2784 * yet, then a future passing test will
2785 * mark this edge as the right edge.
2788 IO_IO_OUT1_DELAY_MAX + 1) {
2789 right_edge[i] = -(d + 1);
2792 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2793 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2794 (int)(bit_chk & 1), i, left_edge[i]);
2795 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2797 bit_chk = bit_chk >> 1;
2802 /* Reset DQ delay chains to 0 */
2803 scc_mgr_apply_group_dq_out1_delay(0);
2805 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2806 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2807 %d right_edge[%u]: %d\n", __func__, __LINE__,
2808 i, left_edge[i], i, right_edge[i]);
2811 * Check for cases where we haven't found the left edge,
2812 * which makes our assignment of the the right edge invalid.
2813 * Reset it to the illegal value.
2815 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2816 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2817 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2818 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2819 right_edge[%u]: %d\n", __func__, __LINE__,
2824 * Reset sticky bit (except for bits where we have
2825 * seen the left edge).
2827 sticky_bit_chk = sticky_bit_chk << 1;
2828 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2829 sticky_bit_chk = sticky_bit_chk | 1;
2835 /* Search for the right edge of the window for each bit */
2836 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2837 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2840 writel(0, &sdr_scc_mgr->update);
2843 * Stop searching when the read test doesn't pass AND when
2844 * we've seen a passing read on every bit.
2846 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2847 0, PASS_ONE_BIT, &bit_chk, 0);
2849 sticky_bit_chk = sticky_bit_chk | bit_chk;
2850 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2852 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2853 %u && %u\n", d, sticky_bit_chk,
2854 param->write_correct_mask, stop);
2858 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2860 /* d = 0 failed, but it passed when
2861 testing the left edge, so it must be
2862 marginal, set it to -1 */
2863 if (right_edge[i] ==
2864 IO_IO_OUT1_DELAY_MAX + 1 &&
2866 IO_IO_OUT1_DELAY_MAX + 1) {
2873 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2876 * Remember a passing test as
2883 * If a right edge has not
2884 * been seen yet, then a future
2885 * passing test will mark this
2886 * edge as the left edge.
2888 if (right_edge[i] ==
2889 IO_IO_OUT1_DELAY_MAX + 1)
2890 left_edge[i] = -(d + 1);
2893 * d = 0 failed, but it passed
2894 * when testing the left edge,
2895 * so it must be marginal, set
2898 if (right_edge[i] ==
2899 IO_IO_OUT1_DELAY_MAX + 1 &&
2901 IO_IO_OUT1_DELAY_MAX + 1)
2904 * If a right edge has not been
2905 * seen yet, then a future
2906 * passing test will mark this
2907 * edge as the left edge.
2909 else if (right_edge[i] ==
2910 IO_IO_OUT1_DELAY_MAX +
2912 left_edge[i] = -(d + 1);
2915 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2916 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2917 (int)(bit_chk & 1), i, left_edge[i]);
2918 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2920 bit_chk = bit_chk >> 1;
2925 /* Check that all bits have a window */
2926 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2927 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2928 %d right_edge[%u]: %d", __func__, __LINE__,
2929 i, left_edge[i], i, right_edge[i]);
2930 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2931 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2932 set_failing_group_stage(test_bgn + i,
2934 CAL_SUBSTAGE_WRITES_CENTER);
2939 /* Find middle of window for each DQ bit */
2940 mid_min = left_edge[0] - right_edge[0];
2942 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2943 mid = left_edge[i] - right_edge[i];
2944 if (mid < mid_min) {
2951 * -mid_min/2 represents the amount that we need to move DQS.
2952 * If mid_min is odd and positive we'll need to add one to
2953 * make sure the rounding in further calculations is correct
2954 * (always bias to the right), so just add 1 for all positive values.
2958 mid_min = mid_min / 2;
2959 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2962 /* Determine the amount we can change DQS (which is -mid_min) */
2963 orig_mid_min = mid_min;
2964 new_dqs = start_dqs;
2966 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2967 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2968 /* Initialize data for export structures */
2969 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2970 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2972 /* add delay to bring centre of all DQ windows to the same "level" */
2973 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2974 /* Use values before divide by 2 to reduce round off error */
2975 shift_dq = (left_edge[i] - right_edge[i] -
2976 (left_edge[min_index] - right_edge[min_index]))/2 +
2977 (orig_mid_min - mid_min);
2979 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2980 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2982 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2983 temp_dq_out1_delay = readl(addr + (i << 2));
2984 if (shift_dq + (int32_t)temp_dq_out1_delay >
2985 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2986 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2987 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2988 shift_dq = -(int32_t)temp_dq_out1_delay;
2990 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2992 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2995 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2996 left_edge[i] - shift_dq + (-mid_min),
2997 right_edge[i] + shift_dq - (-mid_min));
2998 /* To determine values for export structures */
2999 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
3000 dq_margin = left_edge[i] - shift_dq + (-mid_min);
3002 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
3003 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
3007 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3008 writel(0, &sdr_scc_mgr->update);
3011 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3014 * set the left and right edge of each bit to an illegal value,
3015 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3017 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3018 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3019 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3020 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3021 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3022 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3023 int32_t win_best = 0;
3025 /* Search for the/part of the window with DM shift */
3026 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3027 scc_mgr_apply_group_dm_out1_delay(d);
3028 writel(0, &sdr_scc_mgr->update);
3030 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3031 PASS_ALL_BITS, &bit_chk,
3033 /* USE Set current end of the window */
3036 * If a starting edge of our window has not been seen
3037 * this is our current start of the DM window.
3039 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3043 * If current window is bigger than best seen.
3044 * Set best seen to be current window.
3046 if ((end_curr-bgn_curr+1) > win_best) {
3047 win_best = end_curr-bgn_curr+1;
3048 bgn_best = bgn_curr;
3049 end_best = end_curr;
3052 /* We just saw a failing test. Reset temp edge */
3053 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3054 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3059 /* Reset DM delay chains to 0 */
3060 scc_mgr_apply_group_dm_out1_delay(0);
3063 * Check to see if the current window nudges up aganist 0 delay.
3064 * If so we need to continue the search by shifting DQS otherwise DQS
3065 * search begins as a new search. */
3066 if (end_curr != 0) {
3067 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3068 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3071 /* Search for the/part of the window with DQS shifts */
3072 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3074 * Note: This only shifts DQS, so are we limiting ourselve to
3075 * width of DQ unnecessarily.
3077 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3080 writel(0, &sdr_scc_mgr->update);
3081 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3082 PASS_ALL_BITS, &bit_chk,
3084 /* USE Set current end of the window */
3087 * If a beginning edge of our window has not been seen
3088 * this is our current begin of the DM window.
3090 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3094 * If current window is bigger than best seen. Set best
3095 * seen to be current window.
3097 if ((end_curr-bgn_curr+1) > win_best) {
3098 win_best = end_curr-bgn_curr+1;
3099 bgn_best = bgn_curr;
3100 end_best = end_curr;
3103 /* We just saw a failing test. Reset temp edge */
3104 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3105 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3107 /* Early exit optimization: if ther remaining delay
3108 chain space is less than already seen largest window
3111 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3117 /* assign left and right edge for cal and reporting; */
3118 left_edge[0] = -1*bgn_best;
3119 right_edge[0] = end_best;
3121 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3122 __LINE__, left_edge[0], right_edge[0]);
3124 /* Move DQS (back to orig) */
3125 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3129 /* Find middle of window for the DM bit */
3130 mid = (left_edge[0] - right_edge[0]) / 2;
3132 /* only move right, since we are not moving DQS/DQ */
3136 /* dm_marign should fail if we never find a window */
3140 dm_margin = left_edge[0] - mid;
3142 scc_mgr_apply_group_dm_out1_delay(mid);
3143 writel(0, &sdr_scc_mgr->update);
3145 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3146 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3147 right_edge[0], mid, dm_margin);
3149 gbl->fom_out += dq_margin + dqs_margin;
3151 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3152 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3153 dq_margin, dqs_margin, dm_margin);
3156 * Do not remove this line as it makes sure all of our
3157 * decisions have been applied.
3159 writel(0, &sdr_scc_mgr->update);
3160 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3163 /* calibrate the write operations */
3164 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3167 /* update info for sims */
3168 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3170 reg_file_set_stage(CAL_STAGE_WRITES);
3171 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3173 reg_file_set_group(g);
3175 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3176 set_failing_group_stage(g, CAL_STAGE_WRITES,
3177 CAL_SUBSTAGE_WRITES_CENTER);
3185 * mem_precharge_and_activate() - Precharge all banks and activate
3187 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3189 static void mem_precharge_and_activate(void)
3193 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3194 /* Test if the rank should be skipped. */
3195 if (param->skip_ranks[r])
3199 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3201 /* Precharge all banks. */
3202 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3203 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3205 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3206 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3207 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3209 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3210 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3211 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3213 /* Activate rows. */
3214 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3215 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3220 * mem_init_latency() - Configure memory RLAT and WLAT settings
3222 * Configure memory RLAT and WLAT parameters.
3224 static void mem_init_latency(void)
3227 * For AV/CV, LFIFO is hardened and always runs at full rate
3228 * so max latency in AFI clocks, used here, is correspondingly
3231 const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3234 debug("%s:%d\n", __func__, __LINE__);
3237 * Read in write latency.
3238 * WL for Hard PHY does not include additive latency.
3240 wlat = readl(&data_mgr->t_wl_add);
3241 wlat += readl(&data_mgr->mem_t_add);
3243 gbl->rw_wl_nop_cycles = wlat - 1;
3245 /* Read in readl latency. */
3246 rlat = readl(&data_mgr->t_rl_add);
3248 /* Set a pretty high read latency initially. */
3249 gbl->curr_read_lat = rlat + 16;
3250 if (gbl->curr_read_lat > max_latency)
3251 gbl->curr_read_lat = max_latency;
3253 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3255 /* Advertise write latency. */
3256 writel(wlat, &phy_mgr_cfg->afi_wlat);
3260 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3262 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3264 static void mem_skip_calibrate(void)
3266 uint32_t vfifo_offset;
3269 debug("%s:%d\n", __func__, __LINE__);
3270 /* Need to update every shadow register set used by the interface */
3271 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3272 r += NUM_RANKS_PER_SHADOW_REG) {
3274 * Set output phase alignment settings appropriate for
3277 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3278 scc_mgr_set_dqs_en_phase(i, 0);
3279 #if IO_DLL_CHAIN_LENGTH == 6
3280 scc_mgr_set_dqdqs_output_phase(i, 6);
3282 scc_mgr_set_dqdqs_output_phase(i, 7);
3287 * Write data arrives to the I/O two cycles before write
3288 * latency is reached (720 deg).
3289 * -> due to bit-slip in a/c bus
3290 * -> to allow board skew where dqs is longer than ck
3291 * -> how often can this happen!?
3292 * -> can claim back some ptaps for high freq
3293 * support if we can relax this, but i digress...
3295 * The write_clk leads mem_ck by 90 deg
3296 * The minimum ptap of the OPA is 180 deg
3297 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3298 * The write_clk is always delayed by 2 ptaps
3300 * Hence, to make DQS aligned to CK, we need to delay
3302 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3304 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3305 * gives us the number of ptaps, which simplies to:
3307 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3309 scc_mgr_set_dqdqs_output_phase(i,
3310 1.25 * IO_DLL_CHAIN_LENGTH - 2);
3312 writel(0xff, &sdr_scc_mgr->dqs_ena);
3313 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3315 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3316 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3317 SCC_MGR_GROUP_COUNTER_OFFSET);
3319 writel(0xff, &sdr_scc_mgr->dq_ena);
3320 writel(0xff, &sdr_scc_mgr->dm_ena);
3321 writel(0, &sdr_scc_mgr->update);
3324 /* Compensate for simulation model behaviour */
3325 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3326 scc_mgr_set_dqs_bus_in_delay(i, 10);
3327 scc_mgr_load_dqs(i);
3329 writel(0, &sdr_scc_mgr->update);
3332 * ArriaV has hard FIFOs that can only be initialized by incrementing
3335 vfifo_offset = CALIB_VFIFO_OFFSET;
3336 for (j = 0; j < vfifo_offset; j++)
3337 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3338 writel(0, &phy_mgr_cmd->fifo_reset);
3341 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3342 * setting from generation-time constant.
3344 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3345 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3349 * mem_calibrate() - Memory calibration entry point.
3351 * Perform memory calibration.
3353 static uint32_t mem_calibrate(void)
3356 uint32_t rank_bgn, sr;
3357 uint32_t write_group, write_test_bgn;
3358 uint32_t read_group, read_test_bgn;
3359 uint32_t run_groups, current_run;
3360 uint32_t failing_groups = 0;
3361 uint32_t group_failed = 0;
3363 const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3364 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3366 debug("%s:%d\n", __func__, __LINE__);
3368 /* Initialize the data settings */
3369 gbl->error_substage = CAL_SUBSTAGE_NIL;
3370 gbl->error_stage = CAL_STAGE_NIL;
3371 gbl->error_group = 0xff;
3375 /* Initialize WLAT and RLAT. */
3378 /* Initialize bit slips. */
3379 mem_precharge_and_activate();
3381 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3382 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3383 SCC_MGR_GROUP_COUNTER_OFFSET);
3384 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3386 scc_mgr_set_hhp_extras();
3388 scc_set_bypass_mode(i);
3391 /* Calibration is skipped. */
3392 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3394 * Set VFIFO and LFIFO to instant-on settings in skip
3397 mem_skip_calibrate();
3400 * Do not remove this line as it makes sure all of our
3401 * decisions have been applied.
3403 writel(0, &sdr_scc_mgr->update);
3407 /* Calibration is not skipped. */
3408 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3410 * Zero all delay chain/phase settings for all
3411 * groups and all shadow register sets.
3415 run_groups = ~param->skip_groups;
3417 for (write_group = 0, write_test_bgn = 0; write_group
3418 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3419 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3421 /* Initialize the group failure */
3424 current_run = run_groups & ((1 <<
3425 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3426 run_groups = run_groups >>
3427 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3429 if (current_run == 0)
3432 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3433 SCC_MGR_GROUP_COUNTER_OFFSET);
3434 scc_mgr_zero_group(write_group, 0);
3436 for (read_group = write_group * rwdqs_ratio,
3438 read_group < (write_group + 1) * rwdqs_ratio;
3440 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3441 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3444 /* Calibrate the VFIFO */
3445 if (rw_mgr_mem_calibrate_vfifo(read_group,
3449 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3452 /* The group failed, we're done. */
3456 /* Calibrate the output side */
3457 for (rank_bgn = 0, sr = 0;
3458 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3459 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3460 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3463 /* Not needed in quick mode! */
3464 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3468 * Determine if this set of ranks
3469 * should be skipped entirely.
3471 if (param->skip_shadow_regs[sr])
3474 /* Calibrate WRITEs */
3475 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3476 write_group, write_test_bgn))
3480 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3484 /* Some group failed, we're done. */
3488 for (read_group = write_group * rwdqs_ratio,
3490 read_group < (write_group + 1) * rwdqs_ratio;
3492 read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3493 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3496 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3500 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3503 /* The group failed, we're done. */
3507 /* No group failed, continue as usual. */
3510 grp_failed: /* A group failed, increment the counter. */
3515 * USER If there are any failing groups then report
3518 if (failing_groups != 0)
3521 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3525 * If we're skipping groups as part of debug,
3526 * don't calibrate LFIFO.
3528 if (param->skip_groups != 0)
3531 /* Calibrate the LFIFO */
3532 if (!rw_mgr_mem_calibrate_lfifo())
3537 * Do not remove this line as it makes sure all of our decisions
3538 * have been applied.
3540 writel(0, &sdr_scc_mgr->update);
3545 * run_mem_calibrate() - Perform memory calibration
3547 * This function triggers the entire memory calibration procedure.
3549 static int run_mem_calibrate(void)
3553 debug("%s:%d\n", __func__, __LINE__);
3555 /* Reset pass/fail status shown on afi_cal_success/fail */
3556 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3558 /* Stop tracking manager. */
3559 clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3561 phy_mgr_initialize();
3562 rw_mgr_mem_initialize();
3564 /* Perform the actual memory calibration. */
3565 pass = mem_calibrate();
3567 mem_precharge_and_activate();
3568 writel(0, &phy_mgr_cmd->fifo_reset);
3571 rw_mgr_mem_handoff();
3573 * In Hard PHY this is a 2-bit control:
3575 * 1: DDIO Mux Select
3577 writel(0x2, &phy_mgr_cfg->mux_sel);
3579 /* Start tracking manager. */
3580 setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3586 * debug_mem_calibrate() - Report result of memory calibration
3587 * @pass: Value indicating whether calibration passed or failed
3589 * This function reports the results of the memory calibration
3590 * and writes debug information into the register file.
3592 static void debug_mem_calibrate(int pass)
3594 uint32_t debug_info;
3597 printf("%s: CALIBRATION PASSED\n", __FILE__);
3602 if (gbl->fom_in > 0xff)
3605 if (gbl->fom_out > 0xff)
3606 gbl->fom_out = 0xff;
3608 /* Update the FOM in the register file */
3609 debug_info = gbl->fom_in;
3610 debug_info |= gbl->fom_out << 8;
3611 writel(debug_info, &sdr_reg_file->fom);
3613 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3614 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3616 printf("%s: CALIBRATION FAILED\n", __FILE__);
3618 debug_info = gbl->error_stage;
3619 debug_info |= gbl->error_substage << 8;
3620 debug_info |= gbl->error_group << 16;
3622 writel(debug_info, &sdr_reg_file->failing_stage);
3623 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3624 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3626 /* Update the failing group/stage in the register file */
3627 debug_info = gbl->error_stage;
3628 debug_info |= gbl->error_substage << 8;
3629 debug_info |= gbl->error_group << 16;
3630 writel(debug_info, &sdr_reg_file->failing_stage);
3633 printf("%s: Calibration complete\n", __FILE__);
3637 * hc_initialize_rom_data() - Initialize ROM data
3639 * Initialize ROM data.
3641 static void hc_initialize_rom_data(void)
3645 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3646 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3647 writel(inst_rom_init[i], addr + (i << 2));
3649 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3650 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3651 writel(ac_rom_init[i], addr + (i << 2));
3655 * initialize_reg_file() - Initialize SDR register file
3657 * Initialize SDR register file.
3659 static void initialize_reg_file(void)
3661 /* Initialize the register file with the correct data */
3662 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3663 writel(0, &sdr_reg_file->debug_data_addr);
3664 writel(0, &sdr_reg_file->cur_stage);
3665 writel(0, &sdr_reg_file->fom);
3666 writel(0, &sdr_reg_file->failing_stage);
3667 writel(0, &sdr_reg_file->debug1);
3668 writel(0, &sdr_reg_file->debug2);
3672 * initialize_hps_phy() - Initialize HPS PHY
3674 * Initialize HPS PHY.
3676 static void initialize_hps_phy(void)
3680 * Tracking also gets configured here because it's in the
3683 uint32_t trk_sample_count = 7500;
3684 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3686 * Format is number of outer loops in the 16 MSB, sample
3691 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3692 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3693 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3694 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3695 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3696 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3698 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3699 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3701 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3702 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3704 writel(reg, &sdr_ctrl->phy_ctrl0);
3707 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3709 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3710 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3711 trk_long_idle_sample_count);
3712 writel(reg, &sdr_ctrl->phy_ctrl1);
3715 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3716 trk_long_idle_sample_count >>
3717 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3718 writel(reg, &sdr_ctrl->phy_ctrl2);
3722 * initialize_tracking() - Initialize tracking
3724 * Initialize the register file with usable initial data.
3726 static void initialize_tracking(void)
3729 * Initialize the register file with the correct data.
3730 * Compute usable version of value in case we skip full
3731 * computation later.
3733 writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3734 &sdr_reg_file->dtaps_per_ptap);
3736 /* trk_sample_count */
3737 writel(7500, &sdr_reg_file->trk_sample_count);
3739 /* longidle outer loop [15:0] */
3740 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3743 * longidle sample count [31:24]
3744 * trfc, worst case of 933Mhz 4Gb [23:16]
3745 * trcd, worst case [15:8]
3748 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3749 &sdr_reg_file->delays);
3752 writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3753 (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3754 &sdr_reg_file->trk_rw_mgr_addr);
3756 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3757 &sdr_reg_file->trk_read_dqs_width);
3760 writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3761 &sdr_reg_file->trk_rfsh);
3764 int sdram_calibration_full(void)
3766 struct param_type my_param;
3767 struct gbl_type my_gbl;
3770 memset(&my_param, 0, sizeof(my_param));
3771 memset(&my_gbl, 0, sizeof(my_gbl));
3776 /* Set the calibration enabled by default */
3777 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3779 * Only sweep all groups (regardless of fail state) by default
3780 * Set enabled read test by default.
3782 #if DISABLE_GUARANTEED_READ
3783 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3785 /* Initialize the register file */
3786 initialize_reg_file();
3788 /* Initialize any PHY CSR */
3789 initialize_hps_phy();
3791 scc_mgr_initialize();
3793 initialize_tracking();
3795 printf("%s: Preparing to start memory calibration\n", __FILE__);
3797 debug("%s:%d\n", __func__, __LINE__);
3798 debug_cond(DLEVEL == 1,
3799 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3800 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3801 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3802 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3803 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3804 debug_cond(DLEVEL == 1,
3805 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3806 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3807 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3808 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3809 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3810 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3811 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3812 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3813 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3814 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3815 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3816 IO_IO_OUT2_DELAY_MAX);
3817 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3818 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3820 hc_initialize_rom_data();
3822 /* update info for sims */
3823 reg_file_set_stage(CAL_STAGE_NIL);
3824 reg_file_set_group(0);
3827 * Load global needed for those actions that require
3828 * some dynamic calibration support.
3830 dyn_calib_steps = STATIC_CALIB_STEPS;
3832 * Load global to allow dynamic selection of delay loop settings
3833 * based on calibration mode.
3835 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3836 skip_delay_mask = 0xff;
3838 skip_delay_mask = 0x0;
3840 pass = run_mem_calibrate();
3841 debug_mem_calibrate(pass);