2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
13 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
14 (struct socfpga_sdr_rw_load_manager *)
15 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
16 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
17 (struct socfpga_sdr_rw_load_jump_manager *)
18 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
19 static struct socfpga_sdr_reg_file *sdr_reg_file =
20 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
21 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
22 (struct socfpga_sdr_scc_mgr *)
23 (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
24 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
25 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
26 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
27 (struct socfpga_phy_mgr_cfg *)
28 (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
29 static struct socfpga_data_mgr *data_mgr =
30 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
31 static struct socfpga_sdr_ctrl *sdr_ctrl =
32 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
34 const struct socfpga_sdram_rw_mgr_config *rwcfg;
35 const struct socfpga_sdram_io_config *iocfg;
36 const struct socfpga_sdram_misc_config *misccfg;
41 * In order to reduce ROM size, most of the selectable calibration steps are
42 * decided at compile time based on the user's calibration mode selection,
43 * as captured by the STATIC_CALIB_STEPS selection below.
45 * However, to support simulation-time selection of fast simulation mode, where
46 * we skip everything except the bare minimum, we need a few of the steps to
47 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
48 * check, which is based on the rtl-supplied value, or we dynamically compute
49 * the value to use based on the dynamically-chosen calibration mode
53 #define STATIC_IN_RTL_SIM 0
54 #define STATIC_SKIP_DELAY_LOOPS 0
56 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
57 STATIC_SKIP_DELAY_LOOPS)
59 /* calibration steps requested by the rtl */
60 static u16 dyn_calib_steps;
63 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
64 * instead of static, we use boolean logic to select between
65 * non-skip and skip values
67 * The mask is set to include all bits when not-skipping, but is
71 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
73 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
74 ((non_skip_value) & skip_delay_mask)
76 static struct gbl_type *gbl;
77 static struct param_type *param;
79 static void set_failing_group_stage(u32 group, u32 stage,
83 * Only set the global stage if there was not been any other
86 if (gbl->error_stage == CAL_STAGE_NIL) {
87 gbl->error_substage = substage;
88 gbl->error_stage = stage;
89 gbl->error_group = group;
93 static void reg_file_set_group(u16 set_group)
95 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
98 static void reg_file_set_stage(u8 set_stage)
100 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
103 static void reg_file_set_sub_stage(u8 set_sub_stage)
105 set_sub_stage &= 0xff;
106 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
110 * phy_mgr_initialize() - Initialize PHY Manager
112 * Initialize PHY Manager.
114 static void phy_mgr_initialize(void)
118 debug("%s:%d\n", __func__, __LINE__);
119 /* Calibration has control over path to memory */
121 * In Hard PHY this is a 2-bit control:
125 writel(0x3, &phy_mgr_cfg->mux_sel);
127 /* USER memory clock is not stable we begin initialization */
128 writel(0, &phy_mgr_cfg->reset_mem_stbl);
130 /* USER calibration status all set to zero */
131 writel(0, &phy_mgr_cfg->cal_status);
133 writel(0, &phy_mgr_cfg->cal_debug_info);
135 /* Init params only if we do NOT skip calibration. */
136 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
139 ratio = rwcfg->mem_dq_per_read_dqs /
140 rwcfg->mem_virtual_groups_per_read_dqs;
141 param->read_correct_mask_vg = (1 << ratio) - 1;
142 param->write_correct_mask_vg = (1 << ratio) - 1;
143 param->read_correct_mask = (1 << rwcfg->mem_dq_per_read_dqs) - 1;
144 param->write_correct_mask = (1 << rwcfg->mem_dq_per_write_dqs) - 1;
148 * set_rank_and_odt_mask() - Set Rank and ODT mask
150 * @odt_mode: ODT mode, OFF or READ_WRITE
152 * Set Rank and ODT mask (On-Die Termination).
154 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
160 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
163 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
164 switch (rwcfg->mem_number_of_ranks) {
166 /* Read: ODT = 0 ; Write: ODT = 1 */
170 case 2: /* 2 Ranks */
171 if (rwcfg->mem_number_of_cs_per_dimm == 1) {
173 * - Dual-Slot , Single-Rank (1 CS per DIMM)
175 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
177 * Since MEM_NUMBER_OF_RANKS is 2, they
178 * are both single rank with 2 CS each
179 * (special for RDIMM).
181 * Read: Turn on ODT on the opposite rank
182 * Write: Turn on ODT on all ranks
184 odt_mask_0 = 0x3 & ~(1 << rank);
188 * - Single-Slot , Dual-Rank (2 CS per DIMM)
190 * Read: Turn on ODT off on all ranks
191 * Write: Turn on ODT on active rank
194 odt_mask_1 = 0x3 & (1 << rank);
197 case 4: /* 4 Ranks */
199 * ----------+-----------------------+
201 * Read From +-----------------------+
202 * Rank | 3 | 2 | 1 | 0 |
203 * ----------+-----+-----+-----+-----+
204 * 0 | 0 | 1 | 0 | 0 |
205 * 1 | 1 | 0 | 0 | 0 |
206 * 2 | 0 | 0 | 0 | 1 |
207 * 3 | 0 | 0 | 1 | 0 |
208 * ----------+-----+-----+-----+-----+
211 * ----------+-----------------------+
213 * Write To +-----------------------+
214 * Rank | 3 | 2 | 1 | 0 |
215 * ----------+-----+-----+-----+-----+
216 * 0 | 0 | 1 | 0 | 1 |
217 * 1 | 1 | 0 | 1 | 0 |
218 * 2 | 0 | 1 | 0 | 1 |
219 * 3 | 1 | 0 | 1 | 0 |
220 * ----------+-----+-----+-----+-----+
244 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
245 ((0xFF & odt_mask_0) << 8) |
246 ((0xFF & odt_mask_1) << 16);
247 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
248 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
252 * scc_mgr_set() - Set SCC Manager register
253 * @off: Base offset in SCC Manager space
254 * @grp: Read/Write group
255 * @val: Value to be set
257 * This function sets the SCC Manager (Scan Chain Control Manager) register.
259 static void scc_mgr_set(u32 off, u32 grp, u32 val)
261 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
265 * scc_mgr_initialize() - Initialize SCC Manager registers
267 * Initialize SCC Manager registers.
269 static void scc_mgr_initialize(void)
272 * Clear register file for HPS. 16 (2^4) is the size of the
273 * full register file in the scc mgr:
274 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
275 * MEM_IF_READ_DQS_WIDTH - 1);
279 for (i = 0; i < 16; i++) {
280 debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
281 __func__, __LINE__, i);
282 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
286 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
288 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
291 static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
293 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
296 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
298 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
301 static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
303 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
306 static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
308 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
311 static void scc_mgr_set_dqs_io_in_delay(u32 delay)
313 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
317 static void scc_mgr_set_dm_in_delay(u32 dm, u32 delay)
319 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
320 rwcfg->mem_dq_per_write_dqs + 1 + dm,
324 static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
329 static void scc_mgr_set_dqs_out1_delay(u32 delay)
331 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, rwcfg->mem_dq_per_write_dqs,
335 static void scc_mgr_set_dm_out1_delay(u32 dm, u32 delay)
337 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
338 rwcfg->mem_dq_per_write_dqs + 1 + dm,
342 /* load up dqs config settings */
343 static void scc_mgr_load_dqs(u32 dqs)
345 writel(dqs, &sdr_scc_mgr->dqs_ena);
348 /* load up dqs io config settings */
349 static void scc_mgr_load_dqs_io(void)
351 writel(0, &sdr_scc_mgr->dqs_io_ena);
354 /* load up dq config settings */
355 static void scc_mgr_load_dq(u32 dq_in_group)
357 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
360 /* load up dm config settings */
361 static void scc_mgr_load_dm(u32 dm)
363 writel(dm, &sdr_scc_mgr->dm_ena);
367 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
368 * @off: Base offset in SCC Manager space
369 * @grp: Read/Write group
370 * @val: Value to be set
371 * @update: If non-zero, trigger SCC Manager update for all ranks
373 * This function sets the SCC Manager (Scan Chain Control Manager) register
374 * and optionally triggers the SCC update for all ranks.
376 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
381 for (r = 0; r < rwcfg->mem_number_of_ranks;
382 r += NUM_RANKS_PER_SHADOW_REG) {
383 scc_mgr_set(off, grp, val);
385 if (update || (r == 0)) {
386 writel(grp, &sdr_scc_mgr->dqs_ena);
387 writel(0, &sdr_scc_mgr->update);
392 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
395 * USER although the h/w doesn't support different phases per
396 * shadow register, for simplicity our scc manager modeling
397 * keeps different phase settings per shadow reg, and it's
398 * important for us to keep them in sync to match h/w.
399 * for efficiency, the scan chain update should occur only
402 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
403 read_group, phase, 0);
406 static void scc_mgr_set_dqdqs_output_phase_all_ranks(u32 write_group,
410 * USER although the h/w doesn't support different phases per
411 * shadow register, for simplicity our scc manager modeling
412 * keeps different phase settings per shadow reg, and it's
413 * important for us to keep them in sync to match h/w.
414 * for efficiency, the scan chain update should occur only
417 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
418 write_group, phase, 0);
421 static void scc_mgr_set_dqs_en_delay_all_ranks(u32 read_group,
425 * In shadow register mode, the T11 settings are stored in
426 * registers in the core, which are updated by the DQS_ENA
427 * signals. Not issuing the SCC_MGR_UPD command allows us to
428 * save lots of rank switching overhead, by calling
429 * select_shadow_regs_for_update with update_scan_chains
432 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
433 read_group, delay, 1);
437 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
438 * @write_group: Write group
439 * @delay: Delay value
441 * This function sets the OCT output delay in SCC manager.
443 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
445 const int ratio = rwcfg->mem_if_read_dqs_width /
446 rwcfg->mem_if_write_dqs_width;
447 const int base = write_group * ratio;
450 * Load the setting in the SCC manager
451 * Although OCT affects only write data, the OCT delay is controlled
452 * by the DQS logic block which is instantiated once per read group.
453 * For protocols where a write group consists of multiple read groups,
454 * the setting must be set multiple times.
456 for (i = 0; i < ratio; i++)
457 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
461 * scc_mgr_set_hhp_extras() - Set HHP extras.
463 * Load the fixed setting in the SCC manager HHP extras.
465 static void scc_mgr_set_hhp_extras(void)
468 * Load the fixed setting in the SCC manager
469 * bits: 0:0 = 1'b1 - DQS bypass
470 * bits: 1:1 = 1'b1 - DQ bypass
471 * bits: 4:2 = 3'b001 - rfifo_mode
472 * bits: 6:5 = 2'b01 - rfifo clock_select
473 * bits: 7:7 = 1'b0 - separate gating from ungating setting
474 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
476 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
477 (1 << 2) | (1 << 1) | (1 << 0);
478 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
479 SCC_MGR_HHP_GLOBALS_OFFSET |
480 SCC_MGR_HHP_EXTRAS_OFFSET;
482 debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
485 debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
490 * scc_mgr_zero_all() - Zero all DQS config
492 * Zero all DQS config.
494 static void scc_mgr_zero_all(void)
499 * USER Zero all DQS config settings, across all groups and all
502 for (r = 0; r < rwcfg->mem_number_of_ranks;
503 r += NUM_RANKS_PER_SHADOW_REG) {
504 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
506 * The phases actually don't exist on a per-rank basis,
507 * but there's no harm updating them several times, so
508 * let's keep the code simple.
510 scc_mgr_set_dqs_bus_in_delay(i, iocfg->dqs_in_reserve);
511 scc_mgr_set_dqs_en_phase(i, 0);
512 scc_mgr_set_dqs_en_delay(i, 0);
515 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
516 scc_mgr_set_dqdqs_output_phase(i, 0);
517 /* Arria V/Cyclone V don't have out2. */
518 scc_mgr_set_oct_out1_delay(i, iocfg->dqs_out_reserve);
522 /* Multicast to all DQS group enables. */
523 writel(0xff, &sdr_scc_mgr->dqs_ena);
524 writel(0, &sdr_scc_mgr->update);
528 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
529 * @write_group: Write group
531 * Set bypass mode and trigger SCC update.
533 static void scc_set_bypass_mode(const u32 write_group)
535 /* Multicast to all DQ enables. */
536 writel(0xff, &sdr_scc_mgr->dq_ena);
537 writel(0xff, &sdr_scc_mgr->dm_ena);
539 /* Update current DQS IO enable. */
540 writel(0, &sdr_scc_mgr->dqs_io_ena);
542 /* Update the DQS logic. */
543 writel(write_group, &sdr_scc_mgr->dqs_ena);
546 writel(0, &sdr_scc_mgr->update);
550 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
551 * @write_group: Write group
553 * Load DQS settings for Write Group, do not trigger SCC update.
555 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
557 const int ratio = rwcfg->mem_if_read_dqs_width /
558 rwcfg->mem_if_write_dqs_width;
559 const int base = write_group * ratio;
562 * Load the setting in the SCC manager
563 * Although OCT affects only write data, the OCT delay is controlled
564 * by the DQS logic block which is instantiated once per read group.
565 * For protocols where a write group consists of multiple read groups,
566 * the setting must be set multiple times.
568 for (i = 0; i < ratio; i++)
569 writel(base + i, &sdr_scc_mgr->dqs_ena);
573 * scc_mgr_zero_group() - Zero all configs for a group
575 * Zero DQ, DM, DQS and OCT configs for a group.
577 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
581 for (r = 0; r < rwcfg->mem_number_of_ranks;
582 r += NUM_RANKS_PER_SHADOW_REG) {
583 /* Zero all DQ config settings. */
584 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
585 scc_mgr_set_dq_out1_delay(i, 0);
587 scc_mgr_set_dq_in_delay(i, 0);
590 /* Multicast to all DQ enables. */
591 writel(0xff, &sdr_scc_mgr->dq_ena);
593 /* Zero all DM config settings. */
594 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
596 scc_mgr_set_dm_in_delay(i, 0);
597 scc_mgr_set_dm_out1_delay(i, 0);
600 /* Multicast to all DM enables. */
601 writel(0xff, &sdr_scc_mgr->dm_ena);
603 /* Zero all DQS IO settings. */
605 scc_mgr_set_dqs_io_in_delay(0);
607 /* Arria V/Cyclone V don't have out2. */
608 scc_mgr_set_dqs_out1_delay(iocfg->dqs_out_reserve);
609 scc_mgr_set_oct_out1_delay(write_group, iocfg->dqs_out_reserve);
610 scc_mgr_load_dqs_for_write_group(write_group);
612 /* Multicast to all DQS IO enables (only 1 in total). */
613 writel(0, &sdr_scc_mgr->dqs_io_ena);
615 /* Hit update to zero everything. */
616 writel(0, &sdr_scc_mgr->update);
621 * apply and load a particular input delay for the DQ pins in a group
622 * group_bgn is the index of the first dq pin (in the write group)
624 static void scc_mgr_apply_group_dq_in_delay(u32 group_bgn, u32 delay)
628 for (i = 0, p = group_bgn; i < rwcfg->mem_dq_per_read_dqs; i++, p++) {
629 scc_mgr_set_dq_in_delay(p, delay);
635 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
636 * @delay: Delay value
638 * Apply and load a particular output delay for the DQ pins in a group.
640 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
644 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
645 scc_mgr_set_dq_out1_delay(i, delay);
650 /* apply and load a particular output delay for the DM pins in a group */
651 static void scc_mgr_apply_group_dm_out1_delay(u32 delay1)
655 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
656 scc_mgr_set_dm_out1_delay(i, delay1);
662 /* apply and load delay on both DQS and OCT out1 */
663 static void scc_mgr_apply_group_dqs_io_and_oct_out1(u32 write_group,
666 scc_mgr_set_dqs_out1_delay(delay);
667 scc_mgr_load_dqs_io();
669 scc_mgr_set_oct_out1_delay(write_group, delay);
670 scc_mgr_load_dqs_for_write_group(write_group);
674 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
675 * @write_group: Write group
676 * @delay: Delay value
678 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
680 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
686 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++)
690 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
694 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
695 if (new_delay > iocfg->io_out2_delay_max) {
696 debug_cond(DLEVEL >= 1,
697 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
698 __func__, __LINE__, write_group, delay, new_delay,
699 iocfg->io_out2_delay_max,
700 new_delay - iocfg->io_out2_delay_max);
701 new_delay -= iocfg->io_out2_delay_max;
702 scc_mgr_set_dqs_out1_delay(new_delay);
705 scc_mgr_load_dqs_io();
708 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
709 if (new_delay > iocfg->io_out2_delay_max) {
710 debug_cond(DLEVEL >= 1,
711 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
712 __func__, __LINE__, write_group, delay,
713 new_delay, iocfg->io_out2_delay_max,
714 new_delay - iocfg->io_out2_delay_max);
715 new_delay -= iocfg->io_out2_delay_max;
716 scc_mgr_set_oct_out1_delay(write_group, new_delay);
719 scc_mgr_load_dqs_for_write_group(write_group);
723 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
724 * @write_group: Write group
725 * @delay: Delay value
727 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
730 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
735 for (r = 0; r < rwcfg->mem_number_of_ranks;
736 r += NUM_RANKS_PER_SHADOW_REG) {
737 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
738 writel(0, &sdr_scc_mgr->update);
743 * set_jump_as_return() - Return instruction optimization
745 * Optimization used to recover some slots in ddr3 inst_rom could be
746 * applied to other protocols if we wanted to
748 static void set_jump_as_return(void)
751 * To save space, we replace return with jump to special shared
752 * RETURN instruction so we set the counter to large value so that
755 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
756 writel(rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
760 * delay_for_n_mem_clocks() - Delay for N memory clocks
761 * @clocks: Length of the delay
763 * Delay for N memory clocks.
765 static void delay_for_n_mem_clocks(const u32 clocks)
772 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
774 /* Scale (rounding up) to get afi clocks. */
775 afi_clocks = DIV_ROUND_UP(clocks, misccfg->afi_rate_ratio);
776 if (afi_clocks) /* Temporary underflow protection */
780 * Note, we don't bother accounting for being off a little
781 * bit because of a few extra instructions in outer loops.
782 * Note, the loops have a test at the end, and do the test
783 * before the decrement, and so always perform the loop
784 * 1 time more than the counter value
786 c_loop = afi_clocks >> 16;
787 outer = c_loop ? 0xff : (afi_clocks >> 8);
788 inner = outer ? 0xff : afi_clocks;
791 * rom instructions are structured as follows:
793 * IDLE_LOOP2: jnz cntr0, TARGET_A
794 * IDLE_LOOP1: jnz cntr1, TARGET_B
797 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
798 * TARGET_B is set to IDLE_LOOP2 as well
800 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
801 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
803 * a little confusing, but it helps save precious space in the inst_rom
804 * and sequencer rom and keeps the delays more accurate and reduces
807 if (afi_clocks < 0x100) {
808 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
809 &sdr_rw_load_mgr_regs->load_cntr1);
811 writel(rwcfg->idle_loop1,
812 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
814 writel(rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
815 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
817 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
818 &sdr_rw_load_mgr_regs->load_cntr0);
820 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
821 &sdr_rw_load_mgr_regs->load_cntr1);
823 writel(rwcfg->idle_loop2,
824 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
826 writel(rwcfg->idle_loop2,
827 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
830 writel(rwcfg->idle_loop2,
831 SDR_PHYGRP_RWMGRGRP_ADDRESS |
832 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
833 } while (c_loop-- != 0);
835 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
839 * rw_mgr_mem_init_load_regs() - Load instruction registers
840 * @cntr0: Counter 0 value
841 * @cntr1: Counter 1 value
842 * @cntr2: Counter 2 value
843 * @jump: Jump instruction value
845 * Load instruction registers.
847 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
849 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
850 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
853 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
854 &sdr_rw_load_mgr_regs->load_cntr0);
855 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
856 &sdr_rw_load_mgr_regs->load_cntr1);
857 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
858 &sdr_rw_load_mgr_regs->load_cntr2);
860 /* Load jump address */
861 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
862 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
863 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
865 /* Execute count instruction */
866 writel(jump, grpaddr);
870 * rw_mgr_mem_load_user() - Load user calibration values
871 * @fin1: Final instruction 1
872 * @fin2: Final instruction 2
873 * @precharge: If 1, precharge the banks at the end
875 * Load user calibration values and optionally precharge the banks.
877 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
880 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
881 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
884 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
886 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
888 /* precharge all banks ... */
890 writel(rwcfg->precharge_all, grpaddr);
893 * USER Use Mirror-ed commands for odd ranks if address
896 if ((rwcfg->mem_address_mirroring >> r) & 0x1) {
897 set_jump_as_return();
898 writel(rwcfg->mrs2_mirr, grpaddr);
899 delay_for_n_mem_clocks(4);
900 set_jump_as_return();
901 writel(rwcfg->mrs3_mirr, grpaddr);
902 delay_for_n_mem_clocks(4);
903 set_jump_as_return();
904 writel(rwcfg->mrs1_mirr, grpaddr);
905 delay_for_n_mem_clocks(4);
906 set_jump_as_return();
907 writel(fin1, grpaddr);
909 set_jump_as_return();
910 writel(rwcfg->mrs2, grpaddr);
911 delay_for_n_mem_clocks(4);
912 set_jump_as_return();
913 writel(rwcfg->mrs3, grpaddr);
914 delay_for_n_mem_clocks(4);
915 set_jump_as_return();
916 writel(rwcfg->mrs1, grpaddr);
917 set_jump_as_return();
918 writel(fin2, grpaddr);
924 set_jump_as_return();
925 writel(rwcfg->zqcl, grpaddr);
927 /* tZQinit = tDLLK = 512 ck cycles */
928 delay_for_n_mem_clocks(512);
933 * rw_mgr_mem_initialize() - Initialize RW Manager
935 * Initialize RW Manager.
937 static void rw_mgr_mem_initialize(void)
939 debug("%s:%d\n", __func__, __LINE__);
941 /* The reset / cke part of initialization is broadcasted to all ranks */
942 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
943 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
946 * Here's how you load register for a loop
947 * Counters are located @ 0x800
948 * Jump address are located @ 0xC00
949 * For both, registers 0 to 3 are selected using bits 3 and 2, like
950 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
951 * I know this ain't pretty, but Avalon bus throws away the 2 least
955 /* Start with memory RESET activated */
960 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
961 * If a and b are the number of iteration in 2 nested loops
962 * it takes the following number of cycles to complete the operation:
963 * number_of_cycles = ((2 + n) * a + 2) * b
964 * where n is the number of instruction in the inner loop
965 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
968 rw_mgr_mem_init_load_regs(misccfg->tinit_cntr0_val,
969 misccfg->tinit_cntr1_val,
970 misccfg->tinit_cntr2_val,
971 rwcfg->init_reset_0_cke_0);
973 /* Indicate that memory is stable. */
974 writel(1, &phy_mgr_cfg->reset_mem_stbl);
977 * transition the RESET to high
982 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
983 * If a and b are the number of iteration in 2 nested loops
984 * it takes the following number of cycles to complete the operation
985 * number_of_cycles = ((2 + n) * a + 2) * b
986 * where n is the number of instruction in the inner loop
987 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
990 rw_mgr_mem_init_load_regs(misccfg->treset_cntr0_val,
991 misccfg->treset_cntr1_val,
992 misccfg->treset_cntr2_val,
993 rwcfg->init_reset_1_cke_0);
995 /* Bring up clock enable. */
997 /* tXRP < 250 ck cycles */
998 delay_for_n_mem_clocks(250);
1000 rw_mgr_mem_load_user(rwcfg->mrs0_dll_reset_mirr, rwcfg->mrs0_dll_reset,
1005 * rw_mgr_mem_handoff() - Hand off the memory to user
1007 * At the end of calibration we have to program the user settings in
1008 * and hand off the memory to the user.
1010 static void rw_mgr_mem_handoff(void)
1012 rw_mgr_mem_load_user(rwcfg->mrs0_user_mirr, rwcfg->mrs0_user, 1);
1014 * Need to wait tMOD (12CK or 15ns) time before issuing other
1015 * commands, but we will have plenty of NIOS cycles before actual
1016 * handoff so its okay.
1021 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1022 * @group: Write Group
1025 * Issue write test command. Two variants are provided, one that just tests
1026 * a write pattern and another that tests datamask functionality.
1028 static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
1031 const u32 quick_write_mode =
1032 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1033 misccfg->enable_super_quick_calibration;
1034 u32 mcc_instruction;
1035 u32 rw_wl_nop_cycles;
1038 * Set counter and jump addresses for the right
1039 * number of NOP cycles.
1040 * The number of supported NOP cycles can range from -1 to infinity
1041 * Three different cases are handled:
1043 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1044 * mechanism will be used to insert the right number of NOPs
1046 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1047 * issuing the write command will jump straight to the
1048 * micro-instruction that turns on DQS (for DDRx), or outputs write
1049 * data (for RLD), skipping
1050 * the NOP micro-instruction all together
1052 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1053 * turned on in the same micro-instruction that issues the write
1054 * command. Then we need
1055 * to directly jump to the micro-instruction that sends out the data
1057 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1058 * (2 and 3). One jump-counter (0) is used to perform multiple
1059 * write-read operations.
1060 * one counter left to issue this command in "multiple-group" mode
1063 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
1065 if (rw_wl_nop_cycles == -1) {
1067 * CNTR 2 - We want to execute the special write operation that
1068 * turns on DQS right away and then skip directly to the
1069 * instruction that sends out the data. We set the counter to a
1070 * large number so that the jump is always taken.
1072 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1074 /* CNTR 3 - Not used */
1076 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
1077 writel(rwcfg->lfsr_wr_rd_dm_bank_0_data,
1078 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1079 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1080 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1082 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0_wl_1;
1083 writel(rwcfg->lfsr_wr_rd_bank_0_data,
1084 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1085 writel(rwcfg->lfsr_wr_rd_bank_0_nop,
1086 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1088 } else if (rw_wl_nop_cycles == 0) {
1090 * CNTR 2 - We want to skip the NOP operation and go straight
1091 * to the DQS enable instruction. We set the counter to a large
1092 * number so that the jump is always taken.
1094 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1096 /* CNTR 3 - Not used */
1098 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
1099 writel(rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
1100 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1102 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
1103 writel(rwcfg->lfsr_wr_rd_bank_0_dqs,
1104 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1108 * CNTR 2 - In this case we want to execute the next instruction
1109 * and NOT take the jump. So we set the counter to 0. The jump
1110 * address doesn't count.
1112 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1113 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1116 * CNTR 3 - Set the nop counter to the number of cycles we
1117 * need to loop for, minus 1.
1119 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1121 mcc_instruction = rwcfg->lfsr_wr_rd_dm_bank_0;
1122 writel(rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1123 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1125 mcc_instruction = rwcfg->lfsr_wr_rd_bank_0;
1126 writel(rwcfg->lfsr_wr_rd_bank_0_nop,
1127 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1131 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1132 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1134 if (quick_write_mode)
1135 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1137 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1139 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1142 * CNTR 1 - This is used to ensure enough time elapses
1143 * for read data to come back.
1145 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1148 writel(rwcfg->lfsr_wr_rd_dm_bank_0_wait,
1149 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1151 writel(rwcfg->lfsr_wr_rd_bank_0_wait,
1152 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1155 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1156 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1161 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
1162 * @rank_bgn: Rank number
1163 * @write_group: Write Group
1165 * @all_correct: All bits must be correct in the mask
1166 * @bit_chk: Resulting bit mask after the test
1167 * @all_ranks: Test all ranks
1169 * Test writes, can check for a single bit pass or multiple bit pass.
1172 rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
1173 const u32 use_dm, const u32 all_correct,
1174 u32 *bit_chk, const u32 all_ranks)
1176 const u32 rank_end = all_ranks ?
1177 rwcfg->mem_number_of_ranks :
1178 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1179 const u32 shift_ratio = rwcfg->mem_dq_per_write_dqs /
1180 rwcfg->mem_virtual_groups_per_write_dqs;
1181 const u32 correct_mask_vg = param->write_correct_mask_vg;
1183 u32 tmp_bit_chk, base_rw_mgr;
1186 *bit_chk = param->write_correct_mask;
1188 for (r = rank_bgn; r < rank_end; r++) {
1190 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1193 for (vg = rwcfg->mem_virtual_groups_per_write_dqs - 1;
1195 /* Reset the FIFOs to get pointers to known state. */
1196 writel(0, &phy_mgr_cmd->fifo_reset);
1198 rw_mgr_mem_calibrate_write_test_issue(
1200 rwcfg->mem_virtual_groups_per_write_dqs + vg,
1203 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1204 tmp_bit_chk <<= shift_ratio;
1205 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1208 *bit_chk &= tmp_bit_chk;
1211 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1213 debug_cond(DLEVEL >= 2,
1214 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1215 write_group, use_dm, *bit_chk,
1216 param->write_correct_mask,
1217 *bit_chk == param->write_correct_mask);
1218 return *bit_chk == param->write_correct_mask;
1220 debug_cond(DLEVEL >= 2,
1221 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1222 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1223 return *bit_chk != 0x00;
1228 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1229 * @rank_bgn: Rank number
1230 * @group: Read/Write Group
1231 * @all_ranks: Test all ranks
1233 * Performs a guaranteed read on the patterns we are going to use during a
1234 * read test to ensure memory works.
1237 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1238 const u32 all_ranks)
1240 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1241 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1242 const u32 addr_offset =
1243 (group * rwcfg->mem_virtual_groups_per_read_dqs) << 2;
1244 const u32 rank_end = all_ranks ?
1245 rwcfg->mem_number_of_ranks :
1246 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1247 const u32 shift_ratio = rwcfg->mem_dq_per_read_dqs /
1248 rwcfg->mem_virtual_groups_per_read_dqs;
1249 const u32 correct_mask_vg = param->read_correct_mask_vg;
1251 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1255 bit_chk = param->read_correct_mask;
1257 for (r = rank_bgn; r < rank_end; r++) {
1259 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1261 /* Load up a constant bursts of read commands */
1262 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1263 writel(rwcfg->guaranteed_read,
1264 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1266 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1267 writel(rwcfg->guaranteed_read_cont,
1268 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1271 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1;
1273 /* Reset the FIFOs to get pointers to known state. */
1274 writel(0, &phy_mgr_cmd->fifo_reset);
1275 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1276 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1277 writel(rwcfg->guaranteed_read,
1278 addr + addr_offset + (vg << 2));
1280 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1281 tmp_bit_chk <<= shift_ratio;
1282 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1285 bit_chk &= tmp_bit_chk;
1288 writel(rwcfg->clear_dqs_enable, addr + (group << 2));
1290 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1292 if (bit_chk != param->read_correct_mask)
1295 debug_cond(DLEVEL >= 1,
1296 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1297 __func__, __LINE__, group, bit_chk,
1298 param->read_correct_mask, ret);
1304 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1305 * @rank_bgn: Rank number
1306 * @all_ranks: Test all ranks
1308 * Load up the patterns we are going to use during a read test.
1310 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1311 const int all_ranks)
1313 const u32 rank_end = all_ranks ?
1314 rwcfg->mem_number_of_ranks :
1315 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1318 debug("%s:%d\n", __func__, __LINE__);
1320 for (r = rank_bgn; r < rank_end; r++) {
1322 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1324 /* Load up a constant bursts */
1325 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1327 writel(rwcfg->guaranteed_write_wait0,
1328 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1330 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1332 writel(rwcfg->guaranteed_write_wait1,
1333 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1335 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1337 writel(rwcfg->guaranteed_write_wait2,
1338 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1340 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1342 writel(rwcfg->guaranteed_write_wait3,
1343 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1345 writel(rwcfg->guaranteed_write, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1346 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1349 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1353 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1354 * @rank_bgn: Rank number
1355 * @group: Read/Write group
1356 * @num_tries: Number of retries of the test
1357 * @all_correct: All bits must be correct in the mask
1358 * @bit_chk: Resulting bit mask after the test
1359 * @all_groups: Test all R/W groups
1360 * @all_ranks: Test all ranks
1362 * Try a read and see if it returns correct data back. Test has dummy reads
1363 * inserted into the mix used to align DQS enable. Test has more thorough
1364 * checks than the regular read test.
1367 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1368 const u32 num_tries, const u32 all_correct,
1370 const u32 all_groups, const u32 all_ranks)
1372 const u32 rank_end = all_ranks ? rwcfg->mem_number_of_ranks :
1373 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1374 const u32 quick_read_mode =
1375 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1376 misccfg->enable_super_quick_calibration);
1377 u32 correct_mask_vg = param->read_correct_mask_vg;
1384 *bit_chk = param->read_correct_mask;
1386 for (r = rank_bgn; r < rank_end; r++) {
1388 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1390 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1392 writel(rwcfg->read_b2b_wait1,
1393 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1395 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1396 writel(rwcfg->read_b2b_wait2,
1397 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1399 if (quick_read_mode)
1400 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1401 /* need at least two (1+1) reads to capture failures */
1402 else if (all_groups)
1403 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1405 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1407 writel(rwcfg->read_b2b,
1408 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1410 writel(rwcfg->mem_if_read_dqs_width *
1411 rwcfg->mem_virtual_groups_per_read_dqs - 1,
1412 &sdr_rw_load_mgr_regs->load_cntr3);
1414 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1416 writel(rwcfg->read_b2b,
1417 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1420 for (vg = rwcfg->mem_virtual_groups_per_read_dqs - 1; vg >= 0;
1422 /* Reset the FIFOs to get pointers to known state. */
1423 writel(0, &phy_mgr_cmd->fifo_reset);
1424 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1425 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1428 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1429 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1431 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1432 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1435 writel(rwcfg->read_b2b, addr +
1437 rwcfg->mem_virtual_groups_per_read_dqs +
1440 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1441 tmp_bit_chk <<= rwcfg->mem_dq_per_read_dqs /
1442 rwcfg->mem_virtual_groups_per_read_dqs;
1443 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1446 *bit_chk &= tmp_bit_chk;
1449 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1450 writel(rwcfg->clear_dqs_enable, addr + (group << 2));
1452 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1455 ret = (*bit_chk == param->read_correct_mask);
1456 debug_cond(DLEVEL >= 2,
1457 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1458 __func__, __LINE__, group, all_groups, *bit_chk,
1459 param->read_correct_mask, ret);
1461 ret = (*bit_chk != 0x00);
1462 debug_cond(DLEVEL >= 2,
1463 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1464 __func__, __LINE__, group, all_groups, *bit_chk,
1472 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1473 * @grp: Read/Write group
1474 * @num_tries: Number of retries of the test
1475 * @all_correct: All bits must be correct in the mask
1476 * @all_groups: Test all R/W groups
1478 * Perform a READ test across all memory ranks.
1481 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1482 const u32 all_correct,
1483 const u32 all_groups)
1486 return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1487 &bit_chk, all_groups, 1);
1491 * rw_mgr_incr_vfifo() - Increase VFIFO value
1492 * @grp: Read/Write group
1494 * Increase VFIFO value.
1496 static void rw_mgr_incr_vfifo(const u32 grp)
1498 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1502 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1503 * @grp: Read/Write group
1505 * Decrease VFIFO value.
1507 static void rw_mgr_decr_vfifo(const u32 grp)
1511 for (i = 0; i < misccfg->read_valid_fifo_size - 1; i++)
1512 rw_mgr_incr_vfifo(grp);
1516 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1517 * @grp: Read/Write group
1519 * Push VFIFO until a failing read happens.
1521 static int find_vfifo_failing_read(const u32 grp)
1523 u32 v, ret, fail_cnt = 0;
1525 for (v = 0; v < misccfg->read_valid_fifo_size; v++) {
1526 debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
1527 __func__, __LINE__, v);
1528 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1537 /* Fiddle with FIFO. */
1538 rw_mgr_incr_vfifo(grp);
1541 /* No failing read found! Something must have gone wrong. */
1542 debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1547 * sdr_find_phase_delay() - Find DQS enable phase or delay
1548 * @working: If 1, look for working phase/delay, if 0, look for non-working
1549 * @delay: If 1, look for delay, if 0, look for phase
1550 * @grp: Read/Write group
1551 * @work: Working window position
1552 * @work_inc: Working window increment
1553 * @pd: DQS Phase/Delay Iterator
1555 * Find working or non-working DQS enable phase setting.
1557 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1558 u32 *work, const u32 work_inc, u32 *pd)
1560 const u32 max = delay ? iocfg->dqs_en_delay_max :
1561 iocfg->dqs_en_phase_max;
1564 for (; *pd <= max; (*pd)++) {
1566 scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1568 scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1570 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1585 * sdr_find_phase() - Find DQS enable phase
1586 * @working: If 1, look for working phase, if 0, look for non-working phase
1587 * @grp: Read/Write group
1588 * @work: Working window position
1590 * @p: DQS Phase Iterator
1592 * Find working or non-working DQS enable phase setting.
1594 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1597 const u32 end = misccfg->read_valid_fifo_size + (working ? 0 : 1);
1600 for (; *i < end; (*i)++) {
1604 ret = sdr_find_phase_delay(working, 0, grp, work,
1605 iocfg->delay_per_opa_tap, p);
1609 if (*p > iocfg->dqs_en_phase_max) {
1610 /* Fiddle with FIFO. */
1611 rw_mgr_incr_vfifo(grp);
1621 * sdr_working_phase() - Find working DQS enable phase
1622 * @grp: Read/Write group
1623 * @work_bgn: Working window start position
1624 * @d: dtaps output value
1625 * @p: DQS Phase Iterator
1628 * Find working DQS enable phase setting.
1630 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1633 const u32 dtaps_per_ptap = iocfg->delay_per_opa_tap /
1634 iocfg->delay_per_dqs_en_dchain_tap;
1639 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1641 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1642 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1645 *work_bgn += iocfg->delay_per_dqs_en_dchain_tap;
1648 /* Cannot find working solution */
1649 debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1650 __func__, __LINE__);
1655 * sdr_backup_phase() - Find DQS enable backup phase
1656 * @grp: Read/Write group
1657 * @work_bgn: Working window start position
1658 * @p: DQS Phase Iterator
1660 * Find DQS enable backup phase setting.
1662 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1667 /* Special case code for backing up a phase */
1669 *p = iocfg->dqs_en_phase_max;
1670 rw_mgr_decr_vfifo(grp);
1674 tmp_delay = *work_bgn - iocfg->delay_per_opa_tap;
1675 scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1677 for (d = 0; d <= iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
1679 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1681 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1684 *work_bgn = tmp_delay;
1688 tmp_delay += iocfg->delay_per_dqs_en_dchain_tap;
1691 /* Restore VFIFO to old state before we decremented it (if needed). */
1693 if (*p > iocfg->dqs_en_phase_max) {
1695 rw_mgr_incr_vfifo(grp);
1698 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1702 * sdr_nonworking_phase() - Find non-working DQS enable phase
1703 * @grp: Read/Write group
1704 * @work_end: Working window end position
1705 * @p: DQS Phase Iterator
1708 * Find non-working DQS enable phase setting.
1710 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1715 *work_end += iocfg->delay_per_opa_tap;
1716 if (*p > iocfg->dqs_en_phase_max) {
1717 /* Fiddle with FIFO. */
1719 rw_mgr_incr_vfifo(grp);
1722 ret = sdr_find_phase(0, grp, work_end, i, p);
1724 /* Cannot see edge of failing read. */
1725 debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
1726 __func__, __LINE__);
1733 * sdr_find_window_center() - Find center of the working DQS window.
1734 * @grp: Read/Write group
1735 * @work_bgn: First working settings
1736 * @work_end: Last working settings
1738 * Find center of the working DQS enable window.
1740 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1747 work_mid = (work_bgn + work_end) / 2;
1749 debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1750 work_bgn, work_end, work_mid);
1751 /* Get the middle delay to be less than a VFIFO delay */
1752 tmp_delay = (iocfg->dqs_en_phase_max + 1) * iocfg->delay_per_opa_tap;
1754 debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
1755 work_mid %= tmp_delay;
1756 debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
1758 tmp_delay = rounddown(work_mid, iocfg->delay_per_opa_tap);
1759 if (tmp_delay > iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap)
1760 tmp_delay = iocfg->dqs_en_phase_max * iocfg->delay_per_opa_tap;
1761 p = tmp_delay / iocfg->delay_per_opa_tap;
1763 debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1765 d = DIV_ROUND_UP(work_mid - tmp_delay,
1766 iocfg->delay_per_dqs_en_dchain_tap);
1767 if (d > iocfg->dqs_en_delay_max)
1768 d = iocfg->dqs_en_delay_max;
1769 tmp_delay += d * iocfg->delay_per_dqs_en_dchain_tap;
1771 debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1773 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1774 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1777 * push vfifo until we can successfully calibrate. We can do this
1778 * because the largest possible margin in 1 VFIFO cycle.
1780 for (i = 0; i < misccfg->read_valid_fifo_size; i++) {
1781 debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
1782 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1785 debug_cond(DLEVEL >= 2,
1786 "%s:%d center: found: ptap=%u dtap=%u\n",
1787 __func__, __LINE__, p, d);
1791 /* Fiddle with FIFO. */
1792 rw_mgr_incr_vfifo(grp);
1795 debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
1796 __func__, __LINE__);
1801 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1802 * @grp: Read/Write Group
1804 * Find a good DQS enable to use.
1806 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1810 u32 work_bgn, work_end;
1811 u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
1814 debug("%s:%d %u\n", __func__, __LINE__, grp);
1816 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1818 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1819 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1821 /* Step 0: Determine number of delay taps for each phase tap. */
1822 dtaps_per_ptap = iocfg->delay_per_opa_tap /
1823 iocfg->delay_per_dqs_en_dchain_tap;
1825 /* Step 1: First push vfifo until we get a failing read. */
1826 find_vfifo_failing_read(grp);
1828 /* Step 2: Find first working phase, increment in ptaps. */
1830 ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1834 work_end = work_bgn;
1837 * If d is 0 then the working window covers a phase tap and we can
1838 * follow the old procedure. Otherwise, we've found the beginning
1839 * and we need to increment the dtaps until we find the end.
1843 * Step 3a: If we have room, back off by one and
1844 * increment in dtaps.
1846 sdr_backup_phase(grp, &work_bgn, &p);
1849 * Step 4a: go forward from working phase to non working
1850 * phase, increment in ptaps.
1852 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1856 /* Step 5a: Back off one from last, increment in dtaps. */
1858 /* Special case code for backing up a phase */
1860 p = iocfg->dqs_en_phase_max;
1861 rw_mgr_decr_vfifo(grp);
1866 work_end -= iocfg->delay_per_opa_tap;
1867 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1871 debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
1872 __func__, __LINE__, p);
1875 /* The dtap increment to find the failing edge is done here. */
1876 sdr_find_phase_delay(0, 1, grp, &work_end,
1877 iocfg->delay_per_dqs_en_dchain_tap, &d);
1879 /* Go back to working dtap */
1881 work_end -= iocfg->delay_per_dqs_en_dchain_tap;
1883 debug_cond(DLEVEL >= 2,
1884 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1885 __func__, __LINE__, p, d - 1, work_end);
1887 if (work_end < work_bgn) {
1889 debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
1890 __func__, __LINE__);
1894 debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
1895 __func__, __LINE__, work_bgn, work_end);
1898 * We need to calculate the number of dtaps that equal a ptap.
1899 * To do that we'll back up a ptap and re-find the edge of the
1900 * window using dtaps
1902 debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1903 __func__, __LINE__);
1905 /* Special case code for backing up a phase */
1907 p = iocfg->dqs_en_phase_max;
1908 rw_mgr_decr_vfifo(grp);
1909 debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
1910 __func__, __LINE__, p);
1913 debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
1914 __func__, __LINE__, p);
1917 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1920 * Increase dtap until we first see a passing read (in case the
1921 * window is smaller than a ptap), and then a failing read to
1922 * mark the edge of the window again.
1925 /* Find a passing read. */
1926 debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
1927 __func__, __LINE__);
1929 initial_failing_dtap = d;
1931 found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1932 if (found_passing_read) {
1933 /* Find a failing read. */
1934 debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
1935 __func__, __LINE__);
1937 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1940 debug_cond(DLEVEL >= 1,
1941 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1942 __func__, __LINE__);
1946 * The dynamically calculated dtaps_per_ptap is only valid if we
1947 * found a passing/failing read. If we didn't, it means d hit the max
1948 * (iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
1949 * statically calculated value.
1951 if (found_passing_read && found_failing_read)
1952 dtaps_per_ptap = d - initial_failing_dtap;
1954 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1955 debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1956 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1958 /* Step 6: Find the centre of the window. */
1959 ret = sdr_find_window_center(grp, work_bgn, work_end);
1965 * search_stop_check() - Check if the detected edge is valid
1966 * @write: Perform read (Stage 2) or write (Stage 3) calibration
1968 * @rank_bgn: Rank number
1969 * @write_group: Write Group
1970 * @read_group: Read Group
1971 * @bit_chk: Resulting bit mask after the test
1972 * @sticky_bit_chk: Resulting sticky bit mask after the test
1973 * @use_read_test: Perform read test
1975 * Test if the found edge is valid.
1977 static u32 search_stop_check(const int write, const int d, const int rank_bgn,
1978 const u32 write_group, const u32 read_group,
1979 u32 *bit_chk, u32 *sticky_bit_chk,
1980 const u32 use_read_test)
1982 const u32 ratio = rwcfg->mem_if_read_dqs_width /
1983 rwcfg->mem_if_write_dqs_width;
1984 const u32 correct_mask = write ? param->write_correct_mask :
1985 param->read_correct_mask;
1986 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
1987 rwcfg->mem_dq_per_read_dqs;
1990 * Stop searching when the read test doesn't pass AND when
1991 * we've seen a passing read on every bit.
1993 if (write) { /* WRITE-ONLY */
1994 ret = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1997 } else if (use_read_test) { /* READ-ONLY */
1998 ret = !rw_mgr_mem_calibrate_read_test(rank_bgn, read_group,
2000 PASS_ONE_BIT, bit_chk,
2002 } else { /* READ-ONLY */
2003 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 0,
2004 PASS_ONE_BIT, bit_chk, 0);
2005 *bit_chk = *bit_chk >> (per_dqs *
2006 (read_group - (write_group * ratio)));
2007 ret = (*bit_chk == 0);
2009 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2010 ret = ret && (*sticky_bit_chk == correct_mask);
2011 debug_cond(DLEVEL >= 2,
2012 "%s:%d center(left): dtap=%u => %u == %u && %u",
2013 __func__, __LINE__, d,
2014 *sticky_bit_chk, correct_mask, ret);
2019 * search_left_edge() - Find left edge of DQ/DQS working phase
2020 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2021 * @rank_bgn: Rank number
2022 * @write_group: Write Group
2023 * @read_group: Read Group
2024 * @test_bgn: Rank number to begin the test
2025 * @sticky_bit_chk: Resulting sticky bit mask after the test
2026 * @left_edge: Left edge of the DQ/DQS phase
2027 * @right_edge: Right edge of the DQ/DQS phase
2028 * @use_read_test: Perform read test
2030 * Find left edge of DQ/DQS working phase.
2032 static void search_left_edge(const int write, const int rank_bgn,
2033 const u32 write_group, const u32 read_group, const u32 test_bgn,
2034 u32 *sticky_bit_chk,
2035 int *left_edge, int *right_edge, const u32 use_read_test)
2037 const u32 delay_max = write ? iocfg->io_out1_delay_max :
2038 iocfg->io_in_delay_max;
2039 const u32 dqs_max = write ? iocfg->io_out1_delay_max :
2040 iocfg->dqs_in_delay_max;
2041 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2042 rwcfg->mem_dq_per_read_dqs;
2046 for (d = 0; d <= dqs_max; d++) {
2048 scc_mgr_apply_group_dq_out1_delay(d);
2050 scc_mgr_apply_group_dq_in_delay(test_bgn, d);
2052 writel(0, &sdr_scc_mgr->update);
2054 stop = search_stop_check(write, d, rank_bgn, write_group,
2055 read_group, &bit_chk, sticky_bit_chk,
2061 for (i = 0; i < per_dqs; i++) {
2064 * Remember a passing test as
2070 * If a left edge has not been seen
2071 * yet, then a future passing test
2072 * will mark this edge as the right
2075 if (left_edge[i] == delay_max + 1)
2076 right_edge[i] = -(d + 1);
2082 /* Reset DQ delay chains to 0 */
2084 scc_mgr_apply_group_dq_out1_delay(0);
2086 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2088 *sticky_bit_chk = 0;
2089 for (i = per_dqs - 1; i >= 0; i--) {
2090 debug_cond(DLEVEL >= 2,
2091 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2092 __func__, __LINE__, i, left_edge[i],
2096 * Check for cases where we haven't found the left edge,
2097 * which makes our assignment of the the right edge invalid.
2098 * Reset it to the illegal value.
2100 if ((left_edge[i] == delay_max + 1) &&
2101 (right_edge[i] != delay_max + 1)) {
2102 right_edge[i] = delay_max + 1;
2103 debug_cond(DLEVEL >= 2,
2104 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2105 __func__, __LINE__, i, right_edge[i]);
2110 * READ: except for bits where we have seen both
2111 * the left and right edge.
2112 * WRITE: except for bits where we have seen the
2115 *sticky_bit_chk <<= 1;
2117 if (left_edge[i] != delay_max + 1)
2118 *sticky_bit_chk |= 1;
2120 if ((left_edge[i] != delay_max + 1) &&
2121 (right_edge[i] != delay_max + 1))
2122 *sticky_bit_chk |= 1;
2128 * search_right_edge() - Find right edge of DQ/DQS working phase
2129 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2130 * @rank_bgn: Rank number
2131 * @write_group: Write Group
2132 * @read_group: Read Group
2133 * @start_dqs: DQS start phase
2134 * @start_dqs_en: DQS enable start phase
2135 * @sticky_bit_chk: Resulting sticky bit mask after the test
2136 * @left_edge: Left edge of the DQ/DQS phase
2137 * @right_edge: Right edge of the DQ/DQS phase
2138 * @use_read_test: Perform read test
2140 * Find right edge of DQ/DQS working phase.
2142 static int search_right_edge(const int write, const int rank_bgn,
2143 const u32 write_group, const u32 read_group,
2144 const int start_dqs, const int start_dqs_en,
2145 u32 *sticky_bit_chk,
2146 int *left_edge, int *right_edge, const u32 use_read_test)
2148 const u32 delay_max = write ? iocfg->io_out1_delay_max :
2149 iocfg->io_in_delay_max;
2150 const u32 dqs_max = write ? iocfg->io_out1_delay_max :
2151 iocfg->dqs_in_delay_max;
2152 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2153 rwcfg->mem_dq_per_read_dqs;
2157 for (d = 0; d <= dqs_max - start_dqs; d++) {
2158 if (write) { /* WRITE-ONLY */
2159 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2161 } else { /* READ-ONLY */
2162 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2163 if (iocfg->shift_dqs_en_when_shift_dqs) {
2164 u32 delay = d + start_dqs_en;
2165 if (delay > iocfg->dqs_en_delay_max)
2166 delay = iocfg->dqs_en_delay_max;
2167 scc_mgr_set_dqs_en_delay(read_group, delay);
2169 scc_mgr_load_dqs(read_group);
2172 writel(0, &sdr_scc_mgr->update);
2174 stop = search_stop_check(write, d, rank_bgn, write_group,
2175 read_group, &bit_chk, sticky_bit_chk,
2178 if (write && (d == 0)) { /* WRITE-ONLY */
2179 for (i = 0; i < rwcfg->mem_dq_per_write_dqs;
2182 * d = 0 failed, but it passed when
2183 * testing the left edge, so it must be
2184 * marginal, set it to -1
2186 if (right_edge[i] == delay_max + 1 &&
2187 left_edge[i] != delay_max + 1)
2195 for (i = 0; i < per_dqs; i++) {
2198 * Remember a passing test as
2205 * If a right edge has not
2206 * been seen yet, then a future
2207 * passing test will mark this
2208 * edge as the left edge.
2210 if (right_edge[i] == delay_max + 1)
2211 left_edge[i] = -(d + 1);
2214 * d = 0 failed, but it passed
2215 * when testing the left edge,
2216 * so it must be marginal, set
2219 if (right_edge[i] == delay_max + 1 &&
2220 left_edge[i] != delay_max + 1)
2223 * If a right edge has not been
2224 * seen yet, then a future
2225 * passing test will mark this
2226 * edge as the left edge.
2228 else if (right_edge[i] == delay_max + 1)
2229 left_edge[i] = -(d + 1);
2233 debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
2234 __func__, __LINE__, d);
2235 debug_cond(DLEVEL >= 2,
2236 "bit_chk_test=%i left_edge[%u]: %d ",
2237 bit_chk & 1, i, left_edge[i]);
2238 debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
2244 /* Check that all bits have a window */
2245 for (i = 0; i < per_dqs; i++) {
2246 debug_cond(DLEVEL >= 2,
2247 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2248 __func__, __LINE__, i, left_edge[i],
2250 if ((left_edge[i] == dqs_max + 1) ||
2251 (right_edge[i] == dqs_max + 1))
2252 return i + 1; /* FIXME: If we fail, retval > 0 */
2259 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2260 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2261 * @left_edge: Left edge of the DQ/DQS phase
2262 * @right_edge: Right edge of the DQ/DQS phase
2263 * @mid_min: Best DQ/DQS phase middle setting
2265 * Find index and value of the middle of the DQ/DQS working phase.
2267 static int get_window_mid_index(const int write, int *left_edge,
2268 int *right_edge, int *mid_min)
2270 const u32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2271 rwcfg->mem_dq_per_read_dqs;
2272 int i, mid, min_index;
2274 /* Find middle of window for each DQ bit */
2275 *mid_min = left_edge[0] - right_edge[0];
2277 for (i = 1; i < per_dqs; i++) {
2278 mid = left_edge[i] - right_edge[i];
2279 if (mid < *mid_min) {
2286 * -mid_min/2 represents the amount that we need to move DQS.
2287 * If mid_min is odd and positive we'll need to add one to make
2288 * sure the rounding in further calculations is correct (always
2289 * bias to the right), so just add 1 for all positive values.
2293 *mid_min = *mid_min / 2;
2295 debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2296 __func__, __LINE__, *mid_min, min_index);
2301 * center_dq_windows() - Center the DQ/DQS windows
2302 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2303 * @left_edge: Left edge of the DQ/DQS phase
2304 * @right_edge: Right edge of the DQ/DQS phase
2305 * @mid_min: Adjusted DQ/DQS phase middle setting
2306 * @orig_mid_min: Original DQ/DQS phase middle setting
2307 * @min_index: DQ/DQS phase middle setting index
2308 * @test_bgn: Rank number to begin the test
2309 * @dq_margin: Amount of shift for the DQ
2310 * @dqs_margin: Amount of shift for the DQS
2312 * Align the DQ/DQS windows in each group.
2314 static void center_dq_windows(const int write, int *left_edge, int *right_edge,
2315 const int mid_min, const int orig_mid_min,
2316 const int min_index, const int test_bgn,
2317 int *dq_margin, int *dqs_margin)
2319 const s32 delay_max = write ? iocfg->io_out1_delay_max :
2320 iocfg->io_in_delay_max;
2321 const s32 per_dqs = write ? rwcfg->mem_dq_per_write_dqs :
2322 rwcfg->mem_dq_per_read_dqs;
2323 const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2324 SCC_MGR_IO_IN_DELAY_OFFSET;
2325 const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2327 s32 temp_dq_io_delay1;
2330 /* Initialize data for export structures */
2331 *dqs_margin = delay_max + 1;
2332 *dq_margin = delay_max + 1;
2334 /* add delay to bring centre of all DQ windows to the same "level" */
2335 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2336 /* Use values before divide by 2 to reduce round off error */
2337 shift_dq = (left_edge[i] - right_edge[i] -
2338 (left_edge[min_index] - right_edge[min_index]))/2 +
2339 (orig_mid_min - mid_min);
2341 debug_cond(DLEVEL >= 2,
2342 "vfifo_center: before: shift_dq[%u]=%d\n",
2345 temp_dq_io_delay1 = readl(addr + (i << 2));
2347 if (shift_dq + temp_dq_io_delay1 > delay_max)
2348 shift_dq = delay_max - temp_dq_io_delay1;
2349 else if (shift_dq + temp_dq_io_delay1 < 0)
2350 shift_dq = -temp_dq_io_delay1;
2352 debug_cond(DLEVEL >= 2,
2353 "vfifo_center: after: shift_dq[%u]=%d\n",
2357 scc_mgr_set_dq_out1_delay(i,
2358 temp_dq_io_delay1 + shift_dq);
2360 scc_mgr_set_dq_in_delay(p,
2361 temp_dq_io_delay1 + shift_dq);
2365 debug_cond(DLEVEL >= 2,
2366 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2367 left_edge[i] - shift_dq + (-mid_min),
2368 right_edge[i] + shift_dq - (-mid_min));
2370 /* To determine values for export structures */
2371 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2372 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2374 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2375 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2380 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2381 * @rank_bgn: Rank number
2382 * @rw_group: Read/Write Group
2383 * @test_bgn: Rank at which the test begins
2384 * @use_read_test: Perform a read test
2385 * @update_fom: Update FOM
2387 * Per-bit deskew DQ and centering.
2389 static int rw_mgr_mem_calibrate_vfifo_center(const u32 rank_bgn,
2390 const u32 rw_group, const u32 test_bgn,
2391 const int use_read_test, const int update_fom)
2394 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2397 * Store these as signed since there are comparisons with
2401 int32_t left_edge[rwcfg->mem_dq_per_read_dqs];
2402 int32_t right_edge[rwcfg->mem_dq_per_read_dqs];
2403 int32_t orig_mid_min, mid_min;
2404 int32_t new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
2405 int32_t dq_margin, dqs_margin;
2409 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2411 start_dqs = readl(addr);
2412 if (iocfg->shift_dqs_en_when_shift_dqs)
2413 start_dqs_en = readl(addr - iocfg->dqs_en_delay_offset);
2415 /* set the left and right edge of each bit to an illegal value */
2416 /* use (iocfg->io_in_delay_max + 1) as an illegal value */
2418 for (i = 0; i < rwcfg->mem_dq_per_read_dqs; i++) {
2419 left_edge[i] = iocfg->io_in_delay_max + 1;
2420 right_edge[i] = iocfg->io_in_delay_max + 1;
2423 /* Search for the left edge of the window for each bit */
2424 search_left_edge(0, rank_bgn, rw_group, rw_group, test_bgn,
2426 left_edge, right_edge, use_read_test);
2429 /* Search for the right edge of the window for each bit */
2430 ret = search_right_edge(0, rank_bgn, rw_group, rw_group,
2431 start_dqs, start_dqs_en,
2433 left_edge, right_edge, use_read_test);
2436 * Restore delay chain settings before letting the loop
2437 * in rw_mgr_mem_calibrate_vfifo to retry different
2438 * dqs/ck relationships.
2440 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2441 if (iocfg->shift_dqs_en_when_shift_dqs)
2442 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2444 scc_mgr_load_dqs(rw_group);
2445 writel(0, &sdr_scc_mgr->update);
2447 debug_cond(DLEVEL >= 1,
2448 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2449 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2450 if (use_read_test) {
2451 set_failing_group_stage(rw_group *
2452 rwcfg->mem_dq_per_read_dqs + i,
2454 CAL_SUBSTAGE_VFIFO_CENTER);
2456 set_failing_group_stage(rw_group *
2457 rwcfg->mem_dq_per_read_dqs + i,
2458 CAL_STAGE_VFIFO_AFTER_WRITES,
2459 CAL_SUBSTAGE_VFIFO_CENTER);
2464 min_index = get_window_mid_index(0, left_edge, right_edge, &mid_min);
2466 /* Determine the amount we can change DQS (which is -mid_min) */
2467 orig_mid_min = mid_min;
2468 new_dqs = start_dqs - mid_min;
2469 if (new_dqs > iocfg->dqs_in_delay_max)
2470 new_dqs = iocfg->dqs_in_delay_max;
2471 else if (new_dqs < 0)
2474 mid_min = start_dqs - new_dqs;
2475 debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2478 if (iocfg->shift_dqs_en_when_shift_dqs) {
2479 if (start_dqs_en - mid_min > iocfg->dqs_en_delay_max)
2480 mid_min += start_dqs_en - mid_min -
2481 iocfg->dqs_en_delay_max;
2482 else if (start_dqs_en - mid_min < 0)
2483 mid_min += start_dqs_en - mid_min;
2485 new_dqs = start_dqs - mid_min;
2487 debug_cond(DLEVEL >= 1,
2488 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2490 iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
2493 /* Add delay to bring centre of all DQ windows to the same "level". */
2494 center_dq_windows(0, left_edge, right_edge, mid_min, orig_mid_min,
2495 min_index, test_bgn, &dq_margin, &dqs_margin);
2498 if (iocfg->shift_dqs_en_when_shift_dqs) {
2499 final_dqs_en = start_dqs_en - mid_min;
2500 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2501 scc_mgr_load_dqs(rw_group);
2505 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2506 scc_mgr_load_dqs(rw_group);
2507 debug_cond(DLEVEL >= 2,
2508 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2509 __func__, __LINE__, dq_margin, dqs_margin);
2512 * Do not remove this line as it makes sure all of our decisions
2513 * have been applied. Apply the update bit.
2515 writel(0, &sdr_scc_mgr->update);
2517 if ((dq_margin < 0) || (dqs_margin < 0))
2524 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2525 * @rw_group: Read/Write Group
2526 * @phase: DQ/DQS phase
2528 * Because initially no communication ca be reliably performed with the memory
2529 * device, the sequencer uses a guaranteed write mechanism to write data into
2530 * the memory device.
2532 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2537 /* Set a particular DQ/DQS phase. */
2538 scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2540 debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
2541 __func__, __LINE__, rw_group, phase);
2544 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2545 * Load up the patterns used by read calibration using the
2546 * current DQDQS phase.
2548 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2550 if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2554 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2555 * Back-to-Back reads of the patterns used for calibration.
2557 ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2559 debug_cond(DLEVEL >= 1,
2560 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2561 __func__, __LINE__, rw_group, phase);
2566 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2567 * @rw_group: Read/Write Group
2568 * @test_bgn: Rank at which the test begins
2570 * DQS enable calibration ensures reliable capture of the DQ signal without
2571 * glitches on the DQS line.
2573 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2577 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2578 * DQS and DQS Eanble Signal Relationships.
2581 /* We start at zero, so have one less dq to devide among */
2582 const u32 delay_step = iocfg->io_in_delay_max /
2583 (rwcfg->mem_dq_per_read_dqs - 1);
2587 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2589 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2590 for (r = 0; r < rwcfg->mem_number_of_ranks;
2591 r += NUM_RANKS_PER_SHADOW_REG) {
2592 for (i = 0, p = test_bgn, d = 0;
2593 i < rwcfg->mem_dq_per_read_dqs;
2594 i++, p++, d += delay_step) {
2595 debug_cond(DLEVEL >= 1,
2596 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2597 __func__, __LINE__, rw_group, r, i, p, d);
2599 scc_mgr_set_dq_in_delay(p, d);
2603 writel(0, &sdr_scc_mgr->update);
2607 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2608 * dq_in_delay values
2610 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2612 debug_cond(DLEVEL >= 1,
2613 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2614 __func__, __LINE__, rw_group, !ret);
2616 for (r = 0; r < rwcfg->mem_number_of_ranks;
2617 r += NUM_RANKS_PER_SHADOW_REG) {
2618 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2619 writel(0, &sdr_scc_mgr->update);
2626 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2627 * @rw_group: Read/Write Group
2628 * @test_bgn: Rank at which the test begins
2629 * @use_read_test: Perform a read test
2630 * @update_fom: Update FOM
2632 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2636 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2637 const int use_read_test,
2638 const int update_fom)
2641 int ret, grp_calibrated;
2645 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2646 * Read per-bit deskew can be done on a per shadow register basis.
2649 for (rank_bgn = 0, sr = 0;
2650 rank_bgn < rwcfg->mem_number_of_ranks;
2651 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2652 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2662 if (!grp_calibrated)
2669 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2670 * @rw_group: Read/Write Group
2671 * @test_bgn: Rank at which the test begins
2673 * Stage 1: Calibrate the read valid prediction FIFO.
2675 * This function implements UniPHY calibration Stage 1, as explained in
2676 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2678 * - read valid prediction will consist of finding:
2679 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2680 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2681 * - we also do a per-bit deskew on the DQ lines.
2683 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2687 u32 failed_substage;
2691 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2693 /* Update info for sims */
2694 reg_file_set_group(rw_group);
2695 reg_file_set_stage(CAL_STAGE_VFIFO);
2696 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2698 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2700 /* USER Determine number of delay taps for each phase tap. */
2701 dtaps_per_ptap = DIV_ROUND_UP(iocfg->delay_per_opa_tap,
2702 iocfg->delay_per_dqs_en_dchain_tap) - 1;
2704 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2706 * In RLDRAMX we may be messing the delay of pins in
2707 * the same write rw_group but outside of the current read
2708 * the rw_group, but that's ok because we haven't calibrated
2712 scc_mgr_apply_group_all_out_delay_add_all_ranks(
2716 for (p = 0; p <= iocfg->dqdqs_out_phase_max; p++) {
2717 /* 1) Guaranteed Write */
2718 ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2722 /* 2) DQS Enable Calibration */
2723 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2726 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2730 /* 3) Centering DQ/DQS */
2732 * If doing read after write calibration, do not update
2733 * FOM now. Do it then.
2735 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2738 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2747 /* Calibration Stage 1 failed. */
2748 set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2751 /* Calibration Stage 1 completed OK. */
2754 * Reset the delay chains back to zero if they have moved > 1
2755 * (check for > 1 because loop will increase d even when pass in
2759 scc_mgr_zero_group(rw_group, 1);
2765 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2766 * @rw_group: Read/Write Group
2767 * @test_bgn: Rank at which the test begins
2769 * Stage 3: DQ/DQS Centering.
2771 * This function implements UniPHY calibration Stage 3, as explained in
2772 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2774 static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
2779 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2781 /* Update info for sims. */
2782 reg_file_set_group(rw_group);
2783 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2784 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2786 ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
2788 set_failing_group_stage(rw_group,
2789 CAL_STAGE_VFIFO_AFTER_WRITES,
2790 CAL_SUBSTAGE_VFIFO_CENTER);
2795 * rw_mgr_mem_calibrate_lfifo() - Minimize latency
2797 * Stage 4: Minimize latency.
2799 * This function implements UniPHY calibration Stage 4, as explained in
2800 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2801 * Calibrate LFIFO to find smallest read latency.
2803 static u32 rw_mgr_mem_calibrate_lfifo(void)
2807 debug("%s:%d\n", __func__, __LINE__);
2809 /* Update info for sims. */
2810 reg_file_set_stage(CAL_STAGE_LFIFO);
2811 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2813 /* Load up the patterns used by read calibration for all ranks */
2814 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2817 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2818 debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
2819 __func__, __LINE__, gbl->curr_read_lat);
2821 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
2827 * Reduce read latency and see if things are
2828 * working correctly.
2830 gbl->curr_read_lat--;
2831 } while (gbl->curr_read_lat > 0);
2833 /* Reset the fifos to get pointers to known state. */
2834 writel(0, &phy_mgr_cmd->fifo_reset);
2837 /* Add a fudge factor to the read latency that was determined */
2838 gbl->curr_read_lat += 2;
2839 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2840 debug_cond(DLEVEL >= 2,
2841 "%s:%d lfifo: success: using read_lat=%u\n",
2842 __func__, __LINE__, gbl->curr_read_lat);
2844 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2845 CAL_SUBSTAGE_READ_LATENCY);
2847 debug_cond(DLEVEL >= 2,
2848 "%s:%d lfifo: failed at initial read_lat=%u\n",
2849 __func__, __LINE__, gbl->curr_read_lat);
2856 * search_window() - Search for the/part of the window with DM/DQS shift
2857 * @search_dm: If 1, search for the DM shift, if 0, search for DQS shift
2858 * @rank_bgn: Rank number
2859 * @write_group: Write Group
2860 * @bgn_curr: Current window begin
2861 * @end_curr: Current window end
2862 * @bgn_best: Current best window begin
2863 * @end_best: Current best window end
2864 * @win_best: Size of the best window
2865 * @new_dqs: New DQS value (only applicable if search_dm = 0).
2867 * Search for the/part of the window with DM/DQS shift.
2869 static void search_window(const int search_dm,
2870 const u32 rank_bgn, const u32 write_group,
2871 int *bgn_curr, int *end_curr, int *bgn_best,
2872 int *end_best, int *win_best, int new_dqs)
2875 const int max = iocfg->io_out1_delay_max - new_dqs;
2878 /* Search for the/part of the window with DM/DQS shift. */
2879 for (di = max; di >= 0; di -= DELTA_D) {
2882 scc_mgr_apply_group_dm_out1_delay(d);
2884 /* For DQS, we go from 0...max */
2887 * Note: This only shifts DQS, so are we limiting
2888 * ourselves to width of DQ unnecessarily.
2890 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2894 writel(0, &sdr_scc_mgr->update);
2896 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2897 PASS_ALL_BITS, &bit_chk,
2899 /* Set current end of the window. */
2900 *end_curr = search_dm ? -d : d;
2903 * If a starting edge of our window has not been seen
2904 * this is our current start of the DM window.
2906 if (*bgn_curr == iocfg->io_out1_delay_max + 1)
2907 *bgn_curr = search_dm ? -d : d;
2910 * If current window is bigger than best seen.
2911 * Set best seen to be current window.
2913 if ((*end_curr - *bgn_curr + 1) > *win_best) {
2914 *win_best = *end_curr - *bgn_curr + 1;
2915 *bgn_best = *bgn_curr;
2916 *end_best = *end_curr;
2919 /* We just saw a failing test. Reset temp edge. */
2920 *bgn_curr = iocfg->io_out1_delay_max + 1;
2921 *end_curr = iocfg->io_out1_delay_max + 1;
2923 /* Early exit is only applicable to DQS. */
2928 * Early exit optimization: if the remaining delay
2929 * chain space is less than already seen largest
2930 * window we can exit.
2932 if (*win_best - 1 > iocfg->io_out1_delay_max - new_dqs - d)
2939 * rw_mgr_mem_calibrate_writes_center() - Center all windows
2940 * @rank_bgn: Rank number
2941 * @write_group: Write group
2942 * @test_bgn: Rank at which the test begins
2944 * Center all windows. Do per-bit-deskew to possibly increase size of
2948 rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
2954 int left_edge[rwcfg->mem_dq_per_write_dqs];
2955 int right_edge[rwcfg->mem_dq_per_write_dqs];
2957 int mid_min, orig_mid_min;
2958 int new_dqs, start_dqs;
2959 int dq_margin, dqs_margin, dm_margin;
2960 int bgn_curr = iocfg->io_out1_delay_max + 1;
2961 int end_curr = iocfg->io_out1_delay_max + 1;
2962 int bgn_best = iocfg->io_out1_delay_max + 1;
2963 int end_best = iocfg->io_out1_delay_max + 1;
2968 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2972 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
2973 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
2974 (rwcfg->mem_dq_per_write_dqs << 2));
2976 /* Per-bit deskew. */
2979 * Set the left and right edge of each bit to an illegal value.
2980 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
2983 for (i = 0; i < rwcfg->mem_dq_per_write_dqs; i++) {
2984 left_edge[i] = iocfg->io_out1_delay_max + 1;
2985 right_edge[i] = iocfg->io_out1_delay_max + 1;
2988 /* Search for the left edge of the window for each bit. */
2989 search_left_edge(1, rank_bgn, write_group, 0, test_bgn,
2991 left_edge, right_edge, 0);
2993 /* Search for the right edge of the window for each bit. */
2994 ret = search_right_edge(1, rank_bgn, write_group, 0,
2997 left_edge, right_edge, 0);
2999 set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
3000 CAL_SUBSTAGE_WRITES_CENTER);
3004 min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
3006 /* Determine the amount we can change DQS (which is -mid_min). */
3007 orig_mid_min = mid_min;
3008 new_dqs = start_dqs;
3010 debug_cond(DLEVEL >= 1,
3011 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3012 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3014 /* Add delay to bring centre of all DQ windows to the same "level". */
3015 center_dq_windows(1, left_edge, right_edge, mid_min, orig_mid_min,
3016 min_index, 0, &dq_margin, &dqs_margin);
3019 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3020 writel(0, &sdr_scc_mgr->update);
3023 debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3026 * Set the left and right edge of each bit to an illegal value.
3027 * Use (iocfg->io_out1_delay_max + 1) as an illegal value.
3029 left_edge[0] = iocfg->io_out1_delay_max + 1;
3030 right_edge[0] = iocfg->io_out1_delay_max + 1;
3032 /* Search for the/part of the window with DM shift. */
3033 search_window(1, rank_bgn, write_group, &bgn_curr, &end_curr,
3034 &bgn_best, &end_best, &win_best, 0);
3036 /* Reset DM delay chains to 0. */
3037 scc_mgr_apply_group_dm_out1_delay(0);
3040 * Check to see if the current window nudges up aganist 0 delay.
3041 * If so we need to continue the search by shifting DQS otherwise DQS
3042 * search begins as a new search.
3044 if (end_curr != 0) {
3045 bgn_curr = iocfg->io_out1_delay_max + 1;
3046 end_curr = iocfg->io_out1_delay_max + 1;
3049 /* Search for the/part of the window with DQS shifts. */
3050 search_window(0, rank_bgn, write_group, &bgn_curr, &end_curr,
3051 &bgn_best, &end_best, &win_best, new_dqs);
3053 /* Assign left and right edge for cal and reporting. */
3054 left_edge[0] = -1 * bgn_best;
3055 right_edge[0] = end_best;
3057 debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
3058 __func__, __LINE__, left_edge[0], right_edge[0]);
3060 /* Move DQS (back to orig). */
3061 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3065 /* Find middle of window for the DM bit. */
3066 mid = (left_edge[0] - right_edge[0]) / 2;
3068 /* Only move right, since we are not moving DQS/DQ. */
3072 /* dm_marign should fail if we never find a window. */
3076 dm_margin = left_edge[0] - mid;
3078 scc_mgr_apply_group_dm_out1_delay(mid);
3079 writel(0, &sdr_scc_mgr->update);
3081 debug_cond(DLEVEL >= 2,
3082 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3083 __func__, __LINE__, left_edge[0], right_edge[0],
3085 /* Export values. */
3086 gbl->fom_out += dq_margin + dqs_margin;
3088 debug_cond(DLEVEL >= 2,
3089 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3090 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3093 * Do not remove this line as it makes sure all of our
3094 * decisions have been applied.
3096 writel(0, &sdr_scc_mgr->update);
3098 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3105 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3106 * @rank_bgn: Rank number
3107 * @group: Read/Write Group
3108 * @test_bgn: Rank at which the test begins
3110 * Stage 2: Write Calibration Part One.
3112 * This function implements UniPHY calibration Stage 2, as explained in
3113 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3115 static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
3120 /* Update info for sims */
3121 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3123 reg_file_set_group(group);
3124 reg_file_set_stage(CAL_STAGE_WRITES);
3125 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3127 ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
3129 set_failing_group_stage(group, CAL_STAGE_WRITES,
3130 CAL_SUBSTAGE_WRITES_CENTER);
3136 * mem_precharge_and_activate() - Precharge all banks and activate
3138 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3140 static void mem_precharge_and_activate(void)
3144 for (r = 0; r < rwcfg->mem_number_of_ranks; r++) {
3146 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3148 /* Precharge all banks. */
3149 writel(rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3150 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3152 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3153 writel(rwcfg->activate_0_and_1_wait1,
3154 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3156 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3157 writel(rwcfg->activate_0_and_1_wait2,
3158 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3160 /* Activate rows. */
3161 writel(rwcfg->activate_0_and_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3162 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3167 * mem_init_latency() - Configure memory RLAT and WLAT settings
3169 * Configure memory RLAT and WLAT parameters.
3171 static void mem_init_latency(void)
3174 * For AV/CV, LFIFO is hardened and always runs at full rate
3175 * so max latency in AFI clocks, used here, is correspondingly
3178 const u32 max_latency = (1 << misccfg->max_latency_count_width) - 1;
3181 debug("%s:%d\n", __func__, __LINE__);
3184 * Read in write latency.
3185 * WL for Hard PHY does not include additive latency.
3187 wlat = readl(&data_mgr->t_wl_add);
3188 wlat += readl(&data_mgr->mem_t_add);
3190 gbl->rw_wl_nop_cycles = wlat - 1;
3192 /* Read in readl latency. */
3193 rlat = readl(&data_mgr->t_rl_add);
3195 /* Set a pretty high read latency initially. */
3196 gbl->curr_read_lat = rlat + 16;
3197 if (gbl->curr_read_lat > max_latency)
3198 gbl->curr_read_lat = max_latency;
3200 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3202 /* Advertise write latency. */
3203 writel(wlat, &phy_mgr_cfg->afi_wlat);
3207 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3209 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3211 static void mem_skip_calibrate(void)
3216 debug("%s:%d\n", __func__, __LINE__);
3217 /* Need to update every shadow register set used by the interface */
3218 for (r = 0; r < rwcfg->mem_number_of_ranks;
3219 r += NUM_RANKS_PER_SHADOW_REG) {
3221 * Set output phase alignment settings appropriate for
3224 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3225 scc_mgr_set_dqs_en_phase(i, 0);
3226 if (iocfg->dll_chain_length == 6)
3227 scc_mgr_set_dqdqs_output_phase(i, 6);
3229 scc_mgr_set_dqdqs_output_phase(i, 7);
3233 * Write data arrives to the I/O two cycles before write
3234 * latency is reached (720 deg).
3235 * -> due to bit-slip in a/c bus
3236 * -> to allow board skew where dqs is longer than ck
3237 * -> how often can this happen!?
3238 * -> can claim back some ptaps for high freq
3239 * support if we can relax this, but i digress...
3241 * The write_clk leads mem_ck by 90 deg
3242 * The minimum ptap of the OPA is 180 deg
3243 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3244 * The write_clk is always delayed by 2 ptaps
3246 * Hence, to make DQS aligned to CK, we need to delay
3248 * (720 - 90 - 180 - 2) *
3249 * (360 / iocfg->dll_chain_length)
3251 * Dividing the above by (360 / iocfg->dll_chain_length)
3252 * gives us the number of ptaps, which simplies to:
3254 * (1.25 * iocfg->dll_chain_length - 2)
3256 scc_mgr_set_dqdqs_output_phase(i,
3257 ((125 * iocfg->dll_chain_length) / 100) - 2);
3259 writel(0xff, &sdr_scc_mgr->dqs_ena);
3260 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3262 for (i = 0; i < rwcfg->mem_if_write_dqs_width; i++) {
3263 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3264 SCC_MGR_GROUP_COUNTER_OFFSET);
3266 writel(0xff, &sdr_scc_mgr->dq_ena);
3267 writel(0xff, &sdr_scc_mgr->dm_ena);
3268 writel(0, &sdr_scc_mgr->update);
3271 /* Compensate for simulation model behaviour */
3272 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3273 scc_mgr_set_dqs_bus_in_delay(i, 10);
3274 scc_mgr_load_dqs(i);
3276 writel(0, &sdr_scc_mgr->update);
3279 * ArriaV has hard FIFOs that can only be initialized by incrementing
3282 vfifo_offset = misccfg->calib_vfifo_offset;
3283 for (j = 0; j < vfifo_offset; j++)
3284 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3285 writel(0, &phy_mgr_cmd->fifo_reset);
3288 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3289 * setting from generation-time constant.
3291 gbl->curr_read_lat = misccfg->calib_lfifo_offset;
3292 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3296 * mem_calibrate() - Memory calibration entry point.
3298 * Perform memory calibration.
3300 static u32 mem_calibrate(void)
3304 u32 write_group, write_test_bgn;
3305 u32 read_group, read_test_bgn;
3306 u32 run_groups, current_run;
3307 u32 failing_groups = 0;
3308 u32 group_failed = 0;
3310 const u32 rwdqs_ratio = rwcfg->mem_if_read_dqs_width /
3311 rwcfg->mem_if_write_dqs_width;
3313 debug("%s:%d\n", __func__, __LINE__);
3315 /* Initialize the data settings */
3316 gbl->error_substage = CAL_SUBSTAGE_NIL;
3317 gbl->error_stage = CAL_STAGE_NIL;
3318 gbl->error_group = 0xff;
3322 /* Initialize WLAT and RLAT. */
3325 /* Initialize bit slips. */
3326 mem_precharge_and_activate();
3328 for (i = 0; i < rwcfg->mem_if_read_dqs_width; i++) {
3329 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3330 SCC_MGR_GROUP_COUNTER_OFFSET);
3331 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3333 scc_mgr_set_hhp_extras();
3335 scc_set_bypass_mode(i);
3338 /* Calibration is skipped. */
3339 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3341 * Set VFIFO and LFIFO to instant-on settings in skip
3344 mem_skip_calibrate();
3347 * Do not remove this line as it makes sure all of our
3348 * decisions have been applied.
3350 writel(0, &sdr_scc_mgr->update);
3354 /* Calibration is not skipped. */
3355 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3357 * Zero all delay chain/phase settings for all
3358 * groups and all shadow register sets.
3364 for (write_group = 0, write_test_bgn = 0; write_group
3365 < rwcfg->mem_if_write_dqs_width; write_group++,
3366 write_test_bgn += rwcfg->mem_dq_per_write_dqs) {
3367 /* Initialize the group failure */
3370 current_run = run_groups & ((1 <<
3371 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3372 run_groups = run_groups >>
3373 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3375 if (current_run == 0)
3378 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3379 SCC_MGR_GROUP_COUNTER_OFFSET);
3380 scc_mgr_zero_group(write_group, 0);
3382 for (read_group = write_group * rwdqs_ratio,
3384 read_group < (write_group + 1) * rwdqs_ratio;
3386 read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
3387 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3390 /* Calibrate the VFIFO */
3391 if (rw_mgr_mem_calibrate_vfifo(read_group,
3395 if (!(gbl->phy_debug_mode_flags &
3396 PHY_DEBUG_SWEEP_ALL_GROUPS))
3399 /* The group failed, we're done. */
3403 /* Calibrate the output side */
3404 for (rank_bgn = 0, sr = 0;
3405 rank_bgn < rwcfg->mem_number_of_ranks;
3406 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3407 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3410 /* Not needed in quick mode! */
3411 if (STATIC_CALIB_STEPS &
3412 CALIB_SKIP_DELAY_SWEEPS)
3415 /* Calibrate WRITEs */
3416 if (!rw_mgr_mem_calibrate_writes(rank_bgn,
3422 if (!(gbl->phy_debug_mode_flags &
3423 PHY_DEBUG_SWEEP_ALL_GROUPS))
3427 /* Some group failed, we're done. */
3431 for (read_group = write_group * rwdqs_ratio,
3433 read_group < (write_group + 1) * rwdqs_ratio;
3435 read_test_bgn += rwcfg->mem_dq_per_read_dqs) {
3436 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3439 if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
3443 if (!(gbl->phy_debug_mode_flags &
3444 PHY_DEBUG_SWEEP_ALL_GROUPS))
3447 /* The group failed, we're done. */
3451 /* No group failed, continue as usual. */
3454 grp_failed: /* A group failed, increment the counter. */
3459 * USER If there are any failing groups then report
3462 if (failing_groups != 0)
3465 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3468 /* Calibrate the LFIFO */
3469 if (!rw_mgr_mem_calibrate_lfifo())
3474 * Do not remove this line as it makes sure all of our decisions
3475 * have been applied.
3477 writel(0, &sdr_scc_mgr->update);
3482 * run_mem_calibrate() - Perform memory calibration
3484 * This function triggers the entire memory calibration procedure.
3486 static int run_mem_calibrate(void)
3491 debug("%s:%d\n", __func__, __LINE__);
3493 /* Reset pass/fail status shown on afi_cal_success/fail */
3494 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3496 /* Stop tracking manager. */
3497 ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
3498 writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
3499 &sdr_ctrl->ctrl_cfg);
3501 phy_mgr_initialize();
3502 rw_mgr_mem_initialize();
3504 /* Perform the actual memory calibration. */
3505 pass = mem_calibrate();
3507 mem_precharge_and_activate();
3508 writel(0, &phy_mgr_cmd->fifo_reset);
3511 rw_mgr_mem_handoff();
3513 * In Hard PHY this is a 2-bit control:
3515 * 1: DDIO Mux Select
3517 writel(0x2, &phy_mgr_cfg->mux_sel);
3519 /* Start tracking manager. */
3520 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
3526 * debug_mem_calibrate() - Report result of memory calibration
3527 * @pass: Value indicating whether calibration passed or failed
3529 * This function reports the results of the memory calibration
3530 * and writes debug information into the register file.
3532 static void debug_mem_calibrate(int pass)
3537 printf("%s: CALIBRATION PASSED\n", __FILE__);
3542 if (gbl->fom_in > 0xff)
3545 if (gbl->fom_out > 0xff)
3546 gbl->fom_out = 0xff;
3548 /* Update the FOM in the register file */
3549 debug_info = gbl->fom_in;
3550 debug_info |= gbl->fom_out << 8;
3551 writel(debug_info, &sdr_reg_file->fom);
3553 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3554 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3556 printf("%s: CALIBRATION FAILED\n", __FILE__);
3558 debug_info = gbl->error_stage;
3559 debug_info |= gbl->error_substage << 8;
3560 debug_info |= gbl->error_group << 16;
3562 writel(debug_info, &sdr_reg_file->failing_stage);
3563 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3564 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3566 /* Update the failing group/stage in the register file */
3567 debug_info = gbl->error_stage;
3568 debug_info |= gbl->error_substage << 8;
3569 debug_info |= gbl->error_group << 16;
3570 writel(debug_info, &sdr_reg_file->failing_stage);
3573 printf("%s: Calibration complete\n", __FILE__);
3577 * hc_initialize_rom_data() - Initialize ROM data
3579 * Initialize ROM data.
3581 static void hc_initialize_rom_data(void)
3583 unsigned int nelem = 0;
3584 const u32 *rom_init;
3587 socfpga_get_seq_inst_init(&rom_init, &nelem);
3588 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3589 for (i = 0; i < nelem; i++)
3590 writel(rom_init[i], addr + (i << 2));
3592 socfpga_get_seq_ac_init(&rom_init, &nelem);
3593 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3594 for (i = 0; i < nelem; i++)
3595 writel(rom_init[i], addr + (i << 2));
3599 * initialize_reg_file() - Initialize SDR register file
3601 * Initialize SDR register file.
3603 static void initialize_reg_file(void)
3605 /* Initialize the register file with the correct data */
3606 writel(misccfg->reg_file_init_seq_signature, &sdr_reg_file->signature);
3607 writel(0, &sdr_reg_file->debug_data_addr);
3608 writel(0, &sdr_reg_file->cur_stage);
3609 writel(0, &sdr_reg_file->fom);
3610 writel(0, &sdr_reg_file->failing_stage);
3611 writel(0, &sdr_reg_file->debug1);
3612 writel(0, &sdr_reg_file->debug2);
3616 * initialize_hps_phy() - Initialize HPS PHY
3618 * Initialize HPS PHY.
3620 static void initialize_hps_phy(void)
3624 * Tracking also gets configured here because it's in the
3627 u32 trk_sample_count = 7500;
3628 u32 trk_long_idle_sample_count = (10 << 16) | 100;
3630 * Format is number of outer loops in the 16 MSB, sample
3635 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3636 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3637 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3638 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3639 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3640 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3642 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3643 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3645 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3646 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3648 writel(reg, &sdr_ctrl->phy_ctrl0);
3651 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3653 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3654 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3655 trk_long_idle_sample_count);
3656 writel(reg, &sdr_ctrl->phy_ctrl1);
3659 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3660 trk_long_idle_sample_count >>
3661 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3662 writel(reg, &sdr_ctrl->phy_ctrl2);
3666 * initialize_tracking() - Initialize tracking
3668 * Initialize the register file with usable initial data.
3670 static void initialize_tracking(void)
3673 * Initialize the register file with the correct data.
3674 * Compute usable version of value in case we skip full
3675 * computation later.
3677 writel(DIV_ROUND_UP(iocfg->delay_per_opa_tap,
3678 iocfg->delay_per_dchain_tap) - 1,
3679 &sdr_reg_file->dtaps_per_ptap);
3681 /* trk_sample_count */
3682 writel(7500, &sdr_reg_file->trk_sample_count);
3684 /* longidle outer loop [15:0] */
3685 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3688 * longidle sample count [31:24]
3689 * trfc, worst case of 933Mhz 4Gb [23:16]
3690 * trcd, worst case [15:8]
3693 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3694 &sdr_reg_file->delays);
3697 writel((rwcfg->idle << 24) | (rwcfg->activate_1 << 16) |
3698 (rwcfg->sgle_read << 8) | (rwcfg->precharge_all << 0),
3699 &sdr_reg_file->trk_rw_mgr_addr);
3701 writel(rwcfg->mem_if_read_dqs_width,
3702 &sdr_reg_file->trk_read_dqs_width);
3705 writel((rwcfg->refresh_all << 24) | (1000 << 0),
3706 &sdr_reg_file->trk_rfsh);
3709 int sdram_calibration_full(void)
3711 struct param_type my_param;
3712 struct gbl_type my_gbl;
3715 memset(&my_param, 0, sizeof(my_param));
3716 memset(&my_gbl, 0, sizeof(my_gbl));
3721 rwcfg = socfpga_get_sdram_rwmgr_config();
3722 iocfg = socfpga_get_sdram_io_config();
3723 misccfg = socfpga_get_sdram_misc_config();
3725 /* Set the calibration enabled by default */
3726 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3728 * Only sweep all groups (regardless of fail state) by default
3729 * Set enabled read test by default.
3731 #if DISABLE_GUARANTEED_READ
3732 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3734 /* Initialize the register file */
3735 initialize_reg_file();
3737 /* Initialize any PHY CSR */
3738 initialize_hps_phy();
3740 scc_mgr_initialize();
3742 initialize_tracking();
3744 printf("%s: Preparing to start memory calibration\n", __FILE__);
3746 debug("%s:%d\n", __func__, __LINE__);
3747 debug_cond(DLEVEL >= 1,
3748 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3749 rwcfg->mem_number_of_ranks, rwcfg->mem_number_of_cs_per_dimm,
3750 rwcfg->mem_dq_per_read_dqs, rwcfg->mem_dq_per_write_dqs,
3751 rwcfg->mem_virtual_groups_per_read_dqs,
3752 rwcfg->mem_virtual_groups_per_write_dqs);
3753 debug_cond(DLEVEL >= 1,
3754 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3755 rwcfg->mem_if_read_dqs_width, rwcfg->mem_if_write_dqs_width,
3756 rwcfg->mem_data_width, rwcfg->mem_data_mask_width,
3757 iocfg->delay_per_opa_tap, iocfg->delay_per_dchain_tap);
3758 debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
3759 iocfg->delay_per_dqs_en_dchain_tap, iocfg->dll_chain_length);
3760 debug_cond(DLEVEL >= 1,
3761 "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3762 iocfg->dqs_en_phase_max, iocfg->dqdqs_out_phase_max,
3763 iocfg->dqs_en_delay_max, iocfg->dqs_in_delay_max);
3764 debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3765 iocfg->io_in_delay_max, iocfg->io_out1_delay_max,
3766 iocfg->io_out2_delay_max);
3767 debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3768 iocfg->dqs_in_reserve, iocfg->dqs_out_reserve);
3770 hc_initialize_rom_data();
3772 /* update info for sims */
3773 reg_file_set_stage(CAL_STAGE_NIL);
3774 reg_file_set_group(0);
3777 * Load global needed for those actions that require
3778 * some dynamic calibration support.
3780 dyn_calib_steps = STATIC_CALIB_STEPS;
3782 * Load global to allow dynamic selection of delay loop settings
3783 * based on calibration mode.
3785 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3786 skip_delay_mask = 0xff;
3788 skip_delay_mask = 0x0;
3790 pass = run_mem_calibrate();
3791 debug_mem_calibrate(pass);