drivers/ddr/altera/sequencer.c

   1 /*
   2  * Copyright Altera Corporation (C) 2012-2015
   3  *
   4  * SPDX-License-Identifier:    BSD-3-Clause
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/sdram.h>
  10 #include <errno.h>
  11 #include "sequencer.h"
  12 #include "sequencer_auto.h"
  13 #include "sequencer_auto_ac_init.h"
  14 #include "sequencer_auto_inst_init.h"
  15 #include "sequencer_defines.h"
  16
  17 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
  18         (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
  19
  20 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
  21         (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
  22
  23 static struct socfpga_sdr_reg_file *sdr_reg_file =
  24         (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
  25
  26 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
  27         (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
  28
  29 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
  30         (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
  31
  32 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
  33         (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
  34
  35 static struct socfpga_data_mgr *data_mgr =
  36         (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
  37
  38 static struct socfpga_sdr_ctrl *sdr_ctrl =
  39         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  40
  41 #define DELTA_D         1
  42
  43 /*
  44  * In order to reduce ROM size, most of the selectable calibration steps are
  45  * decided at compile time based on the user's calibration mode selection,
  46  * as captured by the STATIC_CALIB_STEPS selection below.
  47  *
  48  * However, to support simulation-time selection of fast simulation mode, where
  49  * we skip everything except the bare minimum, we need a few of the steps to
  50  * be dynamic.  In those cases, we either use the DYNAMIC_CALIB_STEPS for the
  51  * check, which is based on the rtl-supplied value, or we dynamically compute
  52  * the value to use based on the dynamically-chosen calibration mode
  53  */
  54
  55 #define DLEVEL 0
  56 #define STATIC_IN_RTL_SIM 0
  57 #define STATIC_SKIP_DELAY_LOOPS 0
  58
  59 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
  60         STATIC_SKIP_DELAY_LOOPS)
  61
  62 /* calibration steps requested by the rtl */
  63 uint16_t dyn_calib_steps;
  64
  65 /*
  66  * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
  67  * instead of static, we use boolean logic to select between
  68  * non-skip and skip values
  69  *
  70  * The mask is set to include all bits when not-skipping, but is
  71  * zero when skipping
  72  */
  73
  74 uint16_t skip_delay_mask;       /* mask off bits when skipping/not-skipping */
  75
  76 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
  77         ((non_skip_value) & skip_delay_mask)
  78
  79 struct gbl_type *gbl;
  80 struct param_type *param;
  81 uint32_t curr_shadow_reg;
  82
  83 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
  84         uint32_t write_group, uint32_t use_dm,
  85         uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
  86
  87 static void set_failing_group_stage(uint32_t group, uint32_t stage,
  88         uint32_t substage)
  89 {
  90         /*
  91          * Only set the global stage if there was not been any other
  92          * failing group
  93          */
  94         if (gbl->error_stage == CAL_STAGE_NIL)  {
  95                 gbl->error_substage = substage;
  96                 gbl->error_stage = stage;
  97                 gbl->error_group = group;
  98         }
  99 }
 100
 101 static void reg_file_set_group(u16 set_group)
 102 {
 103         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
 104 }
 105
 106 static void reg_file_set_stage(u8 set_stage)
 107 {
 108         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
 109 }
 110
 111 static void reg_file_set_sub_stage(u8 set_sub_stage)
 112 {
 113         set_sub_stage &= 0xff;
 114         clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
 115 }
 116
 117 /**
 118  * phy_mgr_initialize() - Initialize PHY Manager
 119  *
 120  * Initialize PHY Manager.
 121  */
 122 static void phy_mgr_initialize(void)
 123 {
 124         u32 ratio;
 125
 126         debug("%s:%d\n", __func__, __LINE__);
 127         /* Calibration has control over path to memory */
 128         /*
 129          * In Hard PHY this is a 2-bit control:
 130          * 0: AFI Mux Select
 131          * 1: DDIO Mux Select
 132          */
 133         writel(0x3, &phy_mgr_cfg->mux_sel);
 134
 135         /* USER memory clock is not stable we begin initialization  */
 136         writel(0, &phy_mgr_cfg->reset_mem_stbl);
 137
 138         /* USER calibration status all set to zero */
 139         writel(0, &phy_mgr_cfg->cal_status);
 140
 141         writel(0, &phy_mgr_cfg->cal_debug_info);
 142
 143         /* Init params only if we do NOT skip calibration. */
 144         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
 145                 return;
 146
 147         ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
 148                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
 149         param->read_correct_mask_vg = (1 << ratio) - 1;
 150         param->write_correct_mask_vg = (1 << ratio) - 1;
 151         param->read_correct_mask = (1 << RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
 152         param->write_correct_mask = (1 << RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
 153         ratio = RW_MGR_MEM_DATA_WIDTH /
 154                 RW_MGR_MEM_DATA_MASK_WIDTH;
 155         param->dm_correct_mask = (1 << ratio) - 1;
 156 }
 157
 158 /**
 159  * set_rank_and_odt_mask() - Set Rank and ODT mask
 160  * @rank:       Rank mask
 161  * @odt_mode:   ODT mode, OFF or READ_WRITE
 162  *
 163  * Set Rank and ODT mask (On-Die Termination).
 164  */
 165 static void set_rank_and_odt_mask(const u32 rank, const u32 odt_mode)
 166 {
 167         u32 odt_mask_0 = 0;
 168         u32 odt_mask_1 = 0;
 169         u32 cs_and_odt_mask;
 170
 171         if (odt_mode == RW_MGR_ODT_MODE_OFF) {
 172                 odt_mask_0 = 0x0;
 173                 odt_mask_1 = 0x0;
 174         } else {        /* RW_MGR_ODT_MODE_READ_WRITE */
 175                 switch (RW_MGR_MEM_NUMBER_OF_RANKS) {
 176                 case 1: /* 1 Rank */
 177                         /* Read: ODT = 0 ; Write: ODT = 1 */
 178                         odt_mask_0 = 0x0;
 179                         odt_mask_1 = 0x1;
 180                         break;
 181                 case 2: /* 2 Ranks */
 182                         if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
 183                                 /*
 184                                  * - Dual-Slot , Single-Rank (1 CS per DIMM)
 185                                  *   OR
 186                                  * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
 187                                  *
 188                                  * Since MEM_NUMBER_OF_RANKS is 2, they
 189                                  * are both single rank with 2 CS each
 190                                  * (special for RDIMM).
 191                                  *
 192                                  * Read: Turn on ODT on the opposite rank
 193                                  * Write: Turn on ODT on all ranks
 194                                  */
 195                                 odt_mask_0 = 0x3 & ~(1 << rank);
 196                                 odt_mask_1 = 0x3;
 197                         } else {
 198                                 /*
 199                                  * - Single-Slot , Dual-Rank (2 CS per DIMM)
 200                                  *
 201                                  * Read: Turn on ODT off on all ranks
 202                                  * Write: Turn on ODT on active rank
 203                                  */
 204                                 odt_mask_0 = 0x0;
 205                                 odt_mask_1 = 0x3 & (1 << rank);
 206                         }
 207                         break;
 208                 case 4: /* 4 Ranks */
 209                         /* Read:
 210                          * ----------+-----------------------+
 211                          *           |         ODT           |
 212                          * Read From +-----------------------+
 213                          *   Rank    |  3  |  2  |  1  |  0  |
 214                          * ----------+-----+-----+-----+-----+
 215                          *     0     |  0  |  1  |  0  |  0  |
 216                          *     1     |  1  |  0  |  0  |  0  |
 217                          *     2     |  0  |  0  |  0  |  1  |
 218                          *     3     |  0  |  0  |  1  |  0  |
 219                          * ----------+-----+-----+-----+-----+
 220                          *
 221                          * Write:
 222                          * ----------+-----------------------+
 223                          *           |         ODT           |
 224                          * Write To  +-----------------------+
 225                          *   Rank    |  3  |  2  |  1  |  0  |
 226                          * ----------+-----+-----+-----+-----+
 227                          *     0     |  0  |  1  |  0  |  1  |
 228                          *     1     |  1  |  0  |  1  |  0  |
 229                          *     2     |  0  |  1  |  0  |  1  |
 230                          *     3     |  1  |  0  |  1  |  0  |
 231                          * ----------+-----+-----+-----+-----+
 232                          */
 233                         switch (rank) {
 234                         case 0:
 235                                 odt_mask_0 = 0x4;
 236                                 odt_mask_1 = 0x5;
 237                                 break;
 238                         case 1:
 239                                 odt_mask_0 = 0x8;
 240                                 odt_mask_1 = 0xA;
 241                                 break;
 242                         case 2:
 243                                 odt_mask_0 = 0x1;
 244                                 odt_mask_1 = 0x5;
 245                                 break;
 246                         case 3:
 247                                 odt_mask_0 = 0x2;
 248                                 odt_mask_1 = 0xA;
 249                                 break;
 250                         }
 251                         break;
 252                 }
 253         }
 254
 255         cs_and_odt_mask = (0xFF & ~(1 << rank)) |
 256                           ((0xFF & odt_mask_0) << 8) |
 257                           ((0xFF & odt_mask_1) << 16);
 258         writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 259                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 260 }
 261
 262 /**
 263  * scc_mgr_set() - Set SCC Manager register
 264  * @off:        Base offset in SCC Manager space
 265  * @grp:        Read/Write group
 266  * @val:        Value to be set
 267  *
 268  * This function sets the SCC Manager (Scan Chain Control Manager) register.
 269  */
 270 static void scc_mgr_set(u32 off, u32 grp, u32 val)
 271 {
 272         writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
 273 }
 274
 275 /**
 276  * scc_mgr_initialize() - Initialize SCC Manager registers
 277  *
 278  * Initialize SCC Manager registers.
 279  */
 280 static void scc_mgr_initialize(void)
 281 {
 282         /*
 283          * Clear register file for HPS. 16 (2^4) is the size of the
 284          * full register file in the scc mgr:
 285          *      RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
 286          *                             MEM_IF_READ_DQS_WIDTH - 1);
 287          */
 288         int i;
 289
 290         for (i = 0; i < 16; i++) {
 291                 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
 292                            __func__, __LINE__, i);
 293                 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
 294         }
 295 }
 296
 297 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
 298 {
 299         scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
 300 }
 301
 302 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
 303 {
 304         scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
 305 }
 306
 307 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
 308 {
 309         scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
 310 }
 311
 312 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
 313 {
 314         scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
 315 }
 316
 317 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
 318 {
 319         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 320                     delay);
 321 }
 322
 323 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
 324 {
 325         scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
 326 }
 327
 328 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
 329 {
 330         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
 331 }
 332
 333 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
 334 {
 335         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
 336                     delay);
 337 }
 338
 339 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
 340 {
 341         scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
 342                     RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
 343                     delay);
 344 }
 345
 346 /* load up dqs config settings */
 347 static void scc_mgr_load_dqs(uint32_t dqs)
 348 {
 349         writel(dqs, &sdr_scc_mgr->dqs_ena);
 350 }
 351
 352 /* load up dqs io config settings */
 353 static void scc_mgr_load_dqs_io(void)
 354 {
 355         writel(0, &sdr_scc_mgr->dqs_io_ena);
 356 }
 357
 358 /* load up dq config settings */
 359 static void scc_mgr_load_dq(uint32_t dq_in_group)
 360 {
 361         writel(dq_in_group, &sdr_scc_mgr->dq_ena);
 362 }
 363
 364 /* load up dm config settings */
 365 static void scc_mgr_load_dm(uint32_t dm)
 366 {
 367         writel(dm, &sdr_scc_mgr->dm_ena);
 368 }
 369
 370 /**
 371  * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
 372  * @off:        Base offset in SCC Manager space
 373  * @grp:        Read/Write group
 374  * @val:        Value to be set
 375  * @update:     If non-zero, trigger SCC Manager update for all ranks
 376  *
 377  * This function sets the SCC Manager (Scan Chain Control Manager) register
 378  * and optionally triggers the SCC update for all ranks.
 379  */
 380 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
 381                                   const int update)
 382 {
 383         u32 r;
 384
 385         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 386              r += NUM_RANKS_PER_SHADOW_REG) {
 387                 scc_mgr_set(off, grp, val);
 388
 389                 if (update || (r == 0)) {
 390                         writel(grp, &sdr_scc_mgr->dqs_ena);
 391                         writel(0, &sdr_scc_mgr->update);
 392                 }
 393         }
 394 }
 395
 396 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
 397 {
 398         /*
 399          * USER although the h/w doesn't support different phases per
 400          * shadow register, for simplicity our scc manager modeling
 401          * keeps different phase settings per shadow reg, and it's
 402          * important for us to keep them in sync to match h/w.
 403          * for efficiency, the scan chain update should occur only
 404          * once to sr0.
 405          */
 406         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
 407                               read_group, phase, 0);
 408 }
 409
 410 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
 411                                                      uint32_t phase)
 412 {
 413         /*
 414          * USER although the h/w doesn't support different phases per
 415          * shadow register, for simplicity our scc manager modeling
 416          * keeps different phase settings per shadow reg, and it's
 417          * important for us to keep them in sync to match h/w.
 418          * for efficiency, the scan chain update should occur only
 419          * once to sr0.
 420          */
 421         scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
 422                               write_group, phase, 0);
 423 }
 424
 425 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
 426                                                uint32_t delay)
 427 {
 428         /*
 429          * In shadow register mode, the T11 settings are stored in
 430          * registers in the core, which are updated by the DQS_ENA
 431          * signals. Not issuing the SCC_MGR_UPD command allows us to
 432          * save lots of rank switching overhead, by calling
 433          * select_shadow_regs_for_update with update_scan_chains
 434          * set to 0.
 435          */
 436         scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
 437                               read_group, delay, 1);
 438         writel(0, &sdr_scc_mgr->update);
 439 }
 440
 441 /**
 442  * scc_mgr_set_oct_out1_delay() - Set OCT output delay
 443  * @write_group:        Write group
 444  * @delay:              Delay value
 445  *
 446  * This function sets the OCT output delay in SCC manager.
 447  */
 448 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
 449 {
 450         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 451                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 452         const int base = write_group * ratio;
 453         int i;
 454         /*
 455          * Load the setting in the SCC manager
 456          * Although OCT affects only write data, the OCT delay is controlled
 457          * by the DQS logic block which is instantiated once per read group.
 458          * For protocols where a write group consists of multiple read groups,
 459          * the setting must be set multiple times.
 460          */
 461         for (i = 0; i < ratio; i++)
 462                 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
 463 }
 464
 465 /**
 466  * scc_mgr_set_hhp_extras() - Set HHP extras.
 467  *
 468  * Load the fixed setting in the SCC manager HHP extras.
 469  */
 470 static void scc_mgr_set_hhp_extras(void)
 471 {
 472         /*
 473          * Load the fixed setting in the SCC manager
 474          * bits: 0:0 = 1'b1     - DQS bypass
 475          * bits: 1:1 = 1'b1     - DQ bypass
 476          * bits: 4:2 = 3'b001   - rfifo_mode
 477          * bits: 6:5 = 2'b01    - rfifo clock_select
 478          * bits: 7:7 = 1'b0     - separate gating from ungating setting
 479          * bits: 8:8 = 1'b0     - separate OE from Output delay setting
 480          */
 481         const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
 482                           (1 << 2) | (1 << 1) | (1 << 0);
 483         const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
 484                          SCC_MGR_HHP_GLOBALS_OFFSET |
 485                          SCC_MGR_HHP_EXTRAS_OFFSET;
 486
 487         debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n",
 488                    __func__, __LINE__);
 489         writel(value, addr);
 490         debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
 491                    __func__, __LINE__);
 492 }
 493
 494 /**
 495  * scc_mgr_zero_all() - Zero all DQS config
 496  *
 497  * Zero all DQS config.
 498  */
 499 static void scc_mgr_zero_all(void)
 500 {
 501         int i, r;
 502
 503         /*
 504          * USER Zero all DQS config settings, across all groups and all
 505          * shadow registers
 506          */
 507         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 508              r += NUM_RANKS_PER_SHADOW_REG) {
 509                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
 510                         /*
 511                          * The phases actually don't exist on a per-rank basis,
 512                          * but there's no harm updating them several times, so
 513                          * let's keep the code simple.
 514                          */
 515                         scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
 516                         scc_mgr_set_dqs_en_phase(i, 0);
 517                         scc_mgr_set_dqs_en_delay(i, 0);
 518                 }
 519
 520                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
 521                         scc_mgr_set_dqdqs_output_phase(i, 0);
 522                         /* Arria V/Cyclone V don't have out2. */
 523                         scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
 524                 }
 525         }
 526
 527         /* Multicast to all DQS group enables. */
 528         writel(0xff, &sdr_scc_mgr->dqs_ena);
 529         writel(0, &sdr_scc_mgr->update);
 530 }
 531
 532 /**
 533  * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
 534  * @write_group:        Write group
 535  *
 536  * Set bypass mode and trigger SCC update.
 537  */
 538 static void scc_set_bypass_mode(const u32 write_group)
 539 {
 540         /* Multicast to all DQ enables. */
 541         writel(0xff, &sdr_scc_mgr->dq_ena);
 542         writel(0xff, &sdr_scc_mgr->dm_ena);
 543
 544         /* Update current DQS IO enable. */
 545         writel(0, &sdr_scc_mgr->dqs_io_ena);
 546
 547         /* Update the DQS logic. */
 548         writel(write_group, &sdr_scc_mgr->dqs_ena);
 549
 550         /* Hit update. */
 551         writel(0, &sdr_scc_mgr->update);
 552 }
 553
 554 /**
 555  * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
 556  * @write_group:        Write group
 557  *
 558  * Load DQS settings for Write Group, do not trigger SCC update.
 559  */
 560 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
 561 {
 562         const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
 563                           RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
 564         const int base = write_group * ratio;
 565         int i;
 566         /*
 567          * Load the setting in the SCC manager
 568          * Although OCT affects only write data, the OCT delay is controlled
 569          * by the DQS logic block which is instantiated once per read group.
 570          * For protocols where a write group consists of multiple read groups,
 571          * the setting must be set multiple times.
 572          */
 573         for (i = 0; i < ratio; i++)
 574                 writel(base + i, &sdr_scc_mgr->dqs_ena);
 575 }
 576
 577 /**
 578  * scc_mgr_zero_group() - Zero all configs for a group
 579  *
 580  * Zero DQ, DM, DQS and OCT configs for a group.
 581  */
 582 static void scc_mgr_zero_group(const u32 write_group, const int out_only)
 583 {
 584         int i, r;
 585
 586         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 587              r += NUM_RANKS_PER_SHADOW_REG) {
 588                 /* Zero all DQ config settings. */
 589                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 590                         scc_mgr_set_dq_out1_delay(i, 0);
 591                         if (!out_only)
 592                                 scc_mgr_set_dq_in_delay(i, 0);
 593                 }
 594
 595                 /* Multicast to all DQ enables. */
 596                 writel(0xff, &sdr_scc_mgr->dq_ena);
 597
 598                 /* Zero all DM config settings. */
 599                 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 600                         scc_mgr_set_dm_out1_delay(i, 0);
 601
 602                 /* Multicast to all DM enables. */
 603                 writel(0xff, &sdr_scc_mgr->dm_ena);
 604
 605                 /* Zero all DQS IO settings. */
 606                 if (!out_only)
 607                         scc_mgr_set_dqs_io_in_delay(0);
 608
 609                 /* Arria V/Cyclone V don't have out2. */
 610                 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
 611                 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
 612                 scc_mgr_load_dqs_for_write_group(write_group);
 613
 614                 /* Multicast to all DQS IO enables (only 1 in total). */
 615                 writel(0, &sdr_scc_mgr->dqs_io_ena);
 616
 617                 /* Hit update to zero everything. */
 618                 writel(0, &sdr_scc_mgr->update);
 619         }
 620 }
 621
 622 /*
 623  * apply and load a particular input delay for the DQ pins in a group
 624  * group_bgn is the index of the first dq pin (in the write group)
 625  */
 626 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
 627 {
 628         uint32_t i, p;
 629
 630         for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
 631                 scc_mgr_set_dq_in_delay(p, delay);
 632                 scc_mgr_load_dq(p);
 633         }
 634 }
 635
 636 /**
 637  * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
 638  * @delay:              Delay value
 639  *
 640  * Apply and load a particular output delay for the DQ pins in a group.
 641  */
 642 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
 643 {
 644         int i;
 645
 646         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
 647                 scc_mgr_set_dq_out1_delay(i, delay);
 648                 scc_mgr_load_dq(i);
 649         }
 650 }
 651
 652 /* apply and load a particular output delay for the DM pins in a group */
 653 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
 654 {
 655         uint32_t i;
 656
 657         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
 658                 scc_mgr_set_dm_out1_delay(i, delay1);
 659                 scc_mgr_load_dm(i);
 660         }
 661 }
 662
 663
 664 /* apply and load delay on both DQS and OCT out1 */
 665 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
 666                                                     uint32_t delay)
 667 {
 668         scc_mgr_set_dqs_out1_delay(delay);
 669         scc_mgr_load_dqs_io();
 670
 671         scc_mgr_set_oct_out1_delay(write_group, delay);
 672         scc_mgr_load_dqs_for_write_group(write_group);
 673 }
 674
 675 /**
 676  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side: DQ, DM, DQS, OCT
 677  * @write_group:        Write group
 678  * @delay:              Delay value
 679  *
 680  * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
 681  */
 682 static void scc_mgr_apply_group_all_out_delay_add(const u32 write_group,
 683                                                   const u32 delay)
 684 {
 685         u32 i, new_delay;
 686
 687         /* DQ shift */
 688         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++)
 689                 scc_mgr_load_dq(i);
 690
 691         /* DM shift */
 692         for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
 693                 scc_mgr_load_dm(i);
 694
 695         /* DQS shift */
 696         new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
 697         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 698                 debug_cond(DLEVEL == 1,
 699                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 700                            __func__, __LINE__, write_group, delay, new_delay,
 701                            IO_IO_OUT2_DELAY_MAX,
 702                            new_delay - IO_IO_OUT2_DELAY_MAX);
 703                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 704                 scc_mgr_set_dqs_out1_delay(new_delay);
 705         }
 706
 707         scc_mgr_load_dqs_io();
 708
 709         /* OCT shift */
 710         new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
 711         if (new_delay > IO_IO_OUT2_DELAY_MAX) {
 712                 debug_cond(DLEVEL == 1,
 713                            "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
 714                            __func__, __LINE__, write_group, delay,
 715                            new_delay, IO_IO_OUT2_DELAY_MAX,
 716                            new_delay - IO_IO_OUT2_DELAY_MAX);
 717                 new_delay -= IO_IO_OUT2_DELAY_MAX;
 718                 scc_mgr_set_oct_out1_delay(write_group, new_delay);
 719         }
 720
 721         scc_mgr_load_dqs_for_write_group(write_group);
 722 }
 723
 724 /**
 725  * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output side to all ranks
 726  * @write_group:        Write group
 727  * @delay:              Delay value
 728  *
 729  * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
 730  */
 731 static void
 732 scc_mgr_apply_group_all_out_delay_add_all_ranks(const u32 write_group,
 733                                                 const u32 delay)
 734 {
 735         int r;
 736
 737         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
 738              r += NUM_RANKS_PER_SHADOW_REG) {
 739                 scc_mgr_apply_group_all_out_delay_add(write_group, delay);
 740                 writel(0, &sdr_scc_mgr->update);
 741         }
 742 }
 743
 744 /**
 745  * set_jump_as_return() - Return instruction optimization
 746  *
 747  * Optimization used to recover some slots in ddr3 inst_rom could be
 748  * applied to other protocols if we wanted to
 749  */
 750 static void set_jump_as_return(void)
 751 {
 752         /*
 753          * To save space, we replace return with jump to special shared
 754          * RETURN instruction so we set the counter to large value so that
 755          * we always jump.
 756          */
 757         writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
 758         writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 759 }
 760
 761 /*
 762  * should always use constants as argument to ensure all computations are
 763  * performed at compile time
 764  */
 765 static void delay_for_n_mem_clocks(const uint32_t clocks)
 766 {
 767         uint32_t afi_clocks;
 768         uint8_t inner = 0;
 769         uint8_t outer = 0;
 770         uint16_t c_loop = 0;
 771
 772         debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
 773
 774
 775         afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
 776         /* scale (rounding up) to get afi clocks */
 777
 778         /*
 779          * Note, we don't bother accounting for being off a little bit
 780          * because of a few extra instructions in outer loops
 781          * Note, the loops have a test at the end, and do the test before
 782          * the decrement, and so always perform the loop
 783          * 1 time more than the counter value
 784          */
 785         if (afi_clocks == 0) {
 786                 ;
 787         } else if (afi_clocks <= 0x100) {
 788                 inner = afi_clocks-1;
 789                 outer = 0;
 790                 c_loop = 0;
 791         } else if (afi_clocks <= 0x10000) {
 792                 inner = 0xff;
 793                 outer = (afi_clocks-1) >> 8;
 794                 c_loop = 0;
 795         } else {
 796                 inner = 0xff;
 797                 outer = 0xff;
 798                 c_loop = (afi_clocks-1) >> 16;
 799         }
 800
 801         /*
 802          * rom instructions are structured as follows:
 803          *
 804          *    IDLE_LOOP2: jnz cntr0, TARGET_A
 805          *    IDLE_LOOP1: jnz cntr1, TARGET_B
 806          *                return
 807          *
 808          * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
 809          * TARGET_B is set to IDLE_LOOP2 as well
 810          *
 811          * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
 812          * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
 813          *
 814          * a little confusing, but it helps save precious space in the inst_rom
 815          * and sequencer rom and keeps the delays more accurate and reduces
 816          * overhead
 817          */
 818         if (afi_clocks <= 0x100) {
 819                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 820                         &sdr_rw_load_mgr_regs->load_cntr1);
 821
 822                 writel(RW_MGR_IDLE_LOOP1,
 823                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 824
 825                 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 826                                           RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 827         } else {
 828                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
 829                         &sdr_rw_load_mgr_regs->load_cntr0);
 830
 831                 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
 832                         &sdr_rw_load_mgr_regs->load_cntr1);
 833
 834                 writel(RW_MGR_IDLE_LOOP2,
 835                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 836
 837                 writel(RW_MGR_IDLE_LOOP2,
 838                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 839
 840                 /* hack to get around compiler not being smart enough */
 841                 if (afi_clocks <= 0x10000) {
 842                         /* only need to run once */
 843                         writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 844                                                   RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 845                 } else {
 846                         do {
 847                                 writel(RW_MGR_IDLE_LOOP2,
 848                                         SDR_PHYGRP_RWMGRGRP_ADDRESS |
 849                                         RW_MGR_RUN_SINGLE_GROUP_OFFSET);
 850                         } while (c_loop-- != 0);
 851                 }
 852         }
 853         debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
 854 }
 855
 856 /**
 857  * rw_mgr_mem_init_load_regs() - Load instruction registers
 858  * @cntr0:      Counter 0 value
 859  * @cntr1:      Counter 1 value
 860  * @cntr2:      Counter 2 value
 861  * @jump:       Jump instruction value
 862  *
 863  * Load instruction registers.
 864  */
 865 static void rw_mgr_mem_init_load_regs(u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
 866 {
 867         uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 868                            RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 869
 870         /* Load counters */
 871         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
 872                &sdr_rw_load_mgr_regs->load_cntr0);
 873         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
 874                &sdr_rw_load_mgr_regs->load_cntr1);
 875         writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
 876                &sdr_rw_load_mgr_regs->load_cntr2);
 877
 878         /* Load jump address */
 879         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
 880         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
 881         writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
 882
 883         /* Execute count instruction */
 884         writel(jump, grpaddr);
 885 }
 886
 887 /**
 888  * rw_mgr_mem_load_user() - Load user calibration values
 889  * @fin1:       Final instruction 1
 890  * @fin2:       Final instruction 2
 891  * @precharge:  If 1, precharge the banks at the end
 892  *
 893  * Load user calibration values and optionally precharge the banks.
 894  */
 895 static void rw_mgr_mem_load_user(const u32 fin1, const u32 fin2,
 896                                  const int precharge)
 897 {
 898         u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
 899                       RW_MGR_RUN_SINGLE_GROUP_OFFSET;
 900         u32 r;
 901
 902         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
 903                 if (param->skip_ranks[r]) {
 904                         /* request to skip the rank */
 905                         continue;
 906                 }
 907
 908                 /* set rank */
 909                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
 910
 911                 /* precharge all banks ... */
 912                 if (precharge)
 913                         writel(RW_MGR_PRECHARGE_ALL, grpaddr);
 914
 915                 /*
 916                  * USER Use Mirror-ed commands for odd ranks if address
 917                  * mirrorring is on
 918                  */
 919                 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
 920                         set_jump_as_return();
 921                         writel(RW_MGR_MRS2_MIRR, grpaddr);
 922                         delay_for_n_mem_clocks(4);
 923                         set_jump_as_return();
 924                         writel(RW_MGR_MRS3_MIRR, grpaddr);
 925                         delay_for_n_mem_clocks(4);
 926                         set_jump_as_return();
 927                         writel(RW_MGR_MRS1_MIRR, grpaddr);
 928                         delay_for_n_mem_clocks(4);
 929                         set_jump_as_return();
 930                         writel(fin1, grpaddr);
 931                 } else {
 932                         set_jump_as_return();
 933                         writel(RW_MGR_MRS2, grpaddr);
 934                         delay_for_n_mem_clocks(4);
 935                         set_jump_as_return();
 936                         writel(RW_MGR_MRS3, grpaddr);
 937                         delay_for_n_mem_clocks(4);
 938                         set_jump_as_return();
 939                         writel(RW_MGR_MRS1, grpaddr);
 940                         set_jump_as_return();
 941                         writel(fin2, grpaddr);
 942                 }
 943
 944                 if (precharge)
 945                         continue;
 946
 947                 set_jump_as_return();
 948                 writel(RW_MGR_ZQCL, grpaddr);
 949
 950                 /* tZQinit = tDLLK = 512 ck cycles */
 951                 delay_for_n_mem_clocks(512);
 952         }
 953 }
 954
 955 /**
 956  * rw_mgr_mem_initialize() - Initialize RW Manager
 957  *
 958  * Initialize RW Manager.
 959  */
 960 static void rw_mgr_mem_initialize(void)
 961 {
 962         debug("%s:%d\n", __func__, __LINE__);
 963
 964         /* The reset / cke part of initialization is broadcasted to all ranks */
 965         writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
 966                                 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
 967
 968         /*
 969          * Here's how you load register for a loop
 970          * Counters are located @ 0x800
 971          * Jump address are located @ 0xC00
 972          * For both, registers 0 to 3 are selected using bits 3 and 2, like
 973          * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
 974          * I know this ain't pretty, but Avalon bus throws away the 2 least
 975          * significant bits
 976          */
 977
 978         /* Start with memory RESET activated */
 979
 980         /* tINIT = 200us */
 981
 982         /*
 983          * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
 984          * If a and b are the number of iteration in 2 nested loops
 985          * it takes the following number of cycles to complete the operation:
 986          * number_of_cycles = ((2 + n) * a + 2) * b
 987          * where n is the number of instruction in the inner loop
 988          * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
 989          * b = 6A
 990          */
 991         rw_mgr_mem_init_load_regs(SEQ_TINIT_CNTR0_VAL, SEQ_TINIT_CNTR1_VAL,
 992                                   SEQ_TINIT_CNTR2_VAL,
 993                                   RW_MGR_INIT_RESET_0_CKE_0);
 994
 995         /* Indicate that memory is stable. */
 996         writel(1, &phy_mgr_cfg->reset_mem_stbl);
 997
 998         /*
 999          * transition the RESET to high
1000          * Wait for 500us
1001          */
1002
1003         /*
1004          * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1005          * If a and b are the number of iteration in 2 nested loops
1006          * it takes the following number of cycles to complete the operation
1007          * number_of_cycles = ((2 + n) * a + 2) * b
1008          * where n is the number of instruction in the inner loop
1009          * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
1010          * b = FF
1011          */
1012         rw_mgr_mem_init_load_regs(SEQ_TRESET_CNTR0_VAL, SEQ_TRESET_CNTR1_VAL,
1013                                   SEQ_TRESET_CNTR2_VAL,
1014                                   RW_MGR_INIT_RESET_1_CKE_0);
1015
1016         /* Bring up clock enable. */
1017
1018         /* tXRP < 250 ck cycles */
1019         delay_for_n_mem_clocks(250);
1020
1021         rw_mgr_mem_load_user(RW_MGR_MRS0_DLL_RESET_MIRR, RW_MGR_MRS0_DLL_RESET,
1022                              0);
1023 }
1024
1025 /*
1026  * At the end of calibration we have to program the user settings in, and
1027  * USER  hand off the memory to the user.
1028  */
1029 static void rw_mgr_mem_handoff(void)
1030 {
1031         rw_mgr_mem_load_user(RW_MGR_MRS0_USER_MIRR, RW_MGR_MRS0_USER, 1);
1032         /*
1033          * USER  need to wait tMOD (12CK or 15ns) time before issuing
1034          * other commands, but we will have plenty of NIOS cycles before
1035          * actual handoff so its okay.
1036          */
1037 }
1038
1039 /**
1040  * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1041  * @rank_bgn:   Rank number
1042  * @group:      Read/Write Group
1043  * @all_ranks:  Test all ranks
1044  *
1045  * Performs a guaranteed read on the patterns we are going to use during a
1046  * read test to ensure memory works.
1047  */
1048 static int
1049 rw_mgr_mem_calibrate_read_test_patterns(const u32 rank_bgn, const u32 group,
1050                                         const u32 all_ranks)
1051 {
1052         const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1053                          RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1054         const u32 addr_offset =
1055                          (group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS) << 2;
1056         const u32 rank_end = all_ranks ?
1057                                 RW_MGR_MEM_NUMBER_OF_RANKS :
1058                                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1059         const u32 shift_ratio = RW_MGR_MEM_DQ_PER_READ_DQS /
1060                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1061         const u32 correct_mask_vg = param->read_correct_mask_vg;
1062
1063         u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1064         int vg, r;
1065         int ret = 0;
1066
1067         bit_chk = param->read_correct_mask;
1068
1069         for (r = rank_bgn; r < rank_end; r++) {
1070                 /* Request to skip the rank */
1071                 if (param->skip_ranks[r])
1072                         continue;
1073
1074                 /* Set rank */
1075                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1076
1077                 /* Load up a constant bursts of read commands */
1078                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1079                 writel(RW_MGR_GUARANTEED_READ,
1080                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1081
1082                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1083                 writel(RW_MGR_GUARANTEED_READ_CONT,
1084                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1085
1086                 tmp_bit_chk = 0;
1087                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1;
1088                      vg >= 0; vg--) {
1089                         /* Reset the FIFOs to get pointers to known state. */
1090                         writel(0, &phy_mgr_cmd->fifo_reset);
1091                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1092                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1093                         writel(RW_MGR_GUARANTEED_READ,
1094                                addr + addr_offset + (vg << 2));
1095
1096                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1097                         tmp_bit_chk <<= shift_ratio;
1098                         tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1099                 }
1100
1101                 bit_chk &= tmp_bit_chk;
1102         }
1103
1104         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1105
1106         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1107
1108         if (bit_chk != param->read_correct_mask)
1109                 ret = -EIO;
1110
1111         debug_cond(DLEVEL == 1,
1112                    "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1113                    __func__, __LINE__, group, bit_chk,
1114                    param->read_correct_mask, ret);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read test
1121  * @rank_bgn:   Rank number
1122  * @all_ranks:  Test all ranks
1123  *
1124  * Load up the patterns we are going to use during a read test.
1125  */
1126 static void rw_mgr_mem_calibrate_read_load_patterns(const u32 rank_bgn,
1127                                                     const int all_ranks)
1128 {
1129         const u32 rank_end = all_ranks ?
1130                         RW_MGR_MEM_NUMBER_OF_RANKS :
1131                         (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1132         u32 r;
1133
1134         debug("%s:%d\n", __func__, __LINE__);
1135
1136         for (r = rank_bgn; r < rank_end; r++) {
1137                 if (param->skip_ranks[r])
1138                         /* request to skip the rank */
1139                         continue;
1140
1141                 /* set rank */
1142                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1143
1144                 /* Load up a constant bursts */
1145                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1146
1147                 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1148                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1149
1150                 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1151
1152                 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1153                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1154
1155                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1156
1157                 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1158                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1159
1160                 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1161
1162                 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1163                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1164
1165                 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1166                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1167         }
1168
1169         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1170 }
1171
1172 /*
1173  * try a read and see if it returns correct data back. has dummy reads
1174  * inserted into the mix used to align dqs enable. has more thorough checks
1175  * than the regular read test.
1176  */
1177 static int
1178 rw_mgr_mem_calibrate_read_test(const u32 rank_bgn, const u32 group,
1179                                const u32 num_tries, const u32 all_correct,
1180                                u32 *bit_chk,
1181                                const u32 all_groups, const u32 all_ranks)
1182 {
1183         const u32 rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1184                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1185         const u32 quick_read_mode =
1186                 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1187                  ENABLE_SUPER_QUICK_CALIBRATION);
1188         u32 correct_mask_vg = param->read_correct_mask_vg;
1189         u32 tmp_bit_chk;
1190         u32 base_rw_mgr;
1191         u32 addr;
1192
1193         int r, vg, ret;
1194
1195         *bit_chk = param->read_correct_mask;
1196
1197         for (r = rank_bgn; r < rank_end; r++) {
1198                 if (param->skip_ranks[r])
1199                         /* request to skip the rank */
1200                         continue;
1201
1202                 /* set rank */
1203                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1204
1205                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1206
1207                 writel(RW_MGR_READ_B2B_WAIT1,
1208                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1209
1210                 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1211                 writel(RW_MGR_READ_B2B_WAIT2,
1212                         &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1213
1214                 if (quick_read_mode)
1215                         writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1216                         /* need at least two (1+1) reads to capture failures */
1217                 else if (all_groups)
1218                         writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1219                 else
1220                         writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1221
1222                 writel(RW_MGR_READ_B2B,
1223                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1224                 if (all_groups)
1225                         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1226                                RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1227                                &sdr_rw_load_mgr_regs->load_cntr3);
1228                 else
1229                         writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1230
1231                 writel(RW_MGR_READ_B2B,
1232                         &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1233
1234                 tmp_bit_chk = 0;
1235                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1; vg >= 0;
1236                      vg--) {
1237                         /* Reset the FIFOs to get pointers to known state. */
1238                         writel(0, &phy_mgr_cmd->fifo_reset);
1239                         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1240                                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
1241
1242                         if (all_groups) {
1243                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1244                                        RW_MGR_RUN_ALL_GROUPS_OFFSET;
1245                         } else {
1246                                 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1247                                        RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1248                         }
1249
1250                         writel(RW_MGR_READ_B2B, addr +
1251                                ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1252                                vg) << 2));
1253
1254                         base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1255                         tmp_bit_chk <<= RW_MGR_MEM_DQ_PER_READ_DQS /
1256                                         RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS;
1257                         tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1258                 }
1259
1260                 *bit_chk &= tmp_bit_chk;
1261         }
1262
1263         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1264         writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1265
1266         set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1267
1268         if (all_correct) {
1269                 ret = (*bit_chk == param->read_correct_mask);
1270                 debug_cond(DLEVEL == 2,
1271                            "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1272                            __func__, __LINE__, group, all_groups, *bit_chk,
1273                            param->read_correct_mask, ret);
1274         } else  {
1275                 ret = (*bit_chk != 0x00);
1276                 debug_cond(DLEVEL == 2,
1277                            "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1278                            __func__, __LINE__, group, all_groups, *bit_chk,
1279                            0, ret);
1280         }
1281
1282         return ret;
1283 }
1284
1285 /**
1286  * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1287  * @grp:                Read/Write group
1288  * @num_tries:          Number of retries of the test
1289  * @all_correct:        All bits must be correct in the mask
1290  * @all_groups:         Test all R/W groups
1291  *
1292  * Perform a READ test across all memory ranks.
1293  */
1294 static int
1295 rw_mgr_mem_calibrate_read_test_all_ranks(const u32 grp, const u32 num_tries,
1296                                          const u32 all_correct,
1297                                          const u32 all_groups)
1298 {
1299         u32 bit_chk;
1300         return rw_mgr_mem_calibrate_read_test(0, grp, num_tries, all_correct,
1301                                               &bit_chk, all_groups, 1);
1302 }
1303
1304 /**
1305  * rw_mgr_incr_vfifo() - Increase VFIFO value
1306  * @grp:        Read/Write group
1307  *
1308  * Increase VFIFO value.
1309  */
1310 static void rw_mgr_incr_vfifo(const u32 grp)
1311 {
1312         writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1313 }
1314
1315 /**
1316  * rw_mgr_decr_vfifo() - Decrease VFIFO value
1317  * @grp:        Read/Write group
1318  *
1319  * Decrease VFIFO value.
1320  */
1321 static void rw_mgr_decr_vfifo(const u32 grp)
1322 {
1323         u32 i;
1324
1325         for (i = 0; i < VFIFO_SIZE - 1; i++)
1326                 rw_mgr_incr_vfifo(grp);
1327 }
1328
1329 /**
1330  * find_vfifo_failing_read() - Push VFIFO to get a failing read
1331  * @grp:        Read/Write group
1332  *
1333  * Push VFIFO until a failing read happens.
1334  */
1335 static int find_vfifo_failing_read(const u32 grp)
1336 {
1337         u32 v, ret, fail_cnt = 0;
1338
1339         for (v = 0; v < VFIFO_SIZE; v++) {
1340                 debug_cond(DLEVEL == 2, "%s:%d: vfifo %u\n",
1341                            __func__, __LINE__, v);
1342                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1343                                                 PASS_ONE_BIT, 0);
1344                 if (!ret) {
1345                         fail_cnt++;
1346
1347                         if (fail_cnt == 2)
1348                                 return v;
1349                 }
1350
1351                 /* Fiddle with FIFO. */
1352                 rw_mgr_incr_vfifo(grp);
1353         }
1354
1355         /* No failing read found! Something must have gone wrong. */
1356         debug_cond(DLEVEL == 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1357         return 0;
1358 }
1359
1360 /**
1361  * sdr_find_phase_delay() - Find DQS enable phase or delay
1362  * @working:    If 1, look for working phase/delay, if 0, look for non-working
1363  * @delay:      If 1, look for delay, if 0, look for phase
1364  * @grp:        Read/Write group
1365  * @work:       Working window position
1366  * @work_inc:   Working window increment
1367  * @pd:         DQS Phase/Delay Iterator
1368  *
1369  * Find working or non-working DQS enable phase setting.
1370  */
1371 static int sdr_find_phase_delay(int working, int delay, const u32 grp,
1372                                 u32 *work, const u32 work_inc, u32 *pd)
1373 {
1374         const u32 max = delay ? IO_DQS_EN_DELAY_MAX : IO_DQS_EN_PHASE_MAX;
1375         u32 ret;
1376
1377         for (; *pd <= max; (*pd)++) {
1378                 if (delay)
1379                         scc_mgr_set_dqs_en_delay_all_ranks(grp, *pd);
1380                 else
1381                         scc_mgr_set_dqs_en_phase_all_ranks(grp, *pd);
1382
1383                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1384                                         PASS_ONE_BIT, 0);
1385                 if (!working)
1386                         ret = !ret;
1387
1388                 if (ret)
1389                         return 0;
1390
1391                 if (work)
1392                         *work += work_inc;
1393         }
1394
1395         return -EINVAL;
1396 }
1397 /**
1398  * sdr_find_phase() - Find DQS enable phase
1399  * @working:    If 1, look for working phase, if 0, look for non-working phase
1400  * @grp:        Read/Write group
1401  * @work:       Working window position
1402  * @i:          Iterator
1403  * @p:          DQS Phase Iterator
1404  *
1405  * Find working or non-working DQS enable phase setting.
1406  */
1407 static int sdr_find_phase(int working, const u32 grp, u32 *work,
1408                           u32 *i, u32 *p)
1409 {
1410         const u32 end = VFIFO_SIZE + (working ? 0 : 1);
1411         int ret;
1412
1413         for (; *i < end; (*i)++) {
1414                 if (working)
1415                         *p = 0;
1416
1417                 ret = sdr_find_phase_delay(working, 0, grp, work,
1418                                            IO_DELAY_PER_OPA_TAP, p);
1419                 if (!ret)
1420                         return 0;
1421
1422                 if (*p > IO_DQS_EN_PHASE_MAX) {
1423                         /* Fiddle with FIFO. */
1424                         rw_mgr_incr_vfifo(grp);
1425                         if (!working)
1426                                 *p = 0;
1427                 }
1428         }
1429
1430         return -EINVAL;
1431 }
1432
1433 /**
1434  * sdr_working_phase() - Find working DQS enable phase
1435  * @grp:        Read/Write group
1436  * @work_bgn:   Working window start position
1437  * @d:          dtaps output value
1438  * @p:          DQS Phase Iterator
1439  * @i:          Iterator
1440  *
1441  * Find working DQS enable phase setting.
1442  */
1443 static int sdr_working_phase(const u32 grp, u32 *work_bgn, u32 *d,
1444                              u32 *p, u32 *i)
1445 {
1446         const u32 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP /
1447                                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1448         int ret;
1449
1450         *work_bgn = 0;
1451
1452         for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1453                 *i = 0;
1454                 scc_mgr_set_dqs_en_delay_all_ranks(grp, *d);
1455                 ret = sdr_find_phase(1, grp, work_bgn, i, p);
1456                 if (!ret)
1457                         return 0;
1458                 *work_bgn += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1459         }
1460
1461         /* Cannot find working solution */
1462         debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1463                    __func__, __LINE__);
1464         return -EINVAL;
1465 }
1466
1467 /**
1468  * sdr_backup_phase() - Find DQS enable backup phase
1469  * @grp:        Read/Write group
1470  * @work_bgn:   Working window start position
1471  * @p:          DQS Phase Iterator
1472  *
1473  * Find DQS enable backup phase setting.
1474  */
1475 static void sdr_backup_phase(const u32 grp, u32 *work_bgn, u32 *p)
1476 {
1477         u32 tmp_delay, d;
1478         int ret;
1479
1480         /* Special case code for backing up a phase */
1481         if (*p == 0) {
1482                 *p = IO_DQS_EN_PHASE_MAX;
1483                 rw_mgr_decr_vfifo(grp);
1484         } else {
1485                 (*p)--;
1486         }
1487         tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1488         scc_mgr_set_dqs_en_phase_all_ranks(grp, *p);
1489
1490         for (d = 0; d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn; d++) {
1491                 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1492
1493                 ret = rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1494                                         PASS_ONE_BIT, 0);
1495                 if (ret) {
1496                         *work_bgn = tmp_delay;
1497                         break;
1498                 }
1499
1500                 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1501         }
1502
1503         /* Restore VFIFO to old state before we decremented it (if needed). */
1504         (*p)++;
1505         if (*p > IO_DQS_EN_PHASE_MAX) {
1506                 *p = 0;
1507                 rw_mgr_incr_vfifo(grp);
1508         }
1509
1510         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1511 }
1512
1513 /**
1514  * sdr_nonworking_phase() - Find non-working DQS enable phase
1515  * @grp:        Read/Write group
1516  * @work_end:   Working window end position
1517  * @p:          DQS Phase Iterator
1518  * @i:          Iterator
1519  *
1520  * Find non-working DQS enable phase setting.
1521  */
1522 static int sdr_nonworking_phase(const u32 grp, u32 *work_end, u32 *p, u32 *i)
1523 {
1524         int ret;
1525
1526         (*p)++;
1527         *work_end += IO_DELAY_PER_OPA_TAP;
1528         if (*p > IO_DQS_EN_PHASE_MAX) {
1529                 /* Fiddle with FIFO. */
1530                 *p = 0;
1531                 rw_mgr_incr_vfifo(grp);
1532         }
1533
1534         ret = sdr_find_phase(0, grp, work_end, i, p);
1535         if (ret) {
1536                 /* Cannot see edge of failing read. */
1537                 debug_cond(DLEVEL == 2, "%s:%d: end: failed\n",
1538                            __func__, __LINE__);
1539         }
1540
1541         return ret;
1542 }
1543
1544 /**
1545  * sdr_find_window_center() - Find center of the working DQS window.
1546  * @grp:        Read/Write group
1547  * @work_bgn:   First working settings
1548  * @work_end:   Last working settings
1549  *
1550  * Find center of the working DQS enable window.
1551  */
1552 static int sdr_find_window_center(const u32 grp, const u32 work_bgn,
1553                                   const u32 work_end)
1554 {
1555         u32 work_mid;
1556         int tmp_delay = 0;
1557         int i, p, d;
1558
1559         work_mid = (work_bgn + work_end) / 2;
1560
1561         debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1562                    work_bgn, work_end, work_mid);
1563         /* Get the middle delay to be less than a VFIFO delay */
1564         tmp_delay = (IO_DQS_EN_PHASE_MAX + 1) * IO_DELAY_PER_OPA_TAP;
1565
1566         debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1567         work_mid %= tmp_delay;
1568         debug_cond(DLEVEL == 2, "new work_mid %d\n", work_mid);
1569
1570         tmp_delay = rounddown(work_mid, IO_DELAY_PER_OPA_TAP);
1571         if (tmp_delay > IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP)
1572                 tmp_delay = IO_DQS_EN_PHASE_MAX * IO_DELAY_PER_OPA_TAP;
1573         p = tmp_delay / IO_DELAY_PER_OPA_TAP;
1574
1575         debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1576
1577         d = DIV_ROUND_UP(work_mid - tmp_delay, IO_DELAY_PER_DQS_EN_DCHAIN_TAP);
1578         if (d > IO_DQS_EN_DELAY_MAX)
1579                 d = IO_DQS_EN_DELAY_MAX;
1580         tmp_delay += d * IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1581
1582         debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1583
1584         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1585         scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1586
1587         /*
1588          * push vfifo until we can successfully calibrate. We can do this
1589          * because the largest possible margin in 1 VFIFO cycle.
1590          */
1591         for (i = 0; i < VFIFO_SIZE; i++) {
1592                 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center\n");
1593                 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1594                                                              PASS_ONE_BIT,
1595                                                              0)) {
1596                         debug_cond(DLEVEL == 2,
1597                                    "%s:%d center: found: ptap=%u dtap=%u\n",
1598                                    __func__, __LINE__, p, d);
1599                         return 0;
1600                 }
1601
1602                 /* Fiddle with FIFO. */
1603                 rw_mgr_incr_vfifo(grp);
1604         }
1605
1606         debug_cond(DLEVEL == 2, "%s:%d center: failed.\n",
1607                    __func__, __LINE__);
1608         return -EINVAL;
1609 }
1610
1611 /**
1612  * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to use
1613  * @grp:        Read/Write Group
1614  *
1615  * Find a good DQS enable to use.
1616  */
1617 static int rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(const u32 grp)
1618 {
1619         u32 d, p, i;
1620         u32 dtaps_per_ptap;
1621         u32 work_bgn, work_end;
1622         u32 found_passing_read, found_failing_read, initial_failing_dtap;
1623         int ret;
1624
1625         debug("%s:%d %u\n", __func__, __LINE__, grp);
1626
1627         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1628
1629         scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1630         scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1631
1632         /* Step 0: Determine number of delay taps for each phase tap. */
1633         dtaps_per_ptap = IO_DELAY_PER_OPA_TAP / IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1634
1635         /* Step 1: First push vfifo until we get a failing read. */
1636         find_vfifo_failing_read(grp);
1637
1638         /* Step 2: Find first working phase, increment in ptaps. */
1639         work_bgn = 0;
1640         ret = sdr_working_phase(grp, &work_bgn, &d, &p, &i);
1641         if (ret)
1642                 return ret;
1643
1644         work_end = work_bgn;
1645
1646         /*
1647          * If d is 0 then the working window covers a phase tap and we can
1648          * follow the old procedure. Otherwise, we've found the beginning
1649          * and we need to increment the dtaps until we find the end.
1650          */
1651         if (d == 0) {
1652                 /*
1653                  * Step 3a: If we have room, back off by one and
1654                  *          increment in dtaps.
1655                  */
1656                 sdr_backup_phase(grp, &work_bgn, &p);
1657
1658                 /*
1659                  * Step 4a: go forward from working phase to non working
1660                  * phase, increment in ptaps.
1661                  */
1662                 ret = sdr_nonworking_phase(grp, &work_end, &p, &i);
1663                 if (ret)
1664                         return ret;
1665
1666                 /* Step 5a: Back off one from last, increment in dtaps. */
1667
1668                 /* Special case code for backing up a phase */
1669                 if (p == 0) {
1670                         p = IO_DQS_EN_PHASE_MAX;
1671                         rw_mgr_decr_vfifo(grp);
1672                 } else {
1673                         p = p - 1;
1674                 }
1675
1676                 work_end -= IO_DELAY_PER_OPA_TAP;
1677                 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1678
1679                 d = 0;
1680
1681                 debug_cond(DLEVEL == 2, "%s:%d p: ptap=%u\n",
1682                            __func__, __LINE__, p);
1683         }
1684
1685         /* The dtap increment to find the failing edge is done here. */
1686         sdr_find_phase_delay(0, 1, grp, &work_end,
1687                              IO_DELAY_PER_DQS_EN_DCHAIN_TAP, &d);
1688
1689         /* Go back to working dtap */
1690         if (d != 0)
1691                 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1692
1693         debug_cond(DLEVEL == 2,
1694                    "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
1695                    __func__, __LINE__, p, d - 1, work_end);
1696
1697         if (work_end < work_bgn) {
1698                 /* nil range */
1699                 debug_cond(DLEVEL == 2, "%s:%d end-2: failed\n",
1700                            __func__, __LINE__);
1701                 return -EINVAL;
1702         }
1703
1704         debug_cond(DLEVEL == 2, "%s:%d found range [%u,%u]\n",
1705                    __func__, __LINE__, work_bgn, work_end);
1706
1707         /*
1708          * We need to calculate the number of dtaps that equal a ptap.
1709          * To do that we'll back up a ptap and re-find the edge of the
1710          * window using dtaps
1711          */
1712         debug_cond(DLEVEL == 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
1713                    __func__, __LINE__);
1714
1715         /* Special case code for backing up a phase */
1716         if (p == 0) {
1717                 p = IO_DQS_EN_PHASE_MAX;
1718                 rw_mgr_decr_vfifo(grp);
1719                 debug_cond(DLEVEL == 2, "%s:%d backedup cycle/phase: p=%u\n",
1720                            __func__, __LINE__, p);
1721         } else {
1722                 p = p - 1;
1723                 debug_cond(DLEVEL == 2, "%s:%d backedup phase only: p=%u",
1724                            __func__, __LINE__, p);
1725         }
1726
1727         scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1728
1729         /*
1730          * Increase dtap until we first see a passing read (in case the
1731          * window is smaller than a ptap), and then a failing read to
1732          * mark the edge of the window again.
1733          */
1734
1735         /* Find a passing read. */
1736         debug_cond(DLEVEL == 2, "%s:%d find passing read\n",
1737                    __func__, __LINE__);
1738
1739         initial_failing_dtap = d;
1740
1741         found_passing_read = !sdr_find_phase_delay(1, 1, grp, NULL, 0, &d);
1742         if (found_passing_read) {
1743                 /* Find a failing read. */
1744                 debug_cond(DLEVEL == 2, "%s:%d find failing read\n",
1745                            __func__, __LINE__);
1746                 d++;
1747                 found_failing_read = !sdr_find_phase_delay(0, 1, grp, NULL, 0,
1748                                                            &d);
1749         } else {
1750                 debug_cond(DLEVEL == 1,
1751                            "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
1752                            __func__, __LINE__);
1753         }
1754
1755         /*
1756          * The dynamically calculated dtaps_per_ptap is only valid if we
1757          * found a passing/failing read. If we didn't, it means d hit the max
1758          * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1759          * statically calculated value.
1760          */
1761         if (found_passing_read && found_failing_read)
1762                 dtaps_per_ptap = d - initial_failing_dtap;
1763
1764         writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1765         debug_cond(DLEVEL == 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
1766                    __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
1767
1768         /* Step 6: Find the centre of the window. */
1769         ret = sdr_find_window_center(grp, work_bgn, work_end);
1770
1771         return ret;
1772 }
1773
1774 /* per-bit deskew DQ and center */
1775 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1776         uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1777         uint32_t use_read_test, uint32_t update_fom)
1778 {
1779         uint32_t i, p, d, min_index;
1780         /*
1781          * Store these as signed since there are comparisons with
1782          * signed numbers.
1783          */
1784         uint32_t bit_chk;
1785         uint32_t sticky_bit_chk;
1786         int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1787         int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1788         int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1789         int32_t mid;
1790         int32_t orig_mid_min, mid_min;
1791         int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1792                 final_dqs_en;
1793         int32_t dq_margin, dqs_margin;
1794         uint32_t stop;
1795         uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1796         uint32_t addr;
1797
1798         debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1799
1800         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1801         start_dqs = readl(addr + (read_group << 2));
1802         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1803                 start_dqs_en = readl(addr + ((read_group << 2)
1804                                      - IO_DQS_EN_DELAY_OFFSET));
1805
1806         /* set the left and right edge of each bit to an illegal value */
1807         /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1808         sticky_bit_chk = 0;
1809         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1810                 left_edge[i]  = IO_IO_IN_DELAY_MAX + 1;
1811                 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1812         }
1813
1814         /* Search for the left edge of the window for each bit */
1815         for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1816                 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1817
1818                 writel(0, &sdr_scc_mgr->update);
1819
1820                 /*
1821                  * Stop searching when the read test doesn't pass AND when
1822                  * we've seen a passing read on every bit.
1823                  */
1824                 if (use_read_test) {
1825                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1826                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1827                                 &bit_chk, 0, 0);
1828                 } else {
1829                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1830                                                         0, PASS_ONE_BIT,
1831                                                         &bit_chk, 0);
1832                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1833                                 (read_group - (write_group *
1834                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1835                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1836                         stop = (bit_chk == 0);
1837                 }
1838                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1839                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1840                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1841                            && %u", __func__, __LINE__, d,
1842                            sticky_bit_chk,
1843                         param->read_correct_mask, stop);
1844
1845                 if (stop == 1) {
1846                         break;
1847                 } else {
1848                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1849                                 if (bit_chk & 1) {
1850                                         /* Remember a passing test as the
1851                                         left_edge */
1852                                         left_edge[i] = d;
1853                                 } else {
1854                                         /* If a left edge has not been seen yet,
1855                                         then a future passing test will mark
1856                                         this edge as the right edge */
1857                                         if (left_edge[i] ==
1858                                                 IO_IO_IN_DELAY_MAX + 1) {
1859                                                 right_edge[i] = -(d + 1);
1860                                         }
1861                                 }
1862                                 bit_chk = bit_chk >> 1;
1863                         }
1864                 }
1865         }
1866
1867         /* Reset DQ delay chains to 0 */
1868         scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1869         sticky_bit_chk = 0;
1870         for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1871                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1872                            %d right_edge[%u]: %d\n", __func__, __LINE__,
1873                            i, left_edge[i], i, right_edge[i]);
1874
1875                 /*
1876                  * Check for cases where we haven't found the left edge,
1877                  * which makes our assignment of the the right edge invalid.
1878                  * Reset it to the illegal value.
1879                  */
1880                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1881                         right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1882                         right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1883                         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1884                                    right_edge[%u]: %d\n", __func__, __LINE__,
1885                                    i, right_edge[i]);
1886                 }
1887
1888                 /*
1889                  * Reset sticky bit (except for bits where we have seen
1890                  * both the left and right edge).
1891                  */
1892                 sticky_bit_chk = sticky_bit_chk << 1;
1893                 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1894                     (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1895                         sticky_bit_chk = sticky_bit_chk | 1;
1896                 }
1897
1898                 if (i == 0)
1899                         break;
1900         }
1901
1902         /* Search for the right edge of the window for each bit */
1903         for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1904                 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1905                 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1906                         uint32_t delay = d + start_dqs_en;
1907                         if (delay > IO_DQS_EN_DELAY_MAX)
1908                                 delay = IO_DQS_EN_DELAY_MAX;
1909                         scc_mgr_set_dqs_en_delay(read_group, delay);
1910                 }
1911                 scc_mgr_load_dqs(read_group);
1912
1913                 writel(0, &sdr_scc_mgr->update);
1914
1915                 /*
1916                  * Stop searching when the read test doesn't pass AND when
1917                  * we've seen a passing read on every bit.
1918                  */
1919                 if (use_read_test) {
1920                         stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1921                                 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1922                                 &bit_chk, 0, 0);
1923                 } else {
1924                         rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1925                                                         0, PASS_ONE_BIT,
1926                                                         &bit_chk, 0);
1927                         bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1928                                 (read_group - (write_group *
1929                                         RW_MGR_MEM_IF_READ_DQS_WIDTH /
1930                                         RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1931                         stop = (bit_chk == 0);
1932                 }
1933                 sticky_bit_chk = sticky_bit_chk | bit_chk;
1934                 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1935
1936                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
1937                            %u && %u", __func__, __LINE__, d,
1938                            sticky_bit_chk, param->read_correct_mask, stop);
1939
1940                 if (stop == 1) {
1941                         break;
1942                 } else {
1943                         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1944                                 if (bit_chk & 1) {
1945                                         /* Remember a passing test as
1946                                         the right_edge */
1947                                         right_edge[i] = d;
1948                                 } else {
1949                                         if (d != 0) {
1950                                                 /* If a right edge has not been
1951                                                 seen yet, then a future passing
1952                                                 test will mark this edge as the
1953                                                 left edge */
1954                                                 if (right_edge[i] ==
1955                                                 IO_IO_IN_DELAY_MAX + 1) {
1956                                                         left_edge[i] = -(d + 1);
1957                                                 }
1958                                         } else {
1959                                                 /* d = 0 failed, but it passed
1960                                                 when testing the left edge,
1961                                                 so it must be marginal,
1962                                                 set it to -1 */
1963                                                 if (right_edge[i] ==
1964                                                         IO_IO_IN_DELAY_MAX + 1 &&
1965                                                         left_edge[i] !=
1966                                                         IO_IO_IN_DELAY_MAX
1967                                                         + 1) {
1968                                                         right_edge[i] = -1;
1969                                                 }
1970                                                 /* If a right edge has not been
1971                                                 seen yet, then a future passing
1972                                                 test will mark this edge as the
1973                                                 left edge */
1974                                                 else if (right_edge[i] ==
1975                                                         IO_IO_IN_DELAY_MAX +
1976                                                         1) {
1977                                                         left_edge[i] = -(d + 1);
1978                                                 }
1979                                         }
1980                                 }
1981
1982                                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
1983                                            d=%u]: ", __func__, __LINE__, d);
1984                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
1985                                            (int)(bit_chk & 1), i, left_edge[i]);
1986                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
1987                                            right_edge[i]);
1988                                 bit_chk = bit_chk >> 1;
1989                         }
1990                 }
1991         }
1992
1993         /* Check that all bits have a window */
1994         for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1995                 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1996                            %d right_edge[%u]: %d", __func__, __LINE__,
1997                            i, left_edge[i], i, right_edge[i]);
1998                 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
1999                         == IO_IO_IN_DELAY_MAX + 1)) {
2000                         /*
2001                          * Restore delay chain settings before letting the loop
2002                          * in rw_mgr_mem_calibrate_vfifo to retry different
2003                          * dqs/ck relationships.
2004                          */
2005                         scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2006                         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2007                                 scc_mgr_set_dqs_en_delay(read_group,
2008                                                          start_dqs_en);
2009                         }
2010                         scc_mgr_load_dqs(read_group);
2011                         writel(0, &sdr_scc_mgr->update);
2012
2013                         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2014                                    find edge [%u]: %d %d", __func__, __LINE__,
2015                                    i, left_edge[i], right_edge[i]);
2016                         if (use_read_test) {
2017                                 set_failing_group_stage(read_group *
2018                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2019                                         CAL_STAGE_VFIFO,
2020                                         CAL_SUBSTAGE_VFIFO_CENTER);
2021                         } else {
2022                                 set_failing_group_stage(read_group *
2023                                         RW_MGR_MEM_DQ_PER_READ_DQS + i,
2024                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2025                                         CAL_SUBSTAGE_VFIFO_CENTER);
2026                         }
2027                         return 0;
2028                 }
2029         }
2030
2031         /* Find middle of window for each DQ bit */
2032         mid_min = left_edge[0] - right_edge[0];
2033         min_index = 0;
2034         for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2035                 mid = left_edge[i] - right_edge[i];
2036                 if (mid < mid_min) {
2037                         mid_min = mid;
2038                         min_index = i;
2039                 }
2040         }
2041
2042         /*
2043          * -mid_min/2 represents the amount that we need to move DQS.
2044          * If mid_min is odd and positive we'll need to add one to
2045          * make sure the rounding in further calculations is correct
2046          * (always bias to the right), so just add 1 for all positive values.
2047          */
2048         if (mid_min > 0)
2049                 mid_min++;
2050
2051         mid_min = mid_min / 2;
2052
2053         debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2054                    __func__, __LINE__, mid_min, min_index);
2055
2056         /* Determine the amount we can change DQS (which is -mid_min) */
2057         orig_mid_min = mid_min;
2058         new_dqs = start_dqs - mid_min;
2059         if (new_dqs > IO_DQS_IN_DELAY_MAX)
2060                 new_dqs = IO_DQS_IN_DELAY_MAX;
2061         else if (new_dqs < 0)
2062                 new_dqs = 0;
2063
2064         mid_min = start_dqs - new_dqs;
2065         debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2066                    mid_min, new_dqs);
2067
2068         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2069                 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2070                         mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2071                 else if (start_dqs_en - mid_min < 0)
2072                         mid_min += start_dqs_en - mid_min;
2073         }
2074         new_dqs = start_dqs - mid_min;
2075
2076         debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2077                    new_dqs=%d mid_min=%d\n", start_dqs,
2078                    IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2079                    new_dqs, mid_min);
2080
2081         /* Initialize data for export structures */
2082         dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2083         dq_margin  = IO_IO_IN_DELAY_MAX + 1;
2084
2085         /* add delay to bring centre of all DQ windows to the same "level" */
2086         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2087                 /* Use values before divide by 2 to reduce round off error */
2088                 shift_dq = (left_edge[i] - right_edge[i] -
2089                         (left_edge[min_index] - right_edge[min_index]))/2  +
2090                         (orig_mid_min - mid_min);
2091
2092                 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2093                            shift_dq[%u]=%d\n", i, shift_dq);
2094
2095                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2096                 temp_dq_in_delay1 = readl(addr + (p << 2));
2097                 temp_dq_in_delay2 = readl(addr + (i << 2));
2098
2099                 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2100                         (int32_t)IO_IO_IN_DELAY_MAX) {
2101                         shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2102                 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2103                         shift_dq = -(int32_t)temp_dq_in_delay1;
2104                 }
2105                 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2106                            shift_dq[%u]=%d\n", i, shift_dq);
2107                 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2108                 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2109                 scc_mgr_load_dq(p);
2110
2111                 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2112                            left_edge[i] - shift_dq + (-mid_min),
2113                            right_edge[i] + shift_dq - (-mid_min));
2114                 /* To determine values for export structures */
2115                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2116                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2117
2118                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2119                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2120         }
2121
2122         final_dqs = new_dqs;
2123         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2124                 final_dqs_en = start_dqs_en - mid_min;
2125
2126         /* Move DQS-en */
2127         if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2128                 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2129                 scc_mgr_load_dqs(read_group);
2130         }
2131
2132         /* Move DQS */
2133         scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2134         scc_mgr_load_dqs(read_group);
2135         debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2136                    dqs_margin=%d", __func__, __LINE__,
2137                    dq_margin, dqs_margin);
2138
2139         /*
2140          * Do not remove this line as it makes sure all of our decisions
2141          * have been applied. Apply the update bit.
2142          */
2143         writel(0, &sdr_scc_mgr->update);
2144
2145         return (dq_margin >= 0) && (dqs_margin >= 0);
2146 }
2147
2148 /**
2149  * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the device
2150  * @rw_group:   Read/Write Group
2151  * @phase:      DQ/DQS phase
2152  *
2153  * Because initially no communication ca be reliably performed with the memory
2154  * device, the sequencer uses a guaranteed write mechanism to write data into
2155  * the memory device.
2156  */
2157 static int rw_mgr_mem_calibrate_guaranteed_write(const u32 rw_group,
2158                                                  const u32 phase)
2159 {
2160         int ret;
2161
2162         /* Set a particular DQ/DQS phase. */
2163         scc_mgr_set_dqdqs_output_phase_all_ranks(rw_group, phase);
2164
2165         debug_cond(DLEVEL == 1, "%s:%d guaranteed write: g=%u p=%u\n",
2166                    __func__, __LINE__, rw_group, phase);
2167
2168         /*
2169          * Altera EMI_RM 2015.05.04 :: Figure 1-25
2170          * Load up the patterns used by read calibration using the
2171          * current DQDQS phase.
2172          */
2173         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2174
2175         if (gbl->phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2176                 return 0;
2177
2178         /*
2179          * Altera EMI_RM 2015.05.04 :: Figure 1-26
2180          * Back-to-Back reads of the patterns used for calibration.
2181          */
2182         ret = rw_mgr_mem_calibrate_read_test_patterns(0, rw_group, 1);
2183         if (ret)
2184                 debug_cond(DLEVEL == 1,
2185                            "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2186                            __func__, __LINE__, rw_group, phase);
2187         return ret;
2188 }
2189
2190 /**
2191  * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2192  * @rw_group:   Read/Write Group
2193  * @test_bgn:   Rank at which the test begins
2194  *
2195  * DQS enable calibration ensures reliable capture of the DQ signal without
2196  * glitches on the DQS line.
2197  */
2198 static int rw_mgr_mem_calibrate_dqs_enable_calibration(const u32 rw_group,
2199                                                        const u32 test_bgn)
2200 {
2201         /*
2202          * Altera EMI_RM 2015.05.04 :: Figure 1-27
2203          * DQS and DQS Eanble Signal Relationships.
2204          */
2205
2206         /* We start at zero, so have one less dq to devide among */
2207         const u32 delay_step = IO_IO_IN_DELAY_MAX /
2208                                (RW_MGR_MEM_DQ_PER_READ_DQS - 1);
2209         int ret;
2210         u32 i, p, d, r;
2211
2212         debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2213
2214         /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2215         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2216              r += NUM_RANKS_PER_SHADOW_REG) {
2217                 for (i = 0, p = test_bgn, d = 0;
2218                      i < RW_MGR_MEM_DQ_PER_READ_DQS;
2219                      i++, p++, d += delay_step) {
2220                         debug_cond(DLEVEL == 1,
2221                                    "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2222                                    __func__, __LINE__, rw_group, r, i, p, d);
2223
2224                         scc_mgr_set_dq_in_delay(p, d);
2225                         scc_mgr_load_dq(p);
2226                 }
2227
2228                 writel(0, &sdr_scc_mgr->update);
2229         }
2230
2231         /*
2232          * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2233          * dq_in_delay values
2234          */
2235         ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(rw_group);
2236
2237         debug_cond(DLEVEL == 1,
2238                    "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2239                    __func__, __LINE__, rw_group, !ret);
2240
2241         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
2242              r += NUM_RANKS_PER_SHADOW_REG) {
2243                 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
2244                 writel(0, &sdr_scc_mgr->update);
2245         }
2246
2247         return ret;
2248 }
2249
2250 /**
2251  * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2252  * @rw_group:           Read/Write Group
2253  * @test_bgn:           Rank at which the test begins
2254  * @use_read_test:      Perform a read test
2255  * @update_fom:         Update FOM
2256  *
2257  * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2258  * within a group.
2259  */
2260 static int
2261 rw_mgr_mem_calibrate_dq_dqs_centering(const u32 rw_group, const u32 test_bgn,
2262                                       const int use_read_test,
2263                                       const int update_fom)
2264
2265 {
2266         int ret, grp_calibrated;
2267         u32 rank_bgn, sr;
2268
2269         /*
2270          * Altera EMI_RM 2015.05.04 :: Figure 1-28
2271          * Read per-bit deskew can be done on a per shadow register basis.
2272          */
2273         grp_calibrated = 1;
2274         for (rank_bgn = 0, sr = 0;
2275              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2276              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2277                 /* Check if this set of ranks should be skipped entirely. */
2278                 if (param->skip_shadow_regs[sr])
2279                         continue;
2280
2281                 ret = rw_mgr_mem_calibrate_vfifo_center(rank_bgn, rw_group,
2282                                                         rw_group, test_bgn,
2283                                                         use_read_test,
2284                                                         update_fom);
2285                 if (ret)
2286                         continue;
2287
2288                 grp_calibrated = 0;
2289         }
2290
2291         if (!grp_calibrated)
2292                 return -EIO;
2293
2294         return 0;
2295 }
2296
2297 /**
2298  * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2299  * @rw_group:           Read/Write Group
2300  * @test_bgn:           Rank at which the test begins
2301  *
2302  * Stage 1: Calibrate the read valid prediction FIFO.
2303  *
2304  * This function implements UniPHY calibration Stage 1, as explained in
2305  * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2306  *
2307  * - read valid prediction will consist of finding:
2308  *   - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2309  *   - DQS input phase  and DQS input delay (DQ/DQS Centering)
2310  *  - we also do a per-bit deskew on the DQ lines.
2311  */
2312 static int rw_mgr_mem_calibrate_vfifo(const u32 rw_group, const u32 test_bgn)
2313 {
2314         uint32_t p, d;
2315         uint32_t dtaps_per_ptap;
2316         uint32_t failed_substage;
2317
2318         int ret;
2319
2320         debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2321
2322         /* Update info for sims */
2323         reg_file_set_group(rw_group);
2324         reg_file_set_stage(CAL_STAGE_VFIFO);
2325         reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2326
2327         failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2328
2329         /* USER Determine number of delay taps for each phase tap. */
2330         dtaps_per_ptap = DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP,
2331                                       IO_DELAY_PER_DQS_EN_DCHAIN_TAP) - 1;
2332
2333         for (d = 0; d <= dtaps_per_ptap; d += 2) {
2334                 /*
2335                  * In RLDRAMX we may be messing the delay of pins in
2336                  * the same write rw_group but outside of the current read
2337                  * the rw_group, but that's ok because we haven't calibrated
2338                  * output side yet.
2339                  */
2340                 if (d > 0) {
2341                         scc_mgr_apply_group_all_out_delay_add_all_ranks(
2342                                                                 rw_group, d);
2343                 }
2344
2345                 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX; p++) {
2346                         /* 1) Guaranteed Write */
2347                         ret = rw_mgr_mem_calibrate_guaranteed_write(rw_group, p);
2348                         if (ret)
2349                                 break;
2350
2351                         /* 2) DQS Enable Calibration */
2352                         ret = rw_mgr_mem_calibrate_dqs_enable_calibration(rw_group,
2353                                                                           test_bgn);
2354                         if (ret) {
2355                                 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2356                                 continue;
2357                         }
2358
2359                         /* 3) Centering DQ/DQS */
2360                         /*
2361                          * If doing read after write calibration, do not update
2362                          * FOM now. Do it then.
2363                          */
2364                         ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group,
2365                                                                 test_bgn, 1, 0);
2366                         if (ret) {
2367                                 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2368                                 continue;
2369                         }
2370
2371                         /* All done. */
2372                         goto cal_done_ok;
2373                 }
2374         }
2375
2376         /* Calibration Stage 1 failed. */
2377         set_failing_group_stage(rw_group, CAL_STAGE_VFIFO, failed_substage);
2378         return 0;
2379
2380         /* Calibration Stage 1 completed OK. */
2381 cal_done_ok:
2382         /*
2383          * Reset the delay chains back to zero if they have moved > 1
2384          * (check for > 1 because loop will increase d even when pass in
2385          * first case).
2386          */
2387         if (d > 2)
2388                 scc_mgr_zero_group(rw_group, 1);
2389
2390         return 1;
2391 }
2392
2393 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2394 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2395                                                uint32_t test_bgn)
2396 {
2397         uint32_t rank_bgn, sr;
2398         uint32_t grp_calibrated;
2399         uint32_t write_group;
2400
2401         debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2402
2403         /* update info for sims */
2404
2405         reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2406         reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2407
2408         write_group = read_group;
2409
2410         /* update info for sims */
2411         reg_file_set_group(read_group);
2412
2413         grp_calibrated = 1;
2414         /* Read per-bit deskew can be done on a per shadow register basis */
2415         for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2416                 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2417                 /* Determine if this set of ranks should be skipped entirely */
2418                 if (!param->skip_shadow_regs[sr]) {
2419                 /* This is the last calibration round, update FOM here */
2420                         if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2421                                                                 write_group,
2422                                                                 read_group,
2423                                                                 test_bgn, 0,
2424                                                                 1)) {
2425                                 grp_calibrated = 0;
2426                         }
2427                 }
2428         }
2429
2430
2431         if (grp_calibrated == 0) {
2432                 set_failing_group_stage(write_group,
2433                                         CAL_STAGE_VFIFO_AFTER_WRITES,
2434                                         CAL_SUBSTAGE_VFIFO_CENTER);
2435                 return 0;
2436         }
2437
2438         return 1;
2439 }
2440
2441 /* Calibrate LFIFO to find smallest read latency */
2442 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2443 {
2444         uint32_t found_one;
2445
2446         debug("%s:%d\n", __func__, __LINE__);
2447
2448         /* update info for sims */
2449         reg_file_set_stage(CAL_STAGE_LFIFO);
2450         reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2451
2452         /* Load up the patterns used by read calibration for all ranks */
2453         rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2454         found_one = 0;
2455
2456         do {
2457                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2458                 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2459                            __func__, __LINE__, gbl->curr_read_lat);
2460
2461                 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2462                                                               NUM_READ_TESTS,
2463                                                               PASS_ALL_BITS,
2464                                                               1)) {
2465                         break;
2466                 }
2467
2468                 found_one = 1;
2469                 /* reduce read latency and see if things are working */
2470                 /* correctly */
2471                 gbl->curr_read_lat--;
2472         } while (gbl->curr_read_lat > 0);
2473
2474         /* reset the fifos to get pointers to known state */
2475
2476         writel(0, &phy_mgr_cmd->fifo_reset);
2477
2478         if (found_one) {
2479                 /* add a fudge factor to the read latency that was determined */
2480                 gbl->curr_read_lat += 2;
2481                 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2482                 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2483                            read_lat=%u\n", __func__, __LINE__,
2484                            gbl->curr_read_lat);
2485                 return 1;
2486         } else {
2487                 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2488                                         CAL_SUBSTAGE_READ_LATENCY);
2489
2490                 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2491                            read_lat=%u\n", __func__, __LINE__,
2492                            gbl->curr_read_lat);
2493                 return 0;
2494         }
2495 }
2496
2497 /*
2498  * issue write test command.
2499  * two variants are provided. one that just tests a write pattern and
2500  * another that tests datamask functionality.
2501  */
2502 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2503                                                   uint32_t test_dm)
2504 {
2505         uint32_t mcc_instruction;
2506         uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2507                 ENABLE_SUPER_QUICK_CALIBRATION);
2508         uint32_t rw_wl_nop_cycles;
2509         uint32_t addr;
2510
2511         /*
2512          * Set counter and jump addresses for the right
2513          * number of NOP cycles.
2514          * The number of supported NOP cycles can range from -1 to infinity
2515          * Three different cases are handled:
2516          *
2517          * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2518          *    mechanism will be used to insert the right number of NOPs
2519          *
2520          * 2. For a number of NOP cycles equals to 0, the micro-instruction
2521          *    issuing the write command will jump straight to the
2522          *    micro-instruction that turns on DQS (for DDRx), or outputs write
2523          *    data (for RLD), skipping
2524          *    the NOP micro-instruction all together
2525          *
2526          * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2527          *    turned on in the same micro-instruction that issues the write
2528          *    command. Then we need
2529          *    to directly jump to the micro-instruction that sends out the data
2530          *
2531          * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2532          *       (2 and 3). One jump-counter (0) is used to perform multiple
2533          *       write-read operations.
2534          *       one counter left to issue this command in "multiple-group" mode
2535          */
2536
2537         rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2538
2539         if (rw_wl_nop_cycles == -1) {
2540                 /*
2541                  * CNTR 2 - We want to execute the special write operation that
2542                  * turns on DQS right away and then skip directly to the
2543                  * instruction that sends out the data. We set the counter to a
2544                  * large number so that the jump is always taken.
2545                  */
2546                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2547
2548                 /* CNTR 3 - Not used */
2549                 if (test_dm) {
2550                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2551                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2552                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2553                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2554                                &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2555                 } else {
2556                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2557                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2558                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2559                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2560                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2561                 }
2562         } else if (rw_wl_nop_cycles == 0) {
2563                 /*
2564                  * CNTR 2 - We want to skip the NOP operation and go straight
2565                  * to the DQS enable instruction. We set the counter to a large
2566                  * number so that the jump is always taken.
2567                  */
2568                 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2569
2570                 /* CNTR 3 - Not used */
2571                 if (test_dm) {
2572                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2573                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2574                                &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2575                 } else {
2576                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2577                         writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2578                                 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2579                 }
2580         } else {
2581                 /*
2582                  * CNTR 2 - In this case we want to execute the next instruction
2583                  * and NOT take the jump. So we set the counter to 0. The jump
2584                  * address doesn't count.
2585                  */
2586                 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2587                 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2588
2589                 /*
2590                  * CNTR 3 - Set the nop counter to the number of cycles we
2591                  * need to loop for, minus 1.
2592                  */
2593                 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2594                 if (test_dm) {
2595                         mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2596                         writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2597                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2598                 } else {
2599                         mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2600                         writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2601                                 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2602                 }
2603         }
2604
2605         writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2606                   RW_MGR_RESET_READ_DATAPATH_OFFSET);
2607
2608         if (quick_write_mode)
2609                 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2610         else
2611                 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2612
2613         writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2614
2615         /*
2616          * CNTR 1 - This is used to ensure enough time elapses
2617          * for read data to come back.
2618          */
2619         writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2620
2621         if (test_dm) {
2622                 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2623                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2624         } else {
2625                 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2626                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2627         }
2628
2629         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2630         writel(mcc_instruction, addr + (group << 2));
2631 }
2632
2633 /* Test writes, can check for a single bit pass or multiple bit pass */
2634 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2635         uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2636         uint32_t *bit_chk, uint32_t all_ranks)
2637 {
2638         uint32_t r;
2639         uint32_t correct_mask_vg;
2640         uint32_t tmp_bit_chk;
2641         uint32_t vg;
2642         uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2643                 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2644         uint32_t addr_rw_mgr;
2645         uint32_t base_rw_mgr;
2646
2647         *bit_chk = param->write_correct_mask;
2648         correct_mask_vg = param->write_correct_mask_vg;
2649
2650         for (r = rank_bgn; r < rank_end; r++) {
2651                 if (param->skip_ranks[r]) {
2652                         /* request to skip the rank */
2653                         continue;
2654                 }
2655
2656                 /* set rank */
2657                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2658
2659                 tmp_bit_chk = 0;
2660                 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2661                 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2662                         /* reset the fifos to get pointers to known state */
2663                         writel(0, &phy_mgr_cmd->fifo_reset);
2664
2665                         tmp_bit_chk = tmp_bit_chk <<
2666                                 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2667                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2668                         rw_mgr_mem_calibrate_write_test_issue(write_group *
2669                                 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2670                                 use_dm);
2671
2672                         base_rw_mgr = readl(addr_rw_mgr);
2673                         tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2674                         if (vg == 0)
2675                                 break;
2676                 }
2677                 *bit_chk &= tmp_bit_chk;
2678         }
2679
2680         if (all_correct) {
2681                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2682                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2683                            %u => %lu", write_group, use_dm,
2684                            *bit_chk, param->write_correct_mask,
2685                            (long unsigned int)(*bit_chk ==
2686                            param->write_correct_mask));
2687                 return *bit_chk == param->write_correct_mask;
2688         } else {
2689                 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2690                 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2691                        write_group, use_dm, *bit_chk);
2692                 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2693                         (long unsigned int)(*bit_chk != 0));
2694                 return *bit_chk != 0x00;
2695         }
2696 }
2697
2698 /*
2699  * center all windows. do per-bit-deskew to possibly increase size of
2700  * certain windows.
2701  */
2702 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2703         uint32_t write_group, uint32_t test_bgn)
2704 {
2705         uint32_t i, p, min_index;
2706         int32_t d;
2707         /*
2708          * Store these as signed since there are comparisons with
2709          * signed numbers.
2710          */
2711         uint32_t bit_chk;
2712         uint32_t sticky_bit_chk;
2713         int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2714         int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2715         int32_t mid;
2716         int32_t mid_min, orig_mid_min;
2717         int32_t new_dqs, start_dqs, shift_dq;
2718         int32_t dq_margin, dqs_margin, dm_margin;
2719         uint32_t stop;
2720         uint32_t temp_dq_out1_delay;
2721         uint32_t addr;
2722
2723         debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2724
2725         dm_margin = 0;
2726
2727         addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2728         start_dqs = readl(addr +
2729                           (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2730
2731         /* per-bit deskew */
2732
2733         /*
2734          * set the left and right edge of each bit to an illegal value
2735          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2736          */
2737         sticky_bit_chk = 0;
2738         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2739                 left_edge[i]  = IO_IO_OUT1_DELAY_MAX + 1;
2740                 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2741         }
2742
2743         /* Search for the left edge of the window for each bit */
2744         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2745                 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2746
2747                 writel(0, &sdr_scc_mgr->update);
2748
2749                 /*
2750                  * Stop searching when the read test doesn't pass AND when
2751                  * we've seen a passing read on every bit.
2752                  */
2753                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2754                         0, PASS_ONE_BIT, &bit_chk, 0);
2755                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2756                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2757                 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2758                            == %u && %u [bit_chk= %u ]\n",
2759                         d, sticky_bit_chk, param->write_correct_mask,
2760                         stop, bit_chk);
2761
2762                 if (stop == 1) {
2763                         break;
2764                 } else {
2765                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2766                                 if (bit_chk & 1) {
2767                                         /*
2768                                          * Remember a passing test as the
2769                                          * left_edge.
2770                                          */
2771                                         left_edge[i] = d;
2772                                 } else {
2773                                         /*
2774                                          * If a left edge has not been seen
2775                                          * yet, then a future passing test will
2776                                          * mark this edge as the right edge.
2777                                          */
2778                                         if (left_edge[i] ==
2779                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2780                                                 right_edge[i] = -(d + 1);
2781                                         }
2782                                 }
2783                                 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2784                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2785                                            (int)(bit_chk & 1), i, left_edge[i]);
2786                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2787                                        right_edge[i]);
2788                                 bit_chk = bit_chk >> 1;
2789                         }
2790                 }
2791         }
2792
2793         /* Reset DQ delay chains to 0 */
2794         scc_mgr_apply_group_dq_out1_delay(0);
2795         sticky_bit_chk = 0;
2796         for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2797                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2798                            %d right_edge[%u]: %d\n", __func__, __LINE__,
2799                            i, left_edge[i], i, right_edge[i]);
2800
2801                 /*
2802                  * Check for cases where we haven't found the left edge,
2803                  * which makes our assignment of the the right edge invalid.
2804                  * Reset it to the illegal value.
2805                  */
2806                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2807                     (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2808                         right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2809                         debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2810                                    right_edge[%u]: %d\n", __func__, __LINE__,
2811                                    i, right_edge[i]);
2812                 }
2813
2814                 /*
2815                  * Reset sticky bit (except for bits where we have
2816                  * seen the left edge).
2817                  */
2818                 sticky_bit_chk = sticky_bit_chk << 1;
2819                 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2820                         sticky_bit_chk = sticky_bit_chk | 1;
2821
2822                 if (i == 0)
2823                         break;
2824         }
2825
2826         /* Search for the right edge of the window for each bit */
2827         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2828                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2829                                                         d + start_dqs);
2830
2831                 writel(0, &sdr_scc_mgr->update);
2832
2833                 /*
2834                  * Stop searching when the read test doesn't pass AND when
2835                  * we've seen a passing read on every bit.
2836                  */
2837                 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2838                         0, PASS_ONE_BIT, &bit_chk, 0);
2839
2840                 sticky_bit_chk = sticky_bit_chk | bit_chk;
2841                 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2842
2843                 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2844                            %u && %u\n", d, sticky_bit_chk,
2845                            param->write_correct_mask, stop);
2846
2847                 if (stop == 1) {
2848                         if (d == 0) {
2849                                 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2850                                         i++) {
2851                                         /* d = 0 failed, but it passed when
2852                                         testing the left edge, so it must be
2853                                         marginal, set it to -1 */
2854                                         if (right_edge[i] ==
2855                                                 IO_IO_OUT1_DELAY_MAX + 1 &&
2856                                                 left_edge[i] !=
2857                                                 IO_IO_OUT1_DELAY_MAX + 1) {
2858                                                 right_edge[i] = -1;
2859                                         }
2860                                 }
2861                         }
2862                         break;
2863                 } else {
2864                         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2865                                 if (bit_chk & 1) {
2866                                         /*
2867                                          * Remember a passing test as
2868                                          * the right_edge.
2869                                          */
2870                                         right_edge[i] = d;
2871                                 } else {
2872                                         if (d != 0) {
2873                                                 /*
2874                                                  * If a right edge has not
2875                                                  * been seen yet, then a future
2876                                                  * passing test will mark this
2877                                                  * edge as the left edge.
2878                                                  */
2879                                                 if (right_edge[i] ==
2880                                                     IO_IO_OUT1_DELAY_MAX + 1)
2881                                                         left_edge[i] = -(d + 1);
2882                                         } else {
2883                                                 /*
2884                                                  * d = 0 failed, but it passed
2885                                                  * when testing the left edge,
2886                                                  * so it must be marginal, set
2887                                                  * it to -1.
2888                                                  */
2889                                                 if (right_edge[i] ==
2890                                                     IO_IO_OUT1_DELAY_MAX + 1 &&
2891                                                     left_edge[i] !=
2892                                                     IO_IO_OUT1_DELAY_MAX + 1)
2893                                                         right_edge[i] = -1;
2894                                                 /*
2895                                                  * If a right edge has not been
2896                                                  * seen yet, then a future
2897                                                  * passing test will mark this
2898                                                  * edge as the left edge.
2899                                                  */
2900                                                 else if (right_edge[i] ==
2901                                                         IO_IO_OUT1_DELAY_MAX +
2902                                                         1)
2903                                                         left_edge[i] = -(d + 1);
2904                                         }
2905                                 }
2906                                 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2907                                 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2908                                            (int)(bit_chk & 1), i, left_edge[i]);
2909                                 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2910                                            right_edge[i]);
2911                                 bit_chk = bit_chk >> 1;
2912                         }
2913                 }
2914         }
2915
2916         /* Check that all bits have a window */
2917         for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2918                 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2919                            %d right_edge[%u]: %d", __func__, __LINE__,
2920                            i, left_edge[i], i, right_edge[i]);
2921                 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2922                     (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2923                         set_failing_group_stage(test_bgn + i,
2924                                                 CAL_STAGE_WRITES,
2925                                                 CAL_SUBSTAGE_WRITES_CENTER);
2926                         return 0;
2927                 }
2928         }
2929
2930         /* Find middle of window for each DQ bit */
2931         mid_min = left_edge[0] - right_edge[0];
2932         min_index = 0;
2933         for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2934                 mid = left_edge[i] - right_edge[i];
2935                 if (mid < mid_min) {
2936                         mid_min = mid;
2937                         min_index = i;
2938                 }
2939         }
2940
2941         /*
2942          * -mid_min/2 represents the amount that we need to move DQS.
2943          * If mid_min is odd and positive we'll need to add one to
2944          * make sure the rounding in further calculations is correct
2945          * (always bias to the right), so just add 1 for all positive values.
2946          */
2947         if (mid_min > 0)
2948                 mid_min++;
2949         mid_min = mid_min / 2;
2950         debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2951                    __LINE__, mid_min);
2952
2953         /* Determine the amount we can change DQS (which is -mid_min) */
2954         orig_mid_min = mid_min;
2955         new_dqs = start_dqs;
2956         mid_min = 0;
2957         debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2958                    mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2959         /* Initialize data for export structures */
2960         dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2961         dq_margin  = IO_IO_OUT1_DELAY_MAX + 1;
2962
2963         /* add delay to bring centre of all DQ windows to the same "level" */
2964         for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2965                 /* Use values before divide by 2 to reduce round off error */
2966                 shift_dq = (left_edge[i] - right_edge[i] -
2967                         (left_edge[min_index] - right_edge[min_index]))/2  +
2968                 (orig_mid_min - mid_min);
2969
2970                 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2971                            [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2972
2973                 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2974                 temp_dq_out1_delay = readl(addr + (i << 2));
2975                 if (shift_dq + (int32_t)temp_dq_out1_delay >
2976                         (int32_t)IO_IO_OUT1_DELAY_MAX) {
2977                         shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2978                 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2979                         shift_dq = -(int32_t)temp_dq_out1_delay;
2980                 }
2981                 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2982                            i, shift_dq);
2983                 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2984                 scc_mgr_load_dq(i);
2985
2986                 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2987                            left_edge[i] - shift_dq + (-mid_min),
2988                            right_edge[i] + shift_dq - (-mid_min));
2989                 /* To determine values for export structures */
2990                 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2991                         dq_margin = left_edge[i] - shift_dq + (-mid_min);
2992
2993                 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2994                         dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2995         }
2996
2997         /* Move DQS */
2998         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2999         writel(0, &sdr_scc_mgr->update);
3000
3001         /* Centre DM */
3002         debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3003
3004         /*
3005          * set the left and right edge of each bit to an illegal value,
3006          * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
3007          */
3008         left_edge[0]  = IO_IO_OUT1_DELAY_MAX + 1;
3009         right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
3010         int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3011         int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3012         int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
3013         int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
3014         int32_t win_best = 0;
3015
3016         /* Search for the/part of the window with DM shift */
3017         for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
3018                 scc_mgr_apply_group_dm_out1_delay(d);
3019                 writel(0, &sdr_scc_mgr->update);
3020
3021                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3022                                                     PASS_ALL_BITS, &bit_chk,
3023                                                     0)) {
3024                         /* USE Set current end of the window */
3025                         end_curr = -d;
3026                         /*
3027                          * If a starting edge of our window has not been seen
3028                          * this is our current start of the DM window.
3029                          */
3030                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3031                                 bgn_curr = -d;
3032
3033                         /*
3034                          * If current window is bigger than best seen.
3035                          * Set best seen to be current window.
3036                          */
3037                         if ((end_curr-bgn_curr+1) > win_best) {
3038                                 win_best = end_curr-bgn_curr+1;
3039                                 bgn_best = bgn_curr;
3040                                 end_best = end_curr;
3041                         }
3042                 } else {
3043                         /* We just saw a failing test. Reset temp edge */
3044                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3045                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3046                         }
3047                 }
3048
3049
3050         /* Reset DM delay chains to 0 */
3051         scc_mgr_apply_group_dm_out1_delay(0);
3052
3053         /*
3054          * Check to see if the current window nudges up aganist 0 delay.
3055          * If so we need to continue the search by shifting DQS otherwise DQS
3056          * search begins as a new search. */
3057         if (end_curr != 0) {
3058                 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3059                 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3060         }
3061
3062         /* Search for the/part of the window with DQS shifts */
3063         for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3064                 /*
3065                  * Note: This only shifts DQS, so are we limiting ourselve to
3066                  * width of DQ unnecessarily.
3067                  */
3068                 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3069                                                         d + new_dqs);
3070
3071                 writel(0, &sdr_scc_mgr->update);
3072                 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3073                                                     PASS_ALL_BITS, &bit_chk,
3074                                                     0)) {
3075                         /* USE Set current end of the window */
3076                         end_curr = d;
3077                         /*
3078                          * If a beginning edge of our window has not been seen
3079                          * this is our current begin of the DM window.
3080                          */
3081                         if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3082                                 bgn_curr = d;
3083
3084                         /*
3085                          * If current window is bigger than best seen. Set best
3086                          * seen to be current window.
3087                          */
3088                         if ((end_curr-bgn_curr+1) > win_best) {
3089                                 win_best = end_curr-bgn_curr+1;
3090                                 bgn_best = bgn_curr;
3091                                 end_best = end_curr;
3092                         }
3093                 } else {
3094                         /* We just saw a failing test. Reset temp edge */
3095                         bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3096                         end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3097
3098                         /* Early exit optimization: if ther remaining delay
3099                         chain space is less than already seen largest window
3100                         we can exit */
3101                         if ((win_best-1) >
3102                                 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3103                                         break;
3104                                 }
3105                         }
3106                 }
3107
3108         /* assign left and right edge for cal and reporting; */
3109         left_edge[0] = -1*bgn_best;
3110         right_edge[0] = end_best;
3111
3112         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3113                    __LINE__, left_edge[0], right_edge[0]);
3114
3115         /* Move DQS (back to orig) */
3116         scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3117
3118         /* Move DM */
3119
3120         /* Find middle of window for the DM bit */
3121         mid = (left_edge[0] - right_edge[0]) / 2;
3122
3123         /* only move right, since we are not moving DQS/DQ */
3124         if (mid < 0)
3125                 mid = 0;
3126
3127         /* dm_marign should fail if we never find a window */
3128         if (win_best == 0)
3129                 dm_margin = -1;
3130         else
3131                 dm_margin = left_edge[0] - mid;
3132
3133         scc_mgr_apply_group_dm_out1_delay(mid);
3134         writel(0, &sdr_scc_mgr->update);
3135
3136         debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3137                    dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3138                    right_edge[0], mid, dm_margin);
3139         /* Export values */
3140         gbl->fom_out += dq_margin + dqs_margin;
3141
3142         debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3143                    dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3144                    dq_margin, dqs_margin, dm_margin);
3145
3146         /*
3147          * Do not remove this line as it makes sure all of our
3148          * decisions have been applied.
3149          */
3150         writel(0, &sdr_scc_mgr->update);
3151         return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3152 }
3153
3154 /* calibrate the write operations */
3155 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3156         uint32_t test_bgn)
3157 {
3158         /* update info for sims */
3159         debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3160
3161         reg_file_set_stage(CAL_STAGE_WRITES);
3162         reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3163
3164         reg_file_set_group(g);
3165
3166         if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3167                 set_failing_group_stage(g, CAL_STAGE_WRITES,
3168                                         CAL_SUBSTAGE_WRITES_CENTER);
3169                 return 0;
3170         }
3171
3172         return 1;
3173 }
3174
3175 /**
3176  * mem_precharge_and_activate() - Precharge all banks and activate
3177  *
3178  * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3179  */
3180 static void mem_precharge_and_activate(void)
3181 {
3182         int r;
3183
3184         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3185                 /* Test if the rank should be skipped. */
3186                 if (param->skip_ranks[r])
3187                         continue;
3188
3189                 /* Set rank. */
3190                 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3191
3192                 /* Precharge all banks. */
3193                 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3194                                              RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3195
3196                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3197                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3198                         &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3199
3200                 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3201                 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3202                         &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3203
3204                 /* Activate rows. */
3205                 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3206                                                 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3207         }
3208 }
3209
3210 /**
3211  * mem_init_latency() - Configure memory RLAT and WLAT settings
3212  *
3213  * Configure memory RLAT and WLAT parameters.
3214  */
3215 static void mem_init_latency(void)
3216 {
3217         /*
3218          * For AV/CV, LFIFO is hardened and always runs at full rate
3219          * so max latency in AFI clocks, used here, is correspondingly
3220          * smaller.
3221          */
3222         const u32 max_latency = (1 << MAX_LATENCY_COUNT_WIDTH) - 1;
3223         u32 rlat, wlat;
3224
3225         debug("%s:%d\n", __func__, __LINE__);
3226
3227         /*
3228          * Read in write latency.
3229          * WL for Hard PHY does not include additive latency.
3230          */
3231         wlat = readl(&data_mgr->t_wl_add);
3232         wlat += readl(&data_mgr->mem_t_add);
3233
3234         gbl->rw_wl_nop_cycles = wlat - 1;
3235
3236         /* Read in readl latency. */
3237         rlat = readl(&data_mgr->t_rl_add);
3238
3239         /* Set a pretty high read latency initially. */
3240         gbl->curr_read_lat = rlat + 16;
3241         if (gbl->curr_read_lat > max_latency)
3242                 gbl->curr_read_lat = max_latency;
3243
3244         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3245
3246         /* Advertise write latency. */
3247         writel(wlat, &phy_mgr_cfg->afi_wlat);
3248 }
3249
3250 /**
3251  * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3252  *
3253  * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3254  */
3255 static void mem_skip_calibrate(void)
3256 {
3257         uint32_t vfifo_offset;
3258         uint32_t i, j, r;
3259
3260         debug("%s:%d\n", __func__, __LINE__);
3261         /* Need to update every shadow register set used by the interface */
3262         for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3263              r += NUM_RANKS_PER_SHADOW_REG) {
3264                 /*
3265                  * Set output phase alignment settings appropriate for
3266                  * skip calibration.
3267                  */
3268                 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3269                         scc_mgr_set_dqs_en_phase(i, 0);
3270 #if IO_DLL_CHAIN_LENGTH == 6
3271                         scc_mgr_set_dqdqs_output_phase(i, 6);
3272 #else
3273                         scc_mgr_set_dqdqs_output_phase(i, 7);
3274 #endif
3275                         /*
3276                          * Case:33398
3277                          *
3278                          * Write data arrives to the I/O two cycles before write
3279                          * latency is reached (720 deg).
3280                          *   -> due to bit-slip in a/c bus
3281                          *   -> to allow board skew where dqs is longer than ck
3282                          *      -> how often can this happen!?
3283                          *      -> can claim back some ptaps for high freq
3284                          *       support if we can relax this, but i digress...
3285                          *
3286                          * The write_clk leads mem_ck by 90 deg
3287                          * The minimum ptap of the OPA is 180 deg
3288                          * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3289                          * The write_clk is always delayed by 2 ptaps
3290                          *
3291                          * Hence, to make DQS aligned to CK, we need to delay
3292                          * DQS by:
3293                          *    (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3294                          *
3295                          * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3296                          * gives us the number of ptaps, which simplies to:
3297                          *
3298                          *    (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3299                          */
3300                         scc_mgr_set_dqdqs_output_phase(i,
3301                                         1.25 * IO_DLL_CHAIN_LENGTH - 2);
3302                 }
3303                 writel(0xff, &sdr_scc_mgr->dqs_ena);
3304                 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3305
3306                 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3307                         writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3308                                   SCC_MGR_GROUP_COUNTER_OFFSET);
3309                 }
3310                 writel(0xff, &sdr_scc_mgr->dq_ena);
3311                 writel(0xff, &sdr_scc_mgr->dm_ena);
3312                 writel(0, &sdr_scc_mgr->update);
3313         }
3314
3315         /* Compensate for simulation model behaviour */
3316         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3317                 scc_mgr_set_dqs_bus_in_delay(i, 10);
3318                 scc_mgr_load_dqs(i);
3319         }
3320         writel(0, &sdr_scc_mgr->update);
3321
3322         /*
3323          * ArriaV has hard FIFOs that can only be initialized by incrementing
3324          * in sequencer.
3325          */
3326         vfifo_offset = CALIB_VFIFO_OFFSET;
3327         for (j = 0; j < vfifo_offset; j++)
3328                 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3329         writel(0, &phy_mgr_cmd->fifo_reset);
3330
3331         /*
3332          * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3333          * setting from generation-time constant.
3334          */
3335         gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3336         writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3337 }
3338
3339 /**
3340  * mem_calibrate() - Memory calibration entry point.
3341  *
3342  * Perform memory calibration.
3343  */
3344 static uint32_t mem_calibrate(void)
3345 {
3346         uint32_t i;
3347         uint32_t rank_bgn, sr;
3348         uint32_t write_group, write_test_bgn;
3349         uint32_t read_group, read_test_bgn;
3350         uint32_t run_groups, current_run;
3351         uint32_t failing_groups = 0;
3352         uint32_t group_failed = 0;
3353
3354         const u32 rwdqs_ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
3355                                 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
3356
3357         debug("%s:%d\n", __func__, __LINE__);
3358
3359         /* Initialize the data settings */
3360         gbl->error_substage = CAL_SUBSTAGE_NIL;
3361         gbl->error_stage = CAL_STAGE_NIL;
3362         gbl->error_group = 0xff;
3363         gbl->fom_in = 0;
3364         gbl->fom_out = 0;
3365
3366         /* Initialize WLAT and RLAT. */
3367         mem_init_latency();
3368
3369         /* Initialize bit slips. */
3370         mem_precharge_and_activate();
3371
3372         for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3373                 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3374                           SCC_MGR_GROUP_COUNTER_OFFSET);
3375                 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3376                 if (i == 0)
3377                         scc_mgr_set_hhp_extras();
3378
3379                 scc_set_bypass_mode(i);
3380         }
3381
3382         /* Calibration is skipped. */
3383         if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3384                 /*
3385                  * Set VFIFO and LFIFO to instant-on settings in skip
3386                  * calibration mode.
3387                  */
3388                 mem_skip_calibrate();
3389
3390                 /*
3391                  * Do not remove this line as it makes sure all of our
3392                  * decisions have been applied.
3393                  */
3394                 writel(0, &sdr_scc_mgr->update);
3395                 return 1;
3396         }
3397
3398         /* Calibration is not skipped. */
3399         for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3400                 /*
3401                  * Zero all delay chain/phase settings for all
3402                  * groups and all shadow register sets.
3403                  */
3404                 scc_mgr_zero_all();
3405
3406                 run_groups = ~param->skip_groups;
3407
3408                 for (write_group = 0, write_test_bgn = 0; write_group
3409                         < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3410                         write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3411
3412                         /* Initialize the group failure */
3413                         group_failed = 0;
3414
3415                         current_run = run_groups & ((1 <<
3416                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3417                         run_groups = run_groups >>
3418                                 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3419
3420                         if (current_run == 0)
3421                                 continue;
3422
3423                         writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3424                                             SCC_MGR_GROUP_COUNTER_OFFSET);
3425                         scc_mgr_zero_group(write_group, 0);
3426
3427                         for (read_group = write_group * rwdqs_ratio,
3428                              read_test_bgn = 0;
3429                              read_group < (write_group + 1) * rwdqs_ratio;
3430                              read_group++,
3431                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3432                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3433                                         continue;
3434
3435                                 /* Calibrate the VFIFO */
3436                                 if (rw_mgr_mem_calibrate_vfifo(read_group,
3437                                                                read_test_bgn))
3438                                         continue;
3439
3440                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3441                                         return 0;
3442
3443                                 /* The group failed, we're done. */
3444                                 goto grp_failed;
3445                         }
3446
3447                         /* Calibrate the output side */
3448                         for (rank_bgn = 0, sr = 0;
3449                              rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
3450                              rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3451                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3452                                         continue;
3453
3454                                 /* Not needed in quick mode! */
3455                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS)
3456                                         continue;
3457
3458                                 /*
3459                                  * Determine if this set of ranks
3460                                  * should be skipped entirely.
3461                                  */
3462                                 if (param->skip_shadow_regs[sr])
3463                                         continue;
3464
3465                                 /* Calibrate WRITEs */
3466                                 if (rw_mgr_mem_calibrate_writes(rank_bgn,
3467                                                 write_group, write_test_bgn))
3468                                         continue;
3469
3470                                 group_failed = 1;
3471                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3472                                         return 0;
3473                         }
3474
3475                         /* Some group failed, we're done. */
3476                         if (group_failed)
3477                                 goto grp_failed;
3478
3479                         for (read_group = write_group * rwdqs_ratio,
3480                              read_test_bgn = 0;
3481                              read_group < (write_group + 1) * rwdqs_ratio;
3482                              read_group++,
3483                              read_test_bgn += RW_MGR_MEM_DQ_PER_READ_DQS) {
3484                                 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3485                                         continue;
3486
3487                                 if (rw_mgr_mem_calibrate_vfifo_end(read_group,
3488                                                                 read_test_bgn))
3489                                         continue;
3490
3491                                 if (!(gbl->phy_debug_mode_flags & PHY_DEBUG_SWEEP_ALL_GROUPS))
3492                                         return 0;
3493
3494                                 /* The group failed, we're done. */
3495                                 goto grp_failed;
3496                         }
3497
3498                         /* No group failed, continue as usual. */
3499                         continue;
3500
3501 grp_failed:             /* A group failed, increment the counter. */
3502                         failing_groups++;
3503                 }
3504
3505                 /*
3506                  * USER If there are any failing groups then report
3507                  * the failure.
3508                  */
3509                 if (failing_groups != 0)
3510                         return 0;
3511
3512                 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3513                         continue;
3514
3515                 /*
3516                  * If we're skipping groups as part of debug,
3517                  * don't calibrate LFIFO.
3518                  */
3519                 if (param->skip_groups != 0)
3520                         continue;
3521
3522                 /* Calibrate the LFIFO */
3523                 if (!rw_mgr_mem_calibrate_lfifo())
3524                         return 0;
3525         }
3526
3527         /*
3528          * Do not remove this line as it makes sure all of our decisions
3529          * have been applied.
3530          */
3531         writel(0, &sdr_scc_mgr->update);
3532         return 1;
3533 }
3534
3535 /**
3536  * run_mem_calibrate() - Perform memory calibration
3537  *
3538  * This function triggers the entire memory calibration procedure.
3539  */
3540 static int run_mem_calibrate(void)
3541 {
3542         int pass;
3543
3544         debug("%s:%d\n", __func__, __LINE__);
3545
3546         /* Reset pass/fail status shown on afi_cal_success/fail */
3547         writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3548
3549         /* Stop tracking manager. */
3550         clrbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3551
3552         phy_mgr_initialize();
3553         rw_mgr_mem_initialize();
3554
3555         /* Perform the actual memory calibration. */
3556         pass = mem_calibrate();
3557
3558         mem_precharge_and_activate();
3559         writel(0, &phy_mgr_cmd->fifo_reset);
3560
3561         /* Handoff. */
3562         rw_mgr_mem_handoff();
3563         /*
3564          * In Hard PHY this is a 2-bit control:
3565          * 0: AFI Mux Select
3566          * 1: DDIO Mux Select
3567          */
3568         writel(0x2, &phy_mgr_cfg->mux_sel);
3569
3570         /* Start tracking manager. */
3571         setbits_le32(&sdr_ctrl->ctrl_cfg, 1 << 22);
3572
3573         return pass;
3574 }
3575
3576 /**
3577  * debug_mem_calibrate() - Report result of memory calibration
3578  * @pass:       Value indicating whether calibration passed or failed
3579  *
3580  * This function reports the results of the memory calibration
3581  * and writes debug information into the register file.
3582  */
3583 static void debug_mem_calibrate(int pass)
3584 {
3585         uint32_t debug_info;
3586
3587         if (pass) {
3588                 printf("%s: CALIBRATION PASSED\n", __FILE__);
3589
3590                 gbl->fom_in /= 2;
3591                 gbl->fom_out /= 2;
3592
3593                 if (gbl->fom_in > 0xff)
3594                         gbl->fom_in = 0xff;
3595
3596                 if (gbl->fom_out > 0xff)
3597                         gbl->fom_out = 0xff;
3598
3599                 /* Update the FOM in the register file */
3600                 debug_info = gbl->fom_in;
3601                 debug_info |= gbl->fom_out << 8;
3602                 writel(debug_info, &sdr_reg_file->fom);
3603
3604                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3605                 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3606         } else {
3607                 printf("%s: CALIBRATION FAILED\n", __FILE__);
3608
3609                 debug_info = gbl->error_stage;
3610                 debug_info |= gbl->error_substage << 8;
3611                 debug_info |= gbl->error_group << 16;
3612
3613                 writel(debug_info, &sdr_reg_file->failing_stage);
3614                 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3615                 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3616
3617                 /* Update the failing group/stage in the register file */
3618                 debug_info = gbl->error_stage;
3619                 debug_info |= gbl->error_substage << 8;
3620                 debug_info |= gbl->error_group << 16;
3621                 writel(debug_info, &sdr_reg_file->failing_stage);
3622         }
3623
3624         printf("%s: Calibration complete\n", __FILE__);
3625 }
3626
3627 /**
3628  * hc_initialize_rom_data() - Initialize ROM data
3629  *
3630  * Initialize ROM data.
3631  */
3632 static void hc_initialize_rom_data(void)
3633 {
3634         u32 i, addr;
3635
3636         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3637         for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3638                 writel(inst_rom_init[i], addr + (i << 2));
3639
3640         addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3641         for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3642                 writel(ac_rom_init[i], addr + (i << 2));
3643 }
3644
3645 /**
3646  * initialize_reg_file() - Initialize SDR register file
3647  *
3648  * Initialize SDR register file.
3649  */
3650 static void initialize_reg_file(void)
3651 {
3652         /* Initialize the register file with the correct data */
3653         writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3654         writel(0, &sdr_reg_file->debug_data_addr);
3655         writel(0, &sdr_reg_file->cur_stage);
3656         writel(0, &sdr_reg_file->fom);
3657         writel(0, &sdr_reg_file->failing_stage);
3658         writel(0, &sdr_reg_file->debug1);
3659         writel(0, &sdr_reg_file->debug2);
3660 }
3661
3662 /**
3663  * initialize_hps_phy() - Initialize HPS PHY
3664  *
3665  * Initialize HPS PHY.
3666  */
3667 static void initialize_hps_phy(void)
3668 {
3669         uint32_t reg;
3670         /*
3671          * Tracking also gets configured here because it's in the
3672          * same register.
3673          */
3674         uint32_t trk_sample_count = 7500;
3675         uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3676         /*
3677          * Format is number of outer loops in the 16 MSB, sample
3678          * count in 16 LSB.
3679          */
3680
3681         reg = 0;
3682         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3683         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3684         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3685         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3686         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3687         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3688         /*
3689          * This field selects the intrinsic latency to RDATA_EN/FULL path.
3690          * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3691          */
3692         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3693         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3694                 trk_sample_count);
3695         writel(reg, &sdr_ctrl->phy_ctrl0);
3696
3697         reg = 0;
3698         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3699                 trk_sample_count >>
3700                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3701         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3702                 trk_long_idle_sample_count);
3703         writel(reg, &sdr_ctrl->phy_ctrl1);
3704
3705         reg = 0;
3706         reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3707                 trk_long_idle_sample_count >>
3708                 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3709         writel(reg, &sdr_ctrl->phy_ctrl2);
3710 }
3711
3712 /**
3713  * initialize_tracking() - Initialize tracking
3714  *
3715  * Initialize the register file with usable initial data.
3716  */
3717 static void initialize_tracking(void)
3718 {
3719         /*
3720          * Initialize the register file with the correct data.
3721          * Compute usable version of value in case we skip full
3722          * computation later.
3723          */
3724         writel(DIV_ROUND_UP(IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP) - 1,
3725                &sdr_reg_file->dtaps_per_ptap);
3726
3727         /* trk_sample_count */
3728         writel(7500, &sdr_reg_file->trk_sample_count);
3729
3730         /* longidle outer loop [15:0] */
3731         writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3732
3733         /*
3734          * longidle sample count [31:24]
3735          * trfc, worst case of 933Mhz 4Gb [23:16]
3736          * trcd, worst case [15:8]
3737          * vfifo wait [7:0]
3738          */
3739         writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3740                &sdr_reg_file->delays);
3741
3742         /* mux delay */
3743         writel((RW_MGR_IDLE << 24) | (RW_MGR_ACTIVATE_1 << 16) |
3744                (RW_MGR_SGLE_READ << 8) | (RW_MGR_PRECHARGE_ALL << 0),
3745                &sdr_reg_file->trk_rw_mgr_addr);
3746
3747         writel(RW_MGR_MEM_IF_READ_DQS_WIDTH,
3748                &sdr_reg_file->trk_read_dqs_width);
3749
3750         /* trefi [7:0] */
3751         writel((RW_MGR_REFRESH_ALL << 24) | (1000 << 0),
3752                &sdr_reg_file->trk_rfsh);
3753 }
3754
3755 int sdram_calibration_full(void)
3756 {
3757         struct param_type my_param;
3758         struct gbl_type my_gbl;
3759         uint32_t pass;
3760
3761         memset(&my_param, 0, sizeof(my_param));
3762         memset(&my_gbl, 0, sizeof(my_gbl));
3763
3764         param = &my_param;
3765         gbl = &my_gbl;
3766
3767         /* Set the calibration enabled by default */
3768         gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3769         /*
3770          * Only sweep all groups (regardless of fail state) by default
3771          * Set enabled read test by default.
3772          */
3773 #if DISABLE_GUARANTEED_READ
3774         gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3775 #endif
3776         /* Initialize the register file */
3777         initialize_reg_file();
3778
3779         /* Initialize any PHY CSR */
3780         initialize_hps_phy();
3781
3782         scc_mgr_initialize();
3783
3784         initialize_tracking();
3785
3786         printf("%s: Preparing to start memory calibration\n", __FILE__);
3787
3788         debug("%s:%d\n", __func__, __LINE__);
3789         debug_cond(DLEVEL == 1,
3790                    "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3791                    RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3792                    RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3793                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3794                    RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3795         debug_cond(DLEVEL == 1,
3796                    "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3797                    RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3798                    RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3799                    IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3800         debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3801                    IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3802         debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3803                    IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3804                    IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3805         debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3806                    IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3807                    IO_IO_OUT2_DELAY_MAX);
3808         debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3809                    IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3810
3811         hc_initialize_rom_data();
3812
3813         /* update info for sims */
3814         reg_file_set_stage(CAL_STAGE_NIL);
3815         reg_file_set_group(0);
3816
3817         /*
3818          * Load global needed for those actions that require
3819          * some dynamic calibration support.
3820          */
3821         dyn_calib_steps = STATIC_CALIB_STEPS;
3822         /*
3823          * Load global to allow dynamic selection of delay loop settings
3824          * based on calibration mode.
3825          */
3826         if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3827                 skip_delay_mask = 0xff;
3828         else
3829                 skip_delay_mask = 0x0;
3830
3831         pass = run_mem_calibrate();
3832         debug_mem_calibrate(pass);
3833         return pass;
3834 }