1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
8 #include <asm/arch/sdram.h>
11 #include "sequencer.h"
13 static const struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
14 (struct socfpga_sdr_rw_load_manager *)
15 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
16 static const struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs
17 = (struct socfpga_sdr_rw_load_jump_manager *)
18 (SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
19 static const struct socfpga_sdr_reg_file *sdr_reg_file =
20 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
21 static const struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
22 (struct socfpga_sdr_scc_mgr *)
23 (SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
24 static const struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
25 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
26 static const struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
27 (struct socfpga_phy_mgr_cfg *)
28 (SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
29 static const struct socfpga_data_mgr *data_mgr =
30 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
31 static const struct socfpga_sdr_ctrl *sdr_ctrl =
32 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
37 * In order to reduce ROM size, most of the selectable calibration steps are
38 * decided at compile time based on the user's calibration mode selection,
39 * as captured by the STATIC_CALIB_STEPS selection below.
41 * However, to support simulation-time selection of fast simulation mode, where
42 * we skip everything except the bare minimum, we need a few of the steps to
43 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
44 * check, which is based on the rtl-supplied value, or we dynamically compute
45 * the value to use based on the dynamically-chosen calibration mode
49 #define STATIC_IN_RTL_SIM 0
50 #define STATIC_SKIP_DELAY_LOOPS 0
52 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
53 STATIC_SKIP_DELAY_LOOPS)
55 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
56 ((non_skip_value) & seq->skip_delay_mask)
58 bool dram_is_ddr(const u8 ddr)
60 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
61 const u8 type = (cfg->ctrl_cfg >> SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) &
62 SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK;
64 if (ddr == 2 && type == 1) /* DDR2 */
67 if (ddr == 3 && type == 2) /* DDR3 */
73 static void set_failing_group_stage(struct socfpga_sdrseq *seq,
74 u32 group, u32 stage, u32 substage)
77 * Only set the global stage if there was not been any other
80 if (seq->gbl.error_stage == CAL_STAGE_NIL) {
81 seq->gbl.error_substage = substage;
82 seq->gbl.error_stage = stage;
83 seq->gbl.error_group = group;
87 static void reg_file_set_group(u16 set_group)
89 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
92 static void reg_file_set_stage(u8 set_stage)
94 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
97 static void reg_file_set_sub_stage(u8 set_sub_stage)
99 set_sub_stage &= 0xff;
100 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
104 * phy_mgr_initialize() - Initialize PHY Manager
106 * Initialize PHY Manager.
108 static void phy_mgr_initialize(struct socfpga_sdrseq *seq)
112 debug("%s:%d\n", __func__, __LINE__);
113 /* Calibration has control over path to memory */
115 * In Hard PHY this is a 2-bit control:
119 writel(0x3, &phy_mgr_cfg->mux_sel);
121 /* USER memory clock is not stable we begin initialization */
122 writel(0, &phy_mgr_cfg->reset_mem_stbl);
124 /* USER calibration status all set to zero */
125 writel(0, &phy_mgr_cfg->cal_status);
127 writel(0, &phy_mgr_cfg->cal_debug_info);
129 /* Init params only if we do NOT skip calibration. */
130 if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL)
133 ratio = seq->rwcfg->mem_dq_per_read_dqs /
134 seq->rwcfg->mem_virtual_groups_per_read_dqs;
135 seq->param.read_correct_mask_vg = (1 << ratio) - 1;
136 seq->param.write_correct_mask_vg = (1 << ratio) - 1;
137 seq->param.read_correct_mask = (1 << seq->rwcfg->mem_dq_per_read_dqs)
139 seq->param.write_correct_mask = (1 << seq->rwcfg->mem_dq_per_write_dqs)
144 * set_rank_and_odt_mask() - Set Rank and ODT mask
146 * @odt_mode: ODT mode, OFF or READ_WRITE
148 * Set Rank and ODT mask (On-Die Termination).
150 static void set_rank_and_odt_mask(struct socfpga_sdrseq *seq,
151 const u32 rank, const u32 odt_mode)
157 if (odt_mode == RW_MGR_ODT_MODE_OFF) {
160 } else { /* RW_MGR_ODT_MODE_READ_WRITE */
161 switch (seq->rwcfg->mem_number_of_ranks) {
163 /* Read: ODT = 0 ; Write: ODT = 1 */
167 case 2: /* 2 Ranks */
168 if (seq->rwcfg->mem_number_of_cs_per_dimm == 1) {
170 * - Dual-Slot , Single-Rank (1 CS per DIMM)
172 * - RDIMM, 4 total CS (2 CS per DIMM, 2 DIMM)
174 * Since MEM_NUMBER_OF_RANKS is 2, they
175 * are both single rank with 2 CS each
176 * (special for RDIMM).
178 * Read: Turn on ODT on the opposite rank
179 * Write: Turn on ODT on all ranks
181 odt_mask_0 = 0x3 & ~(1 << rank);
184 odt_mask_1 &= ~(1 << rank);
187 * - Single-Slot , Dual-Rank (2 CS per DIMM)
189 * Read: Turn on ODT off on all ranks
190 * Write: Turn on ODT on active rank
193 odt_mask_1 = 0x3 & (1 << rank);
196 case 4: /* 4 Ranks */
198 * DDR3 Read, DDR2 Read/Write:
199 * ----------+-----------------------+
201 * +-----------------------+
202 * Rank | 3 | 2 | 1 | 0 |
203 * ----------+-----+-----+-----+-----+
204 * 0 | 0 | 1 | 0 | 0 |
205 * 1 | 1 | 0 | 0 | 0 |
206 * 2 | 0 | 0 | 0 | 1 |
207 * 3 | 0 | 0 | 1 | 0 |
208 * ----------+-----+-----+-----+-----+
211 * ----------+-----------------------+
213 * Write To +-----------------------+
214 * Rank | 3 | 2 | 1 | 0 |
215 * ----------+-----+-----+-----+-----+
216 * 0 | 0 | 1 | 0 | 1 |
217 * 1 | 1 | 0 | 1 | 0 |
218 * 2 | 0 | 1 | 0 | 1 |
219 * 3 | 1 | 0 | 1 | 0 |
220 * ----------+-----+-----+-----+-----+
227 else if (dram_is_ddr(3))
234 else if (dram_is_ddr(3))
241 else if (dram_is_ddr(3))
248 else if (dram_is_ddr(3))
256 cs_and_odt_mask = (0xFF & ~(1 << rank)) |
257 ((0xFF & odt_mask_0) << 8) |
258 ((0xFF & odt_mask_1) << 16);
259 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
260 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
264 * scc_mgr_set() - Set SCC Manager register
265 * @off: Base offset in SCC Manager space
266 * @grp: Read/Write group
267 * @val: Value to be set
269 * This function sets the SCC Manager (Scan Chain Control Manager) register.
271 static void scc_mgr_set(u32 off, u32 grp, u32 val)
273 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
277 * scc_mgr_initialize() - Initialize SCC Manager registers
279 * Initialize SCC Manager registers.
281 static void scc_mgr_initialize(void)
284 * Clear register file for HPS. 16 (2^4) is the size of the
285 * full register file in the scc mgr:
286 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
287 * MEM_IF_READ_DQS_WIDTH - 1);
291 for (i = 0; i < 16; i++) {
292 debug_cond(DLEVEL >= 1, "%s:%d: Clearing SCC RFILE index %u\n",
293 __func__, __LINE__, i);
294 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, i, 0);
298 static void scc_mgr_set_dqdqs_output_phase(u32 write_group, u32 phase)
300 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
303 static void scc_mgr_set_dqs_bus_in_delay(u32 read_group, u32 delay)
305 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
308 static void scc_mgr_set_dqs_en_phase(u32 read_group, u32 phase)
310 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
313 static void scc_mgr_set_dqs_en_delay(u32 read_group, u32 delay)
315 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
318 static void scc_mgr_set_dq_in_delay(u32 dq_in_group, u32 delay)
320 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
323 static void scc_mgr_set_dqs_io_in_delay(struct socfpga_sdrseq *seq,
326 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
327 seq->rwcfg->mem_dq_per_write_dqs, delay);
330 static void scc_mgr_set_dm_in_delay(struct socfpga_sdrseq *seq, u32 dm,
333 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET,
334 seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
338 static void scc_mgr_set_dq_out1_delay(u32 dq_in_group, u32 delay)
340 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
343 static void scc_mgr_set_dqs_out1_delay(struct socfpga_sdrseq *seq,
346 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
347 seq->rwcfg->mem_dq_per_write_dqs, delay);
350 static void scc_mgr_set_dm_out1_delay(struct socfpga_sdrseq *seq, u32 dm,
353 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
354 seq->rwcfg->mem_dq_per_write_dqs + 1 + dm,
358 /* load up dqs config settings */
359 static void scc_mgr_load_dqs(u32 dqs)
361 writel(dqs, &sdr_scc_mgr->dqs_ena);
364 /* load up dqs io config settings */
365 static void scc_mgr_load_dqs_io(void)
367 writel(0, &sdr_scc_mgr->dqs_io_ena);
370 /* load up dq config settings */
371 static void scc_mgr_load_dq(u32 dq_in_group)
373 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
376 /* load up dm config settings */
377 static void scc_mgr_load_dm(u32 dm)
379 writel(dm, &sdr_scc_mgr->dm_ena);
383 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
384 * @off: Base offset in SCC Manager space
385 * @grp: Read/Write group
386 * @val: Value to be set
387 * @update: If non-zero, trigger SCC Manager update for all ranks
389 * This function sets the SCC Manager (Scan Chain Control Manager) register
390 * and optionally triggers the SCC update for all ranks.
392 static void scc_mgr_set_all_ranks(struct socfpga_sdrseq *seq,
393 const u32 off, const u32 grp, const u32 val,
398 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
399 r += NUM_RANKS_PER_SHADOW_REG) {
400 scc_mgr_set(off, grp, val);
402 if (update || (r == 0)) {
403 writel(grp, &sdr_scc_mgr->dqs_ena);
404 writel(0, &sdr_scc_mgr->update);
409 static void scc_mgr_set_dqs_en_phase_all_ranks(struct socfpga_sdrseq *seq,
410 u32 read_group, u32 phase)
413 * USER although the h/w doesn't support different phases per
414 * shadow register, for simplicity our scc manager modeling
415 * keeps different phase settings per shadow reg, and it's
416 * important for us to keep them in sync to match h/w.
417 * for efficiency, the scan chain update should occur only
420 scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_PHASE_OFFSET,
421 read_group, phase, 0);
424 static void scc_mgr_set_dqdqs_output_phase_all_ranks(struct socfpga_sdrseq *seq,
425 u32 write_group, u32 phase)
428 * USER although the h/w doesn't support different phases per
429 * shadow register, for simplicity our scc manager modeling
430 * keeps different phase settings per shadow reg, and it's
431 * important for us to keep them in sync to match h/w.
432 * for efficiency, the scan chain update should occur only
435 scc_mgr_set_all_ranks(seq, SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
436 write_group, phase, 0);
439 static void scc_mgr_set_dqs_en_delay_all_ranks(struct socfpga_sdrseq *seq,
440 u32 read_group, u32 delay)
443 * In shadow register mode, the T11 settings are stored in
444 * registers in the core, which are updated by the DQS_ENA
445 * signals. Not issuing the SCC_MGR_UPD command allows us to
446 * save lots of rank switching overhead, by calling
447 * select_shadow_regs_for_update with update_scan_chains
450 scc_mgr_set_all_ranks(seq, SCC_MGR_DQS_EN_DELAY_OFFSET,
451 read_group, delay, 1);
455 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
456 * @write_group: Write group
457 * @delay: Delay value
459 * This function sets the OCT output delay in SCC manager.
461 static void scc_mgr_set_oct_out1_delay(struct socfpga_sdrseq *seq,
462 const u32 write_group, const u32 delay)
464 const int ratio = seq->rwcfg->mem_if_read_dqs_width /
465 seq->rwcfg->mem_if_write_dqs_width;
466 const int base = write_group * ratio;
469 * Load the setting in the SCC manager
470 * Although OCT affects only write data, the OCT delay is controlled
471 * by the DQS logic block which is instantiated once per read group.
472 * For protocols where a write group consists of multiple read groups,
473 * the setting must be set multiple times.
475 for (i = 0; i < ratio; i++)
476 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
480 * scc_mgr_set_hhp_extras() - Set HHP extras.
482 * Load the fixed setting in the SCC manager HHP extras.
484 static void scc_mgr_set_hhp_extras(void)
487 * Load the fixed setting in the SCC manager
488 * bits: 0:0 = 1'b1 - DQS bypass
489 * bits: 1:1 = 1'b1 - DQ bypass
490 * bits: 4:2 = 3'b001 - rfifo_mode
491 * bits: 6:5 = 2'b01 - rfifo clock_select
492 * bits: 7:7 = 1'b0 - separate gating from ungating setting
493 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
495 const u32 value = (0 << 8) | (0 << 7) | (1 << 5) |
496 (1 << 2) | (1 << 1) | (1 << 0);
497 const u32 addr = SDR_PHYGRP_SCCGRP_ADDRESS |
498 SCC_MGR_HHP_GLOBALS_OFFSET |
499 SCC_MGR_HHP_EXTRAS_OFFSET;
501 debug_cond(DLEVEL >= 1, "%s:%d Setting HHP Extras\n",
504 debug_cond(DLEVEL >= 1, "%s:%d Done Setting HHP Extras\n",
509 * scc_mgr_zero_all() - Zero all DQS config
511 * Zero all DQS config.
513 static void scc_mgr_zero_all(struct socfpga_sdrseq *seq)
518 * USER Zero all DQS config settings, across all groups and all
521 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
522 r += NUM_RANKS_PER_SHADOW_REG) {
523 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
525 * The phases actually don't exist on a per-rank basis,
526 * but there's no harm updating them several times, so
527 * let's keep the code simple.
529 scc_mgr_set_dqs_bus_in_delay(i,
530 seq->iocfg->dqs_in_reserve
532 scc_mgr_set_dqs_en_phase(i, 0);
533 scc_mgr_set_dqs_en_delay(i, 0);
536 for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
537 scc_mgr_set_dqdqs_output_phase(i, 0);
538 /* Arria V/Cyclone V don't have out2. */
539 scc_mgr_set_oct_out1_delay(seq, i,
540 seq->iocfg->dqs_out_reserve);
544 /* Multicast to all DQS group enables. */
545 writel(0xff, &sdr_scc_mgr->dqs_ena);
546 writel(0, &sdr_scc_mgr->update);
550 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
551 * @write_group: Write group
553 * Set bypass mode and trigger SCC update.
555 static void scc_set_bypass_mode(const u32 write_group)
557 /* Multicast to all DQ enables. */
558 writel(0xff, &sdr_scc_mgr->dq_ena);
559 writel(0xff, &sdr_scc_mgr->dm_ena);
561 /* Update current DQS IO enable. */
562 writel(0, &sdr_scc_mgr->dqs_io_ena);
564 /* Update the DQS logic. */
565 writel(write_group, &sdr_scc_mgr->dqs_ena);
568 writel(0, &sdr_scc_mgr->update);
572 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
573 * @write_group: Write group
575 * Load DQS settings for Write Group, do not trigger SCC update.
577 static void scc_mgr_load_dqs_for_write_group(struct socfpga_sdrseq *seq,
578 const u32 write_group)
580 const int ratio = seq->rwcfg->mem_if_read_dqs_width /
581 seq->rwcfg->mem_if_write_dqs_width;
582 const int base = write_group * ratio;
585 * Load the setting in the SCC manager
586 * Although OCT affects only write data, the OCT delay is controlled
587 * by the DQS logic block which is instantiated once per read group.
588 * For protocols where a write group consists of multiple read groups,
589 * the setting must be set multiple times.
591 for (i = 0; i < ratio; i++)
592 writel(base + i, &sdr_scc_mgr->dqs_ena);
596 * scc_mgr_zero_group() - Zero all configs for a group
598 * Zero DQ, DM, DQS and OCT configs for a group.
600 static void scc_mgr_zero_group(struct socfpga_sdrseq *seq,
601 const u32 write_group, const int out_only)
605 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
606 r += NUM_RANKS_PER_SHADOW_REG) {
607 /* Zero all DQ config settings. */
608 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
609 scc_mgr_set_dq_out1_delay(i, 0);
611 scc_mgr_set_dq_in_delay(i, 0);
614 /* Multicast to all DQ enables. */
615 writel(0xff, &sdr_scc_mgr->dq_ena);
617 /* Zero all DM config settings. */
618 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
620 scc_mgr_set_dm_in_delay(seq, i, 0);
621 scc_mgr_set_dm_out1_delay(seq, i, 0);
624 /* Multicast to all DM enables. */
625 writel(0xff, &sdr_scc_mgr->dm_ena);
627 /* Zero all DQS IO settings. */
629 scc_mgr_set_dqs_io_in_delay(seq, 0);
631 /* Arria V/Cyclone V don't have out2. */
632 scc_mgr_set_dqs_out1_delay(seq, seq->iocfg->dqs_out_reserve);
633 scc_mgr_set_oct_out1_delay(seq, write_group,
634 seq->iocfg->dqs_out_reserve);
635 scc_mgr_load_dqs_for_write_group(seq, write_group);
637 /* Multicast to all DQS IO enables (only 1 in total). */
638 writel(0, &sdr_scc_mgr->dqs_io_ena);
640 /* Hit update to zero everything. */
641 writel(0, &sdr_scc_mgr->update);
646 * apply and load a particular input delay for the DQ pins in a group
647 * group_bgn is the index of the first dq pin (in the write group)
649 static void scc_mgr_apply_group_dq_in_delay(struct socfpga_sdrseq *seq,
650 u32 group_bgn, u32 delay)
654 for (i = 0, p = group_bgn; i < seq->rwcfg->mem_dq_per_read_dqs;
656 scc_mgr_set_dq_in_delay(p, delay);
662 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the
664 * @delay: Delay value
666 * Apply and load a particular output delay for the DQ pins in a group.
668 static void scc_mgr_apply_group_dq_out1_delay(struct socfpga_sdrseq *seq,
673 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
674 scc_mgr_set_dq_out1_delay(i, delay);
679 /* apply and load a particular output delay for the DM pins in a group */
680 static void scc_mgr_apply_group_dm_out1_delay(struct socfpga_sdrseq *seq,
685 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
686 scc_mgr_set_dm_out1_delay(seq, i, delay1);
692 /* apply and load delay on both DQS and OCT out1 */
693 static void scc_mgr_apply_group_dqs_io_and_oct_out1(struct socfpga_sdrseq *seq,
694 u32 write_group, u32 delay)
696 scc_mgr_set_dqs_out1_delay(seq, delay);
697 scc_mgr_load_dqs_io();
699 scc_mgr_set_oct_out1_delay(seq, write_group, delay);
700 scc_mgr_load_dqs_for_write_group(seq, write_group);
704 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output
705 * side: DQ, DM, DQS, OCT
706 * @write_group: Write group
707 * @delay: Delay value
709 * Apply a delay to the entire output side: DQ, DM, DQS, OCT.
711 static void scc_mgr_apply_group_all_out_delay_add(struct socfpga_sdrseq *seq,
712 const u32 write_group,
718 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++)
722 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
726 new_delay = READ_SCC_DQS_IO_OUT2_DELAY + delay;
727 if (new_delay > seq->iocfg->io_out2_delay_max) {
728 debug_cond(DLEVEL >= 1,
729 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
730 __func__, __LINE__, write_group, delay, new_delay,
731 seq->iocfg->io_out2_delay_max,
732 new_delay - seq->iocfg->io_out2_delay_max);
733 new_delay -= seq->iocfg->io_out2_delay_max;
734 scc_mgr_set_dqs_out1_delay(seq, new_delay);
737 scc_mgr_load_dqs_io();
740 new_delay = READ_SCC_OCT_OUT2_DELAY + delay;
741 if (new_delay > seq->iocfg->io_out2_delay_max) {
742 debug_cond(DLEVEL >= 1,
743 "%s:%d (%u, %u) DQS: %u > %d; adding %u to OUT1\n",
744 __func__, __LINE__, write_group, delay,
745 new_delay, seq->iocfg->io_out2_delay_max,
746 new_delay - seq->iocfg->io_out2_delay_max);
747 new_delay -= seq->iocfg->io_out2_delay_max;
748 scc_mgr_set_oct_out1_delay(seq, write_group, new_delay);
751 scc_mgr_load_dqs_for_write_group(seq, write_group);
755 * scc_mgr_apply_group_all_out_delay_add() - Apply a delay to the entire output
757 * @write_group: Write group
758 * @delay: Delay value
760 * Apply a delay to the entire output side (DQ, DM, DQS, OCT) to all ranks.
763 scc_mgr_apply_group_all_out_delay_add_all_ranks(struct socfpga_sdrseq *seq,
764 const u32 write_group,
769 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
770 r += NUM_RANKS_PER_SHADOW_REG) {
771 scc_mgr_apply_group_all_out_delay_add(seq, write_group, delay);
772 writel(0, &sdr_scc_mgr->update);
777 * set_jump_as_return() - Return instruction optimization
779 * Optimization used to recover some slots in ddr3 inst_rom could be
780 * applied to other protocols if we wanted to
782 static void set_jump_as_return(struct socfpga_sdrseq *seq)
785 * To save space, we replace return with jump to special shared
786 * RETURN instruction so we set the counter to large value so that
789 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
790 writel(seq->rwcfg->rreturn, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
794 * delay_for_n_mem_clocks() - Delay for N memory clocks
795 * @clocks: Length of the delay
797 * Delay for N memory clocks.
799 static void delay_for_n_mem_clocks(struct socfpga_sdrseq *seq,
807 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
809 /* Scale (rounding up) to get afi clocks. */
810 afi_clocks = DIV_ROUND_UP(clocks, seq->misccfg->afi_rate_ratio);
811 if (afi_clocks) /* Temporary underflow protection */
815 * Note, we don't bother accounting for being off a little
816 * bit because of a few extra instructions in outer loops.
817 * Note, the loops have a test at the end, and do the test
818 * before the decrement, and so always perform the loop
819 * 1 time more than the counter value
821 c_loop = afi_clocks >> 16;
822 outer = c_loop ? 0xff : (afi_clocks >> 8);
823 inner = outer ? 0xff : afi_clocks;
826 * rom instructions are structured as follows:
828 * IDLE_LOOP2: jnz cntr0, TARGET_A
829 * IDLE_LOOP1: jnz cntr1, TARGET_B
832 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
833 * TARGET_B is set to IDLE_LOOP2 as well
835 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
836 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
838 * a little confusing, but it helps save precious space in the inst_rom
839 * and sequencer rom and keeps the delays more accurate and reduces
842 if (afi_clocks < 0x100) {
843 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
844 &sdr_rw_load_mgr_regs->load_cntr1);
846 writel(seq->rwcfg->idle_loop1,
847 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
849 writel(seq->rwcfg->idle_loop1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
850 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
852 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
853 &sdr_rw_load_mgr_regs->load_cntr0);
855 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
856 &sdr_rw_load_mgr_regs->load_cntr1);
858 writel(seq->rwcfg->idle_loop2,
859 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
861 writel(seq->rwcfg->idle_loop2,
862 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
865 writel(seq->rwcfg->idle_loop2,
866 SDR_PHYGRP_RWMGRGRP_ADDRESS |
867 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
868 } while (c_loop-- != 0);
870 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
873 static void delay_for_n_ns(struct socfpga_sdrseq *seq, const u32 ns)
875 delay_for_n_mem_clocks(seq, (ns * seq->misccfg->afi_clk_freq *
876 seq->misccfg->afi_rate_ratio) / 1000);
880 * rw_mgr_mem_init_load_regs() - Load instruction registers
881 * @cntr0: Counter 0 value
882 * @cntr1: Counter 1 value
883 * @cntr2: Counter 2 value
884 * @jump: Jump instruction value
886 * Load instruction registers.
888 static void rw_mgr_mem_init_load_regs(struct socfpga_sdrseq *seq,
889 u32 cntr0, u32 cntr1, u32 cntr2, u32 jump)
891 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
892 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
895 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr0),
896 &sdr_rw_load_mgr_regs->load_cntr0);
897 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr1),
898 &sdr_rw_load_mgr_regs->load_cntr1);
899 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(cntr2),
900 &sdr_rw_load_mgr_regs->load_cntr2);
902 /* Load jump address */
903 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
904 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add1);
905 writel(jump, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
907 /* Execute count instruction */
908 writel(jump, grpaddr);
912 * rw_mgr_mem_load_user_ddr2() - Load user calibration values for DDR2
913 * @handoff: Indicate whether this is initialization or handoff phase
915 * Load user calibration values and optionally precharge the banks.
917 static void rw_mgr_mem_load_user_ddr2(struct socfpga_sdrseq *seq,
920 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
921 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
924 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
926 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
928 /* precharge all banks ... */
929 writel(seq->rwcfg->precharge_all, grpaddr);
931 writel(seq->rwcfg->emr2, grpaddr);
932 writel(seq->rwcfg->emr3, grpaddr);
933 writel(seq->rwcfg->emr, grpaddr);
936 writel(seq->rwcfg->mr_user, grpaddr);
940 writel(seq->rwcfg->mr_dll_reset, grpaddr);
942 writel(seq->rwcfg->precharge_all, grpaddr);
944 writel(seq->rwcfg->refresh, grpaddr);
945 delay_for_n_ns(seq, 200);
946 writel(seq->rwcfg->refresh, grpaddr);
947 delay_for_n_ns(seq, 200);
949 writel(seq->rwcfg->mr_calib, grpaddr);
950 writel(/*seq->rwcfg->*/0x0b, grpaddr); // EMR_OCD_ENABLE
951 writel(seq->rwcfg->emr, grpaddr);
952 delay_for_n_mem_clocks(seq, 200);
957 * rw_mgr_mem_load_user_ddr3() - Load user calibration values
958 * @fin1: Final instruction 1
959 * @fin2: Final instruction 2
960 * @precharge: If 1, precharge the banks at the end
962 * Load user calibration values and optionally precharge the banks.
964 static void rw_mgr_mem_load_user_ddr3(struct socfpga_sdrseq *seq,
965 const u32 fin1, const u32 fin2,
968 u32 grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
969 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
972 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
974 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
976 /* precharge all banks ... */
978 writel(seq->rwcfg->precharge_all, grpaddr);
981 * USER Use Mirror-ed commands for odd ranks if address
984 if ((seq->rwcfg->mem_address_mirroring >> r) & 0x1) {
985 set_jump_as_return(seq);
986 writel(seq->rwcfg->mrs2_mirr, grpaddr);
987 delay_for_n_mem_clocks(seq, 4);
988 set_jump_as_return(seq);
989 writel(seq->rwcfg->mrs3_mirr, grpaddr);
990 delay_for_n_mem_clocks(seq, 4);
991 set_jump_as_return(seq);
992 writel(seq->rwcfg->mrs1_mirr, grpaddr);
993 delay_for_n_mem_clocks(seq, 4);
994 set_jump_as_return(seq);
995 writel(fin1, grpaddr);
997 set_jump_as_return(seq);
998 writel(seq->rwcfg->mrs2, grpaddr);
999 delay_for_n_mem_clocks(seq, 4);
1000 set_jump_as_return(seq);
1001 writel(seq->rwcfg->mrs3, grpaddr);
1002 delay_for_n_mem_clocks(seq, 4);
1003 set_jump_as_return(seq);
1004 writel(seq->rwcfg->mrs1, grpaddr);
1005 set_jump_as_return(seq);
1006 writel(fin2, grpaddr);
1012 set_jump_as_return(seq);
1013 writel(seq->rwcfg->zqcl, grpaddr);
1015 /* tZQinit = tDLLK = 512 ck cycles */
1016 delay_for_n_mem_clocks(seq, 512);
1021 * rw_mgr_mem_load_user() - Load user calibration values
1022 * @fin1: Final instruction 1
1023 * @fin2: Final instruction 2
1024 * @precharge: If 1, precharge the banks at the end
1026 * Load user calibration values and optionally precharge the banks.
1028 static void rw_mgr_mem_load_user(struct socfpga_sdrseq *seq,
1029 const u32 fin1, const u32 fin2,
1030 const int precharge)
1033 rw_mgr_mem_load_user_ddr2(seq, precharge);
1034 else if (dram_is_ddr(3))
1035 rw_mgr_mem_load_user_ddr3(seq, fin1, fin2, precharge);
1040 * rw_mgr_mem_initialize() - Initialize RW Manager
1042 * Initialize RW Manager.
1044 static void rw_mgr_mem_initialize(struct socfpga_sdrseq *seq)
1046 debug("%s:%d\n", __func__, __LINE__);
1048 /* The reset / cke part of initialization is broadcasted to all ranks */
1049 if (dram_is_ddr(3)) {
1050 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1051 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
1055 * Here's how you load register for a loop
1056 * Counters are located @ 0x800
1057 * Jump address are located @ 0xC00
1058 * For both, registers 0 to 3 are selected using bits 3 and 2, like
1059 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
1060 * I know this ain't pretty, but Avalon bus throws away the 2 least
1064 /* Start with memory RESET activated */
1069 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
1070 * If a and b are the number of iteration in 2 nested loops
1071 * it takes the following number of cycles to complete the operation:
1072 * number_of_cycles = ((2 + n) * a + 2) * b
1073 * where n is the number of instruction in the inner loop
1074 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
1077 rw_mgr_mem_init_load_regs(seq, seq->misccfg->tinit_cntr0_val,
1078 seq->misccfg->tinit_cntr1_val,
1079 seq->misccfg->tinit_cntr2_val,
1080 seq->rwcfg->init_reset_0_cke_0);
1082 /* Indicate that memory is stable. */
1083 writel(1, &phy_mgr_cfg->reset_mem_stbl);
1085 if (dram_is_ddr(2)) {
1086 writel(seq->rwcfg->nop, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1087 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1089 /* Bring up clock enable. */
1091 /* tXRP < 400 ck cycles */
1092 delay_for_n_ns(seq, 400);
1093 } else if (dram_is_ddr(3)) {
1095 * transition the RESET to high
1100 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
1101 * If a and b are the number of iteration in 2 nested loops
1102 * it takes the following number of cycles to complete the
1103 * operation number_of_cycles = ((2 + n) * a + 2) * b
1104 * where n is the number of instruction in the inner loop
1105 * One possible solution is
1106 * n = 2 , a = 131 , b = 256 => a = 83, b = FF
1108 rw_mgr_mem_init_load_regs(seq, seq->misccfg->treset_cntr0_val,
1109 seq->misccfg->treset_cntr1_val,
1110 seq->misccfg->treset_cntr2_val,
1111 seq->rwcfg->init_reset_1_cke_0);
1112 /* Bring up clock enable. */
1114 /* tXRP < 250 ck cycles */
1115 delay_for_n_mem_clocks(seq, 250);
1118 rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_dll_reset_mirr,
1119 seq->rwcfg->mrs0_dll_reset, 0);
1123 * rw_mgr_mem_handoff() - Hand off the memory to user
1125 * At the end of calibration we have to program the user settings in
1126 * and hand off the memory to the user.
1128 static void rw_mgr_mem_handoff(struct socfpga_sdrseq *seq)
1130 rw_mgr_mem_load_user(seq, seq->rwcfg->mrs0_user_mirr,
1131 seq->rwcfg->mrs0_user, 1);
1133 * Need to wait tMOD (12CK or 15ns) time before issuing other
1134 * commands, but we will have plenty of NIOS cycles before actual
1135 * handoff so its okay.
1140 * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
1141 * @group: Write Group
1144 * Issue write test command. Two variants are provided, one that just tests
1145 * a write pattern and another that tests datamask functionality.
1147 static void rw_mgr_mem_calibrate_write_test_issue(struct socfpga_sdrseq *seq,
1148 u32 group, u32 test_dm)
1150 const u32 quick_write_mode =
1151 (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
1152 seq->misccfg->enable_super_quick_calibration;
1153 u32 mcc_instruction;
1154 u32 rw_wl_nop_cycles;
1157 * Set counter and jump addresses for the right
1158 * number of NOP cycles.
1159 * The number of supported NOP cycles can range from -1 to infinity
1160 * Three different cases are handled:
1162 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
1163 * mechanism will be used to insert the right number of NOPs
1165 * 2. For a number of NOP cycles equals to 0, the micro-instruction
1166 * issuing the write command will jump straight to the
1167 * micro-instruction that turns on DQS (for DDRx), or outputs write
1168 * data (for RLD), skipping
1169 * the NOP micro-instruction all together
1171 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
1172 * turned on in the same micro-instruction that issues the write
1173 * command. Then we need
1174 * to directly jump to the micro-instruction that sends out the data
1176 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
1177 * (2 and 3). One jump-counter (0) is used to perform multiple
1178 * write-read operations.
1179 * one counter left to issue this command in "multiple-group" mode
1182 rw_wl_nop_cycles = seq->gbl.rw_wl_nop_cycles;
1184 if (rw_wl_nop_cycles == -1) {
1186 * CNTR 2 - We want to execute the special write operation that
1187 * turns on DQS right away and then skip directly to the
1188 * instruction that sends out the data. We set the counter to a
1189 * large number so that the jump is always taken.
1191 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1193 /* CNTR 3 - Not used */
1195 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0_wl_1;
1196 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_data,
1197 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1198 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1199 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1201 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0_wl_1;
1202 writel(seq->rwcfg->lfsr_wr_rd_bank_0_data,
1203 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1204 writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
1205 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1207 } else if (rw_wl_nop_cycles == 0) {
1209 * CNTR 2 - We want to skip the NOP operation and go straight
1210 * to the DQS enable instruction. We set the counter to a large
1211 * number so that the jump is always taken.
1213 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
1215 /* CNTR 3 - Not used */
1217 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
1218 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_dqs,
1219 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1221 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
1222 writel(seq->rwcfg->lfsr_wr_rd_bank_0_dqs,
1223 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1227 * CNTR 2 - In this case we want to execute the next instruction
1228 * and NOT take the jump. So we set the counter to 0. The jump
1229 * address doesn't count.
1231 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
1232 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1235 * CNTR 3 - Set the nop counter to the number of cycles we
1236 * need to loop for, minus 1.
1238 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
1240 mcc_instruction = seq->rwcfg->lfsr_wr_rd_dm_bank_0;
1241 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_nop,
1242 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1244 mcc_instruction = seq->rwcfg->lfsr_wr_rd_bank_0;
1245 writel(seq->rwcfg->lfsr_wr_rd_bank_0_nop,
1246 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1250 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1251 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1253 if (quick_write_mode)
1254 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
1256 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
1258 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1261 * CNTR 1 - This is used to ensure enough time elapses
1262 * for read data to come back.
1264 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
1267 writel(seq->rwcfg->lfsr_wr_rd_dm_bank_0_wait,
1268 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1270 writel(seq->rwcfg->lfsr_wr_rd_bank_0_wait,
1271 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1274 writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
1275 RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
1280 * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple
1282 * @rank_bgn: Rank number
1283 * @write_group: Write Group
1285 * @all_correct: All bits must be correct in the mask
1286 * @bit_chk: Resulting bit mask after the test
1287 * @all_ranks: Test all ranks
1289 * Test writes, can check for a single bit pass or multiple bit pass.
1292 rw_mgr_mem_calibrate_write_test(struct socfpga_sdrseq *seq,
1293 const u32 rank_bgn, const u32 write_group,
1294 const u32 use_dm, const u32 all_correct,
1295 u32 *bit_chk, const u32 all_ranks)
1297 const u32 rank_end = all_ranks ?
1298 seq->rwcfg->mem_number_of_ranks :
1299 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1300 const u32 shift_ratio = seq->rwcfg->mem_dq_per_write_dqs /
1301 seq->rwcfg->mem_virtual_groups_per_write_dqs;
1302 const u32 correct_mask_vg = seq->param.write_correct_mask_vg;
1304 u32 tmp_bit_chk, base_rw_mgr, group;
1307 *bit_chk = seq->param.write_correct_mask;
1309 for (r = rank_bgn; r < rank_end; r++) {
1311 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1314 for (vg = seq->rwcfg->mem_virtual_groups_per_write_dqs - 1;
1316 /* Reset the FIFOs to get pointers to known state. */
1317 writel(0, &phy_mgr_cmd->fifo_reset);
1319 group = write_group *
1320 seq->rwcfg->mem_virtual_groups_per_write_dqs
1322 rw_mgr_mem_calibrate_write_test_issue(seq, group,
1325 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1326 tmp_bit_chk <<= shift_ratio;
1327 tmp_bit_chk |= (correct_mask_vg & ~(base_rw_mgr));
1330 *bit_chk &= tmp_bit_chk;
1333 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1335 debug_cond(DLEVEL >= 2,
1336 "write_test(%u,%u,ALL) : %u == %u => %i\n",
1337 write_group, use_dm, *bit_chk,
1338 seq->param.write_correct_mask,
1339 *bit_chk == seq->param.write_correct_mask);
1340 return *bit_chk == seq->param.write_correct_mask;
1342 debug_cond(DLEVEL >= 2,
1343 "write_test(%u,%u,ONE) : %u != %i => %i\n",
1344 write_group, use_dm, *bit_chk, 0, *bit_chk != 0);
1345 return *bit_chk != 0x00;
1350 * rw_mgr_mem_calibrate_read_test_patterns() - Read back test patterns
1351 * @rank_bgn: Rank number
1352 * @group: Read/Write Group
1353 * @all_ranks: Test all ranks
1355 * Performs a guaranteed read on the patterns we are going to use during a
1356 * read test to ensure memory works.
1359 rw_mgr_mem_calibrate_read_test_patterns(struct socfpga_sdrseq *seq,
1360 const u32 rank_bgn, const u32 group,
1361 const u32 all_ranks)
1363 const u32 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1364 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1365 const u32 addr_offset =
1366 (group * seq->rwcfg->mem_virtual_groups_per_read_dqs)
1368 const u32 rank_end = all_ranks ?
1369 seq->rwcfg->mem_number_of_ranks :
1370 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1371 const u32 shift_ratio = seq->rwcfg->mem_dq_per_read_dqs /
1372 seq->rwcfg->mem_virtual_groups_per_read_dqs;
1373 const u32 correct_mask_vg = seq->param.read_correct_mask_vg;
1375 u32 tmp_bit_chk, base_rw_mgr, bit_chk;
1379 bit_chk = seq->param.read_correct_mask;
1381 for (r = rank_bgn; r < rank_end; r++) {
1383 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1385 /* Load up a constant bursts of read commands */
1386 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1387 writel(seq->rwcfg->guaranteed_read,
1388 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1390 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1391 writel(seq->rwcfg->guaranteed_read_cont,
1392 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1395 for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
1397 /* Reset the FIFOs to get pointers to known state. */
1398 writel(0, &phy_mgr_cmd->fifo_reset);
1399 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1400 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1401 writel(seq->rwcfg->guaranteed_read,
1402 addr + addr_offset + (vg << 2));
1404 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1405 tmp_bit_chk <<= shift_ratio;
1406 tmp_bit_chk |= correct_mask_vg & ~base_rw_mgr;
1409 bit_chk &= tmp_bit_chk;
1412 writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
1414 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1416 if (bit_chk != seq->param.read_correct_mask)
1419 debug_cond(DLEVEL >= 1,
1420 "%s:%d test_load_patterns(%u,ALL) => (%u == %u) => %i\n",
1421 __func__, __LINE__, group, bit_chk,
1422 seq->param.read_correct_mask, ret);
1428 * rw_mgr_mem_calibrate_read_load_patterns() - Load up the patterns for read
1430 * @rank_bgn: Rank number
1431 * @all_ranks: Test all ranks
1433 * Load up the patterns we are going to use during a read test.
1435 static void rw_mgr_mem_calibrate_read_load_patterns(struct socfpga_sdrseq *seq,
1437 const int all_ranks)
1439 const u32 rank_end = all_ranks ?
1440 seq->rwcfg->mem_number_of_ranks :
1441 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1444 debug("%s:%d\n", __func__, __LINE__);
1446 for (r = rank_bgn; r < rank_end; r++) {
1448 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1450 /* Load up a constant bursts */
1451 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1453 writel(seq->rwcfg->guaranteed_write_wait0,
1454 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1456 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1458 writel(seq->rwcfg->guaranteed_write_wait1,
1459 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1461 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1463 writel(seq->rwcfg->guaranteed_write_wait2,
1464 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1466 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1468 writel(seq->rwcfg->guaranteed_write_wait3,
1469 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1471 writel(seq->rwcfg->guaranteed_write,
1472 SDR_PHYGRP_RWMGRGRP_ADDRESS |
1473 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1476 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1480 * rw_mgr_mem_calibrate_read_test() - Perform READ test on single rank
1481 * @rank_bgn: Rank number
1482 * @group: Read/Write group
1483 * @num_tries: Number of retries of the test
1484 * @all_correct: All bits must be correct in the mask
1485 * @bit_chk: Resulting bit mask after the test
1486 * @all_groups: Test all R/W groups
1487 * @all_ranks: Test all ranks
1489 * Try a read and see if it returns correct data back. Test has dummy reads
1490 * inserted into the mix used to align DQS enable. Test has more thorough
1491 * checks than the regular read test.
1494 rw_mgr_mem_calibrate_read_test(struct socfpga_sdrseq *seq,
1495 const u32 rank_bgn, const u32 group,
1496 const u32 num_tries, const u32 all_correct,
1498 const u32 all_groups, const u32 all_ranks)
1500 const u32 rank_end = all_ranks ? seq->rwcfg->mem_number_of_ranks :
1501 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1502 const u32 quick_read_mode =
1503 ((STATIC_CALIB_STEPS & CALIB_SKIP_DELAY_SWEEPS) &&
1504 seq->misccfg->enable_super_quick_calibration);
1505 u32 correct_mask_vg = seq->param.read_correct_mask_vg;
1512 *bit_chk = seq->param.read_correct_mask;
1514 for (r = rank_bgn; r < rank_end; r++) {
1516 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_READ_WRITE);
1518 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1520 writel(seq->rwcfg->read_b2b_wait1,
1521 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1523 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1524 writel(seq->rwcfg->read_b2b_wait2,
1525 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1527 if (quick_read_mode)
1528 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1529 /* need at least two (1+1) reads to capture failures */
1530 else if (all_groups)
1531 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1533 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1535 writel(seq->rwcfg->read_b2b,
1536 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1538 writel(seq->rwcfg->mem_if_read_dqs_width *
1539 seq->rwcfg->mem_virtual_groups_per_read_dqs - 1,
1540 &sdr_rw_load_mgr_regs->load_cntr3);
1542 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1544 writel(seq->rwcfg->read_b2b,
1545 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1548 for (vg = seq->rwcfg->mem_virtual_groups_per_read_dqs - 1;
1550 /* Reset the FIFOs to get pointers to known state. */
1551 writel(0, &phy_mgr_cmd->fifo_reset);
1552 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1553 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1556 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1557 RW_MGR_RUN_ALL_GROUPS_OFFSET;
1559 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1560 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1563 writel(seq->rwcfg->read_b2b, addr +
1565 seq->rwcfg->mem_virtual_groups_per_read_dqs +
1568 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1570 seq->rwcfg->mem_dq_per_read_dqs /
1571 seq->rwcfg->mem_virtual_groups_per_read_dqs;
1572 tmp_bit_chk |= correct_mask_vg & ~(base_rw_mgr);
1575 *bit_chk &= tmp_bit_chk;
1578 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1579 writel(seq->rwcfg->clear_dqs_enable, addr + (group << 2));
1581 set_rank_and_odt_mask(seq, 0, RW_MGR_ODT_MODE_OFF);
1584 ret = (*bit_chk == seq->param.read_correct_mask);
1585 debug_cond(DLEVEL >= 2,
1586 "%s:%d read_test(%u,ALL,%u) => (%u == %u) => %i\n",
1587 __func__, __LINE__, group, all_groups, *bit_chk,
1588 seq->param.read_correct_mask, ret);
1590 ret = (*bit_chk != 0x00);
1591 debug_cond(DLEVEL >= 2,
1592 "%s:%d read_test(%u,ONE,%u) => (%u != %u) => %i\n",
1593 __func__, __LINE__, group, all_groups, *bit_chk,
1601 * rw_mgr_mem_calibrate_read_test_all_ranks() - Perform READ test on all ranks
1602 * @grp: Read/Write group
1603 * @num_tries: Number of retries of the test
1604 * @all_correct: All bits must be correct in the mask
1605 * @all_groups: Test all R/W groups
1607 * Perform a READ test across all memory ranks.
1610 rw_mgr_mem_calibrate_read_test_all_ranks(struct socfpga_sdrseq *seq,
1611 const u32 grp, const u32 num_tries,
1612 const u32 all_correct,
1613 const u32 all_groups)
1616 return rw_mgr_mem_calibrate_read_test(seq, 0, grp, num_tries,
1617 all_correct, &bit_chk, all_groups,
1622 * rw_mgr_incr_vfifo() - Increase VFIFO value
1623 * @grp: Read/Write group
1625 * Increase VFIFO value.
1627 static void rw_mgr_incr_vfifo(const u32 grp)
1629 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1633 * rw_mgr_decr_vfifo() - Decrease VFIFO value
1634 * @grp: Read/Write group
1636 * Decrease VFIFO value.
1638 static void rw_mgr_decr_vfifo(struct socfpga_sdrseq *seq, const u32 grp)
1642 for (i = 0; i < seq->misccfg->read_valid_fifo_size - 1; i++)
1643 rw_mgr_incr_vfifo(grp);
1647 * find_vfifo_failing_read() - Push VFIFO to get a failing read
1648 * @grp: Read/Write group
1650 * Push VFIFO until a failing read happens.
1652 static int find_vfifo_failing_read(struct socfpga_sdrseq *seq,
1655 u32 v, ret, fail_cnt = 0;
1657 for (v = 0; v < seq->misccfg->read_valid_fifo_size; v++) {
1658 debug_cond(DLEVEL >= 2, "%s:%d: vfifo %u\n",
1659 __func__, __LINE__, v);
1660 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1669 /* Fiddle with FIFO. */
1670 rw_mgr_incr_vfifo(grp);
1673 /* No failing read found! Something must have gone wrong. */
1674 debug_cond(DLEVEL >= 2, "%s:%d: vfifo failed\n", __func__, __LINE__);
1679 * sdr_find_phase_delay() - Find DQS enable phase or delay
1680 * @working: If 1, look for working phase/delay, if 0, look for non-working
1681 * @delay: If 1, look for delay, if 0, look for phase
1682 * @grp: Read/Write group
1683 * @work: Working window position
1684 * @work_inc: Working window increment
1685 * @pd: DQS Phase/Delay Iterator
1687 * Find working or non-working DQS enable phase setting.
1689 static int sdr_find_phase_delay(struct socfpga_sdrseq *seq, int working,
1690 int delay, const u32 grp, u32 *work,
1691 const u32 work_inc, u32 *pd)
1693 const u32 max = delay ? seq->iocfg->dqs_en_delay_max :
1694 seq->iocfg->dqs_en_phase_max;
1697 for (; *pd <= max; (*pd)++) {
1699 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *pd);
1701 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *pd);
1703 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1718 * sdr_find_phase() - Find DQS enable phase
1719 * @working: If 1, look for working phase, if 0, look for non-working phase
1720 * @grp: Read/Write group
1721 * @work: Working window position
1723 * @p: DQS Phase Iterator
1725 * Find working or non-working DQS enable phase setting.
1727 static int sdr_find_phase(struct socfpga_sdrseq *seq, int working,
1728 const u32 grp, u32 *work, u32 *i, u32 *p)
1730 const u32 end = seq->misccfg->read_valid_fifo_size + (working ? 0 : 1);
1733 for (; *i < end; (*i)++) {
1737 ret = sdr_find_phase_delay(seq, working, 0, grp, work,
1738 seq->iocfg->delay_per_opa_tap, p);
1742 if (*p > seq->iocfg->dqs_en_phase_max) {
1743 /* Fiddle with FIFO. */
1744 rw_mgr_incr_vfifo(grp);
1754 * sdr_working_phase() - Find working DQS enable phase
1755 * @grp: Read/Write group
1756 * @work_bgn: Working window start position
1757 * @d: dtaps output value
1758 * @p: DQS Phase Iterator
1761 * Find working DQS enable phase setting.
1763 static int sdr_working_phase(struct socfpga_sdrseq *seq, const u32 grp,
1764 u32 *work_bgn, u32 *d, u32 *p, u32 *i)
1766 const u32 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
1767 seq->iocfg->delay_per_dqs_en_dchain_tap;
1772 for (*d = 0; *d <= dtaps_per_ptap; (*d)++) {
1774 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, *d);
1775 ret = sdr_find_phase(seq, 1, grp, work_bgn, i, p);
1778 *work_bgn += seq->iocfg->delay_per_dqs_en_dchain_tap;
1781 /* Cannot find working solution */
1782 debug_cond(DLEVEL >= 2, "%s:%d find_dqs_en_phase: no vfifo/ptap/dtap\n",
1783 __func__, __LINE__);
1788 * sdr_backup_phase() - Find DQS enable backup phase
1789 * @grp: Read/Write group
1790 * @work_bgn: Working window start position
1791 * @p: DQS Phase Iterator
1793 * Find DQS enable backup phase setting.
1795 static void sdr_backup_phase(struct socfpga_sdrseq *seq, const u32 grp,
1796 u32 *work_bgn, u32 *p)
1801 /* Special case code for backing up a phase */
1803 *p = seq->iocfg->dqs_en_phase_max;
1804 rw_mgr_decr_vfifo(seq, grp);
1808 tmp_delay = *work_bgn - seq->iocfg->delay_per_opa_tap;
1809 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, *p);
1811 for (d = 0; d <= seq->iocfg->dqs_en_delay_max && tmp_delay < *work_bgn;
1813 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
1815 ret = rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1818 *work_bgn = tmp_delay;
1822 tmp_delay += seq->iocfg->delay_per_dqs_en_dchain_tap;
1825 /* Restore VFIFO to old state before we decremented it (if needed). */
1827 if (*p > seq->iocfg->dqs_en_phase_max) {
1829 rw_mgr_incr_vfifo(grp);
1832 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
1836 * sdr_nonworking_phase() - Find non-working DQS enable phase
1837 * @grp: Read/Write group
1838 * @work_end: Working window end position
1839 * @p: DQS Phase Iterator
1842 * Find non-working DQS enable phase setting.
1844 static int sdr_nonworking_phase(struct socfpga_sdrseq *seq,
1845 const u32 grp, u32 *work_end, u32 *p, u32 *i)
1850 *work_end += seq->iocfg->delay_per_opa_tap;
1851 if (*p > seq->iocfg->dqs_en_phase_max) {
1852 /* Fiddle with FIFO. */
1854 rw_mgr_incr_vfifo(grp);
1857 ret = sdr_find_phase(seq, 0, grp, work_end, i, p);
1859 /* Cannot see edge of failing read. */
1860 debug_cond(DLEVEL >= 2, "%s:%d: end: failed\n",
1861 __func__, __LINE__);
1868 * sdr_find_window_center() - Find center of the working DQS window.
1869 * @grp: Read/Write group
1870 * @work_bgn: First working settings
1871 * @work_end: Last working settings
1873 * Find center of the working DQS enable window.
1875 static int sdr_find_window_center(struct socfpga_sdrseq *seq,
1876 const u32 grp, const u32 work_bgn,
1883 work_mid = (work_bgn + work_end) / 2;
1885 debug_cond(DLEVEL >= 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1886 work_bgn, work_end, work_mid);
1887 /* Get the middle delay to be less than a VFIFO delay */
1888 tmp_delay = (seq->iocfg->dqs_en_phase_max + 1)
1889 * seq->iocfg->delay_per_opa_tap;
1891 debug_cond(DLEVEL >= 2, "vfifo ptap delay %d\n", tmp_delay);
1892 work_mid %= tmp_delay;
1893 debug_cond(DLEVEL >= 2, "new work_mid %d\n", work_mid);
1895 tmp_delay = rounddown(work_mid, seq->iocfg->delay_per_opa_tap);
1896 if (tmp_delay > seq->iocfg->dqs_en_phase_max
1897 * seq->iocfg->delay_per_opa_tap) {
1898 tmp_delay = seq->iocfg->dqs_en_phase_max
1899 * seq->iocfg->delay_per_opa_tap;
1901 p = tmp_delay / seq->iocfg->delay_per_opa_tap;
1903 debug_cond(DLEVEL >= 2, "new p %d, tmp_delay=%d\n", p, tmp_delay);
1905 d = DIV_ROUND_UP(work_mid - tmp_delay,
1906 seq->iocfg->delay_per_dqs_en_dchain_tap);
1907 if (d > seq->iocfg->dqs_en_delay_max)
1908 d = seq->iocfg->dqs_en_delay_max;
1909 tmp_delay += d * seq->iocfg->delay_per_dqs_en_dchain_tap;
1911 debug_cond(DLEVEL >= 2, "new d %d, tmp_delay=%d\n", d, tmp_delay);
1913 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
1914 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, d);
1917 * push vfifo until we can successfully calibrate. We can do this
1918 * because the largest possible margin in 1 VFIFO cycle.
1920 for (i = 0; i < seq->misccfg->read_valid_fifo_size; i++) {
1921 debug_cond(DLEVEL >= 2, "find_dqs_en_phase: center\n");
1922 if (rw_mgr_mem_calibrate_read_test_all_ranks(seq, grp, 1,
1925 debug_cond(DLEVEL >= 2,
1926 "%s:%d center: found: ptap=%u dtap=%u\n",
1927 __func__, __LINE__, p, d);
1931 /* Fiddle with FIFO. */
1932 rw_mgr_incr_vfifo(grp);
1935 debug_cond(DLEVEL >= 2, "%s:%d center: failed.\n",
1936 __func__, __LINE__);
1941 * rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase() - Find a good DQS enable to
1943 * @grp: Read/Write Group
1945 * Find a good DQS enable to use.
1948 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(struct socfpga_sdrseq *seq,
1953 u32 work_bgn, work_end;
1954 u32 found_passing_read, found_failing_read = 0, initial_failing_dtap;
1957 debug("%s:%d %u\n", __func__, __LINE__, grp);
1959 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1961 scc_mgr_set_dqs_en_delay_all_ranks(seq, grp, 0);
1962 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, 0);
1964 /* Step 0: Determine number of delay taps for each phase tap. */
1965 dtaps_per_ptap = seq->iocfg->delay_per_opa_tap /
1966 seq->iocfg->delay_per_dqs_en_dchain_tap;
1968 /* Step 1: First push vfifo until we get a failing read. */
1969 find_vfifo_failing_read(seq, grp);
1971 /* Step 2: Find first working phase, increment in ptaps. */
1973 ret = sdr_working_phase(seq, grp, &work_bgn, &d, &p, &i);
1977 work_end = work_bgn;
1980 * If d is 0 then the working window covers a phase tap and we can
1981 * follow the old procedure. Otherwise, we've found the beginning
1982 * and we need to increment the dtaps until we find the end.
1986 * Step 3a: If we have room, back off by one and
1987 * increment in dtaps.
1989 sdr_backup_phase(seq, grp, &work_bgn, &p);
1992 * Step 4a: go forward from working phase to non working
1993 * phase, increment in ptaps.
1995 ret = sdr_nonworking_phase(seq, grp, &work_end, &p, &i);
1999 /* Step 5a: Back off one from last, increment in dtaps. */
2001 /* Special case code for backing up a phase */
2003 p = seq->iocfg->dqs_en_phase_max;
2004 rw_mgr_decr_vfifo(seq, grp);
2009 work_end -= seq->iocfg->delay_per_opa_tap;
2010 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
2014 debug_cond(DLEVEL >= 2, "%s:%d p: ptap=%u\n",
2015 __func__, __LINE__, p);
2018 /* The dtap increment to find the failing edge is done here. */
2019 sdr_find_phase_delay(seq, 0, 1, grp, &work_end,
2020 seq->iocfg->delay_per_dqs_en_dchain_tap, &d);
2022 /* Go back to working dtap */
2024 work_end -= seq->iocfg->delay_per_dqs_en_dchain_tap;
2026 debug_cond(DLEVEL >= 2,
2027 "%s:%d p/d: ptap=%u dtap=%u end=%u\n",
2028 __func__, __LINE__, p, d - 1, work_end);
2030 if (work_end < work_bgn) {
2032 debug_cond(DLEVEL >= 2, "%s:%d end-2: failed\n",
2033 __func__, __LINE__);
2037 debug_cond(DLEVEL >= 2, "%s:%d found range [%u,%u]\n",
2038 __func__, __LINE__, work_bgn, work_end);
2041 * We need to calculate the number of dtaps that equal a ptap.
2042 * To do that we'll back up a ptap and re-find the edge of the
2043 * window using dtaps
2045 debug_cond(DLEVEL >= 2, "%s:%d calculate dtaps_per_ptap for tracking\n",
2046 __func__, __LINE__);
2048 /* Special case code for backing up a phase */
2050 p = seq->iocfg->dqs_en_phase_max;
2051 rw_mgr_decr_vfifo(seq, grp);
2052 debug_cond(DLEVEL >= 2, "%s:%d backedup cycle/phase: p=%u\n",
2053 __func__, __LINE__, p);
2056 debug_cond(DLEVEL >= 2, "%s:%d backedup phase only: p=%u",
2057 __func__, __LINE__, p);
2060 scc_mgr_set_dqs_en_phase_all_ranks(seq, grp, p);
2063 * Increase dtap until we first see a passing read (in case the
2064 * window is smaller than a ptap), and then a failing read to
2065 * mark the edge of the window again.
2068 /* Find a passing read. */
2069 debug_cond(DLEVEL >= 2, "%s:%d find passing read\n",
2070 __func__, __LINE__);
2072 initial_failing_dtap = d;
2074 found_passing_read = !sdr_find_phase_delay(seq, 1, 1, grp, NULL, 0, &d);
2075 if (found_passing_read) {
2076 /* Find a failing read. */
2077 debug_cond(DLEVEL >= 2, "%s:%d find failing read\n",
2078 __func__, __LINE__);
2080 found_failing_read = !sdr_find_phase_delay(seq, 0, 1, grp, NULL,
2083 debug_cond(DLEVEL >= 1,
2084 "%s:%d failed to calculate dtaps per ptap. Fall back on static value\n",
2085 __func__, __LINE__);
2089 * The dynamically calculated dtaps_per_ptap is only valid if we
2090 * found a passing/failing read. If we didn't, it means d hit the max
2091 * (seq->iocfg->dqs_en_delay_max). Otherwise, dtaps_per_ptap retains its
2092 * statically calculated value.
2094 if (found_passing_read && found_failing_read)
2095 dtaps_per_ptap = d - initial_failing_dtap;
2097 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
2098 debug_cond(DLEVEL >= 2, "%s:%d dtaps_per_ptap=%u - %u = %u",
2099 __func__, __LINE__, d, initial_failing_dtap, dtaps_per_ptap);
2101 /* Step 6: Find the centre of the window. */
2102 ret = sdr_find_window_center(seq, grp, work_bgn, work_end);
2108 * search_stop_check() - Check if the detected edge is valid
2109 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2111 * @rank_bgn: Rank number
2112 * @write_group: Write Group
2113 * @read_group: Read Group
2114 * @bit_chk: Resulting bit mask after the test
2115 * @sticky_bit_chk: Resulting sticky bit mask after the test
2116 * @use_read_test: Perform read test
2118 * Test if the found edge is valid.
2120 static u32 search_stop_check(struct socfpga_sdrseq *seq, const int write,
2121 const int d, const int rank_bgn,
2122 const u32 write_group, const u32 read_group,
2123 u32 *bit_chk, u32 *sticky_bit_chk,
2124 const u32 use_read_test)
2126 const u32 ratio = seq->rwcfg->mem_if_read_dqs_width /
2127 seq->rwcfg->mem_if_write_dqs_width;
2128 const u32 correct_mask = write ? seq->param.write_correct_mask :
2129 seq->param.read_correct_mask;
2130 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2131 seq->rwcfg->mem_dq_per_read_dqs;
2134 * Stop searching when the read test doesn't pass AND when
2135 * we've seen a passing read on every bit.
2137 if (write) { /* WRITE-ONLY */
2138 ret = !rw_mgr_mem_calibrate_write_test(seq, rank_bgn,
2140 PASS_ONE_BIT, bit_chk,
2142 } else if (use_read_test) { /* READ-ONLY */
2143 ret = !rw_mgr_mem_calibrate_read_test(seq, rank_bgn, read_group,
2145 PASS_ONE_BIT, bit_chk,
2147 } else { /* READ-ONLY */
2148 rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group, 0,
2149 PASS_ONE_BIT, bit_chk, 0);
2150 *bit_chk = *bit_chk >> (per_dqs *
2151 (read_group - (write_group * ratio)));
2152 ret = (*bit_chk == 0);
2154 *sticky_bit_chk = *sticky_bit_chk | *bit_chk;
2155 ret = ret && (*sticky_bit_chk == correct_mask);
2156 debug_cond(DLEVEL >= 2,
2157 "%s:%d center(left): dtap=%u => %u == %u && %u",
2158 __func__, __LINE__, d,
2159 *sticky_bit_chk, correct_mask, ret);
2164 * search_left_edge() - Find left edge of DQ/DQS working phase
2165 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2166 * @rank_bgn: Rank number
2167 * @write_group: Write Group
2168 * @read_group: Read Group
2169 * @test_bgn: Rank number to begin the test
2170 * @sticky_bit_chk: Resulting sticky bit mask after the test
2171 * @left_edge: Left edge of the DQ/DQS phase
2172 * @right_edge: Right edge of the DQ/DQS phase
2173 * @use_read_test: Perform read test
2175 * Find left edge of DQ/DQS working phase.
2177 static void search_left_edge(struct socfpga_sdrseq *seq, const int write,
2178 const int rank_bgn, const u32 write_group,
2179 const u32 read_group, const u32 test_bgn,
2180 u32 *sticky_bit_chk, int *left_edge,
2181 int *right_edge, const u32 use_read_test)
2183 const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2184 seq->iocfg->io_in_delay_max;
2185 const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
2186 seq->iocfg->dqs_in_delay_max;
2187 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2188 seq->rwcfg->mem_dq_per_read_dqs;
2192 for (d = 0; d <= dqs_max; d++) {
2194 scc_mgr_apply_group_dq_out1_delay(seq, d);
2196 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, d);
2198 writel(0, &sdr_scc_mgr->update);
2200 stop = search_stop_check(seq, write, d, rank_bgn, write_group,
2201 read_group, &bit_chk, sticky_bit_chk,
2207 for (i = 0; i < per_dqs; i++) {
2210 * Remember a passing test as
2216 * If a left edge has not been seen
2217 * yet, then a future passing test
2218 * will mark this edge as the right
2221 if (left_edge[i] == delay_max + 1)
2222 right_edge[i] = -(d + 1);
2228 /* Reset DQ delay chains to 0 */
2230 scc_mgr_apply_group_dq_out1_delay(seq, 0);
2232 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
2234 *sticky_bit_chk = 0;
2235 for (i = per_dqs - 1; i >= 0; i--) {
2236 debug_cond(DLEVEL >= 2,
2237 "%s:%d vfifo_center: left_edge[%u]: %d right_edge[%u]: %d\n",
2238 __func__, __LINE__, i, left_edge[i],
2242 * Check for cases where we haven't found the left edge,
2243 * which makes our assignment of the the right edge invalid.
2244 * Reset it to the illegal value.
2246 if ((left_edge[i] == delay_max + 1) &&
2247 (right_edge[i] != delay_max + 1)) {
2248 right_edge[i] = delay_max + 1;
2249 debug_cond(DLEVEL >= 2,
2250 "%s:%d vfifo_center: reset right_edge[%u]: %d\n",
2251 __func__, __LINE__, i, right_edge[i]);
2256 * READ: except for bits where we have seen both
2257 * the left and right edge.
2258 * WRITE: except for bits where we have seen the
2261 *sticky_bit_chk <<= 1;
2263 if (left_edge[i] != delay_max + 1)
2264 *sticky_bit_chk |= 1;
2266 if ((left_edge[i] != delay_max + 1) &&
2267 (right_edge[i] != delay_max + 1))
2268 *sticky_bit_chk |= 1;
2274 * search_right_edge() - Find right edge of DQ/DQS working phase
2275 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2276 * @rank_bgn: Rank number
2277 * @write_group: Write Group
2278 * @read_group: Read Group
2279 * @start_dqs: DQS start phase
2280 * @start_dqs_en: DQS enable start phase
2281 * @sticky_bit_chk: Resulting sticky bit mask after the test
2282 * @left_edge: Left edge of the DQ/DQS phase
2283 * @right_edge: Right edge of the DQ/DQS phase
2284 * @use_read_test: Perform read test
2286 * Find right edge of DQ/DQS working phase.
2288 static int search_right_edge(struct socfpga_sdrseq *seq, const int write,
2289 const int rank_bgn, const u32 write_group,
2290 const u32 read_group, const int start_dqs,
2291 const int start_dqs_en, u32 *sticky_bit_chk,
2292 int *left_edge, int *right_edge,
2293 const u32 use_read_test)
2295 const u32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2296 seq->iocfg->io_in_delay_max;
2297 const u32 dqs_max = write ? seq->iocfg->io_out1_delay_max :
2298 seq->iocfg->dqs_in_delay_max;
2299 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2300 seq->rwcfg->mem_dq_per_read_dqs;
2304 for (d = 0; d <= dqs_max - start_dqs; d++) {
2305 if (write) { /* WRITE-ONLY */
2306 scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
2309 } else { /* READ-ONLY */
2310 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
2311 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2312 u32 delay = d + start_dqs_en;
2313 if (delay > seq->iocfg->dqs_en_delay_max)
2314 delay = seq->iocfg->dqs_en_delay_max;
2315 scc_mgr_set_dqs_en_delay(read_group, delay);
2317 scc_mgr_load_dqs(read_group);
2320 writel(0, &sdr_scc_mgr->update);
2322 stop = search_stop_check(seq, write, d, rank_bgn, write_group,
2323 read_group, &bit_chk, sticky_bit_chk,
2326 if (write && (d == 0)) { /* WRITE-ONLY */
2328 i < seq->rwcfg->mem_dq_per_write_dqs;
2331 * d = 0 failed, but it passed when
2332 * testing the left edge, so it must be
2333 * marginal, set it to -1
2335 if (right_edge[i] == delay_max + 1 &&
2336 left_edge[i] != delay_max + 1)
2344 for (i = 0; i < per_dqs; i++) {
2347 * Remember a passing test as
2354 * If a right edge has not
2355 * been seen yet, then a future
2356 * passing test will mark this
2357 * edge as the left edge.
2359 if (right_edge[i] == delay_max + 1)
2360 left_edge[i] = -(d + 1);
2363 * d = 0 failed, but it passed
2364 * when testing the left edge,
2365 * so it must be marginal, set
2368 if (right_edge[i] == delay_max + 1 &&
2369 left_edge[i] != delay_max + 1)
2372 * If a right edge has not been
2373 * seen yet, then a future
2374 * passing test will mark this
2375 * edge as the left edge.
2377 else if (right_edge[i] == delay_max + 1)
2378 left_edge[i] = -(d + 1);
2382 debug_cond(DLEVEL >= 2, "%s:%d center[r,d=%u]: ",
2383 __func__, __LINE__, d);
2384 debug_cond(DLEVEL >= 2,
2385 "bit_chk_test=%i left_edge[%u]: %d ",
2386 bit_chk & 1, i, left_edge[i]);
2387 debug_cond(DLEVEL >= 2, "right_edge[%u]: %d\n", i,
2393 /* Check that all bits have a window */
2394 for (i = 0; i < per_dqs; i++) {
2395 debug_cond(DLEVEL >= 2,
2396 "%s:%d write_center: left_edge[%u]: %d right_edge[%u]: %d",
2397 __func__, __LINE__, i, left_edge[i],
2399 if ((left_edge[i] == dqs_max + 1) ||
2400 (right_edge[i] == dqs_max + 1))
2401 return i + 1; /* FIXME: If we fail, retval > 0 */
2408 * get_window_mid_index() - Find the best middle setting of DQ/DQS phase
2409 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2410 * @left_edge: Left edge of the DQ/DQS phase
2411 * @right_edge: Right edge of the DQ/DQS phase
2412 * @mid_min: Best DQ/DQS phase middle setting
2414 * Find index and value of the middle of the DQ/DQS working phase.
2416 static int get_window_mid_index(struct socfpga_sdrseq *seq,
2417 const int write, int *left_edge,
2418 int *right_edge, int *mid_min)
2420 const u32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2421 seq->rwcfg->mem_dq_per_read_dqs;
2422 int i, mid, min_index;
2424 /* Find middle of window for each DQ bit */
2425 *mid_min = left_edge[0] - right_edge[0];
2427 for (i = 1; i < per_dqs; i++) {
2428 mid = left_edge[i] - right_edge[i];
2429 if (mid < *mid_min) {
2436 * -mid_min/2 represents the amount that we need to move DQS.
2437 * If mid_min is odd and positive we'll need to add one to make
2438 * sure the rounding in further calculations is correct (always
2439 * bias to the right), so just add 1 for all positive values.
2443 *mid_min = *mid_min / 2;
2445 debug_cond(DLEVEL >= 1, "%s:%d vfifo_center: *mid_min=%d (index=%u)\n",
2446 __func__, __LINE__, *mid_min, min_index);
2451 * center_dq_windows() - Center the DQ/DQS windows
2452 * @write: Perform read (Stage 2) or write (Stage 3) calibration
2453 * @left_edge: Left edge of the DQ/DQS phase
2454 * @right_edge: Right edge of the DQ/DQS phase
2455 * @mid_min: Adjusted DQ/DQS phase middle setting
2456 * @orig_mid_min: Original DQ/DQS phase middle setting
2457 * @min_index: DQ/DQS phase middle setting index
2458 * @test_bgn: Rank number to begin the test
2459 * @dq_margin: Amount of shift for the DQ
2460 * @dqs_margin: Amount of shift for the DQS
2462 * Align the DQ/DQS windows in each group.
2464 static void center_dq_windows(struct socfpga_sdrseq *seq,
2465 const int write, int *left_edge, int *right_edge,
2466 const int mid_min, const int orig_mid_min,
2467 const int min_index, const int test_bgn,
2468 int *dq_margin, int *dqs_margin)
2470 const s32 delay_max = write ? seq->iocfg->io_out1_delay_max :
2471 seq->iocfg->io_in_delay_max;
2472 const s32 per_dqs = write ? seq->rwcfg->mem_dq_per_write_dqs :
2473 seq->rwcfg->mem_dq_per_read_dqs;
2474 const s32 delay_off = write ? SCC_MGR_IO_OUT1_DELAY_OFFSET :
2475 SCC_MGR_IO_IN_DELAY_OFFSET;
2476 const s32 addr = SDR_PHYGRP_SCCGRP_ADDRESS | delay_off;
2478 s32 temp_dq_io_delay1;
2481 /* Initialize data for export structures */
2482 *dqs_margin = delay_max + 1;
2483 *dq_margin = delay_max + 1;
2485 /* add delay to bring centre of all DQ windows to the same "level" */
2486 for (i = 0, p = test_bgn; i < per_dqs; i++, p++) {
2487 /* Use values before divide by 2 to reduce round off error */
2488 shift_dq = (left_edge[i] - right_edge[i] -
2489 (left_edge[min_index] - right_edge[min_index]))/2 +
2490 (orig_mid_min - mid_min);
2492 debug_cond(DLEVEL >= 2,
2493 "vfifo_center: before: shift_dq[%u]=%d\n",
2496 temp_dq_io_delay1 = readl(addr + (i << 2));
2498 if (shift_dq + temp_dq_io_delay1 > delay_max)
2499 shift_dq = delay_max - temp_dq_io_delay1;
2500 else if (shift_dq + temp_dq_io_delay1 < 0)
2501 shift_dq = -temp_dq_io_delay1;
2503 debug_cond(DLEVEL >= 2,
2504 "vfifo_center: after: shift_dq[%u]=%d\n",
2508 scc_mgr_set_dq_out1_delay(i,
2509 temp_dq_io_delay1 + shift_dq);
2511 scc_mgr_set_dq_in_delay(p,
2512 temp_dq_io_delay1 + shift_dq);
2516 debug_cond(DLEVEL >= 2,
2517 "vfifo_center: margin[%u]=[%d,%d]\n", i,
2518 left_edge[i] - shift_dq + (-mid_min),
2519 right_edge[i] + shift_dq - (-mid_min));
2521 /* To determine values for export structures */
2522 if (left_edge[i] - shift_dq + (-mid_min) < *dq_margin)
2523 *dq_margin = left_edge[i] - shift_dq + (-mid_min);
2525 if (right_edge[i] + shift_dq - (-mid_min) < *dqs_margin)
2526 *dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2531 * rw_mgr_mem_calibrate_vfifo_center() - Per-bit deskew DQ and centering
2532 * @rank_bgn: Rank number
2533 * @rw_group: Read/Write Group
2534 * @test_bgn: Rank at which the test begins
2535 * @use_read_test: Perform a read test
2536 * @update_fom: Update FOM
2538 * Per-bit deskew DQ and centering.
2540 static int rw_mgr_mem_calibrate_vfifo_center(struct socfpga_sdrseq *seq,
2544 const int use_read_test,
2545 const int update_fom)
2548 SDR_PHYGRP_SCCGRP_ADDRESS + SCC_MGR_DQS_IN_DELAY_OFFSET +
2551 * Store these as signed since there are comparisons with
2555 s32 left_edge[seq->rwcfg->mem_dq_per_read_dqs];
2556 s32 right_edge[seq->rwcfg->mem_dq_per_read_dqs];
2557 s32 orig_mid_min, mid_min;
2558 s32 new_dqs, start_dqs, start_dqs_en = 0, final_dqs_en;
2559 s32 dq_margin, dqs_margin;
2563 debug("%s:%d: %u %u", __func__, __LINE__, rw_group, test_bgn);
2565 start_dqs = readl(addr);
2566 if (seq->iocfg->shift_dqs_en_when_shift_dqs)
2567 start_dqs_en = readl(addr - seq->iocfg->dqs_en_delay_offset);
2569 /* set the left and right edge of each bit to an illegal value */
2570 /* use (seq->iocfg->io_in_delay_max + 1) as an illegal value */
2572 for (i = 0; i < seq->rwcfg->mem_dq_per_read_dqs; i++) {
2573 left_edge[i] = seq->iocfg->io_in_delay_max + 1;
2574 right_edge[i] = seq->iocfg->io_in_delay_max + 1;
2577 /* Search for the left edge of the window for each bit */
2578 search_left_edge(seq, 0, rank_bgn, rw_group, rw_group, test_bgn,
2580 left_edge, right_edge, use_read_test);
2583 /* Search for the right edge of the window for each bit */
2584 ret = search_right_edge(seq, 0, rank_bgn, rw_group, rw_group,
2585 start_dqs, start_dqs_en,
2587 left_edge, right_edge, use_read_test);
2590 * Restore delay chain settings before letting the loop
2591 * in rw_mgr_mem_calibrate_vfifo to retry different
2592 * dqs/ck relationships.
2594 scc_mgr_set_dqs_bus_in_delay(rw_group, start_dqs);
2595 if (seq->iocfg->shift_dqs_en_when_shift_dqs)
2596 scc_mgr_set_dqs_en_delay(rw_group, start_dqs_en);
2598 scc_mgr_load_dqs(rw_group);
2599 writel(0, &sdr_scc_mgr->update);
2601 debug_cond(DLEVEL >= 1,
2602 "%s:%d vfifo_center: failed to find edge [%u]: %d %d",
2603 __func__, __LINE__, i, left_edge[i], right_edge[i]);
2604 if (use_read_test) {
2605 set_failing_group_stage(seq, rw_group *
2606 seq->rwcfg->mem_dq_per_read_dqs + i,
2608 CAL_SUBSTAGE_VFIFO_CENTER);
2610 set_failing_group_stage(seq, rw_group *
2611 seq->rwcfg->mem_dq_per_read_dqs + i,
2612 CAL_STAGE_VFIFO_AFTER_WRITES,
2613 CAL_SUBSTAGE_VFIFO_CENTER);
2618 min_index = get_window_mid_index(seq, 0, left_edge, right_edge,
2621 /* Determine the amount we can change DQS (which is -mid_min) */
2622 orig_mid_min = mid_min;
2623 new_dqs = start_dqs - mid_min;
2624 if (new_dqs > seq->iocfg->dqs_in_delay_max)
2625 new_dqs = seq->iocfg->dqs_in_delay_max;
2626 else if (new_dqs < 0)
2629 mid_min = start_dqs - new_dqs;
2630 debug_cond(DLEVEL >= 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2633 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2634 if (start_dqs_en - mid_min > seq->iocfg->dqs_en_delay_max)
2635 mid_min += start_dqs_en - mid_min -
2636 seq->iocfg->dqs_en_delay_max;
2637 else if (start_dqs_en - mid_min < 0)
2638 mid_min += start_dqs_en - mid_min;
2640 new_dqs = start_dqs - mid_min;
2642 debug_cond(DLEVEL >= 1,
2643 "vfifo_center: start_dqs=%d start_dqs_en=%d new_dqs=%d mid_min=%d\n",
2645 seq->iocfg->shift_dqs_en_when_shift_dqs ? start_dqs_en : -1,
2648 /* Add delay to bring centre of all DQ windows to the same "level". */
2649 center_dq_windows(seq, 0, left_edge, right_edge, mid_min, orig_mid_min,
2650 min_index, test_bgn, &dq_margin, &dqs_margin);
2653 if (seq->iocfg->shift_dqs_en_when_shift_dqs) {
2654 final_dqs_en = start_dqs_en - mid_min;
2655 scc_mgr_set_dqs_en_delay(rw_group, final_dqs_en);
2656 scc_mgr_load_dqs(rw_group);
2660 scc_mgr_set_dqs_bus_in_delay(rw_group, new_dqs);
2661 scc_mgr_load_dqs(rw_group);
2662 debug_cond(DLEVEL >= 2,
2663 "%s:%d vfifo_center: dq_margin=%d dqs_margin=%d",
2664 __func__, __LINE__, dq_margin, dqs_margin);
2667 * Do not remove this line as it makes sure all of our decisions
2668 * have been applied. Apply the update bit.
2670 writel(0, &sdr_scc_mgr->update);
2672 if ((dq_margin < 0) || (dqs_margin < 0))
2679 * rw_mgr_mem_calibrate_guaranteed_write() - Perform guaranteed write into the
2681 * @rw_group: Read/Write Group
2682 * @phase: DQ/DQS phase
2684 * Because initially no communication ca be reliably performed with the memory
2685 * device, the sequencer uses a guaranteed write mechanism to write data into
2686 * the memory device.
2688 static int rw_mgr_mem_calibrate_guaranteed_write(struct socfpga_sdrseq *seq,
2694 /* Set a particular DQ/DQS phase. */
2695 scc_mgr_set_dqdqs_output_phase_all_ranks(seq, rw_group, phase);
2697 debug_cond(DLEVEL >= 1, "%s:%d guaranteed write: g=%u p=%u\n",
2698 __func__, __LINE__, rw_group, phase);
2701 * Altera EMI_RM 2015.05.04 :: Figure 1-25
2702 * Load up the patterns used by read calibration using the
2703 * current DQDQS phase.
2705 rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
2707 if (seq->gbl.phy_debug_mode_flags & PHY_DEBUG_DISABLE_GUARANTEED_READ)
2711 * Altera EMI_RM 2015.05.04 :: Figure 1-26
2712 * Back-to-Back reads of the patterns used for calibration.
2714 ret = rw_mgr_mem_calibrate_read_test_patterns(seq, 0, rw_group, 1);
2716 debug_cond(DLEVEL >= 1,
2717 "%s:%d Guaranteed read test failed: g=%u p=%u\n",
2718 __func__, __LINE__, rw_group, phase);
2723 * rw_mgr_mem_calibrate_dqs_enable_calibration() - DQS Enable Calibration
2724 * @rw_group: Read/Write Group
2725 * @test_bgn: Rank at which the test begins
2727 * DQS enable calibration ensures reliable capture of the DQ signal without
2728 * glitches on the DQS line.
2731 rw_mgr_mem_calibrate_dqs_enable_calibration(struct socfpga_sdrseq *seq,
2736 * Altera EMI_RM 2015.05.04 :: Figure 1-27
2737 * DQS and DQS Eanble Signal Relationships.
2740 /* We start at zero, so have one less dq to devide among */
2741 const u32 delay_step = seq->iocfg->io_in_delay_max /
2742 (seq->rwcfg->mem_dq_per_read_dqs - 1);
2746 debug("%s:%d (%u,%u)\n", __func__, __LINE__, rw_group, test_bgn);
2748 /* Try different dq_in_delays since the DQ path is shorter than DQS. */
2749 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
2750 r += NUM_RANKS_PER_SHADOW_REG) {
2751 for (i = 0, p = test_bgn, d = 0;
2752 i < seq->rwcfg->mem_dq_per_read_dqs;
2753 i++, p++, d += delay_step) {
2754 debug_cond(DLEVEL >= 1,
2755 "%s:%d: g=%u r=%u i=%u p=%u d=%u\n",
2756 __func__, __LINE__, rw_group, r, i, p, d);
2758 scc_mgr_set_dq_in_delay(p, d);
2762 writel(0, &sdr_scc_mgr->update);
2766 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
2767 * dq_in_delay values
2769 ret = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(seq, rw_group);
2771 debug_cond(DLEVEL >= 1,
2772 "%s:%d: g=%u found=%u; Reseting delay chain to zero\n",
2773 __func__, __LINE__, rw_group, !ret);
2775 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
2776 r += NUM_RANKS_PER_SHADOW_REG) {
2777 scc_mgr_apply_group_dq_in_delay(seq, test_bgn, 0);
2778 writel(0, &sdr_scc_mgr->update);
2785 * rw_mgr_mem_calibrate_dq_dqs_centering() - Centering DQ/DQS
2786 * @rw_group: Read/Write Group
2787 * @test_bgn: Rank at which the test begins
2788 * @use_read_test: Perform a read test
2789 * @update_fom: Update FOM
2791 * The centerin DQ/DQS stage attempts to align DQ and DQS signals on reads
2795 rw_mgr_mem_calibrate_dq_dqs_centering(struct socfpga_sdrseq *seq,
2796 const u32 rw_group, const u32 test_bgn,
2797 const int use_read_test,
2798 const int update_fom)
2801 int ret, grp_calibrated;
2805 * Altera EMI_RM 2015.05.04 :: Figure 1-28
2806 * Read per-bit deskew can be done on a per shadow register basis.
2809 for (rank_bgn = 0, sr = 0;
2810 rank_bgn < seq->rwcfg->mem_number_of_ranks;
2811 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
2812 ret = rw_mgr_mem_calibrate_vfifo_center(seq, rank_bgn, rw_group,
2822 if (!grp_calibrated)
2829 * rw_mgr_mem_calibrate_vfifo() - Calibrate the read valid prediction FIFO
2830 * @rw_group: Read/Write Group
2831 * @test_bgn: Rank at which the test begins
2833 * Stage 1: Calibrate the read valid prediction FIFO.
2835 * This function implements UniPHY calibration Stage 1, as explained in
2836 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2838 * - read valid prediction will consist of finding:
2839 * - DQS enable phase and DQS enable delay (DQS Enable Calibration)
2840 * - DQS input phase and DQS input delay (DQ/DQS Centering)
2841 * - we also do a per-bit deskew on the DQ lines.
2843 static int rw_mgr_mem_calibrate_vfifo(struct socfpga_sdrseq *seq,
2844 const u32 rw_group, const u32 test_bgn)
2848 u32 failed_substage;
2852 debug("%s:%d: %u %u\n", __func__, __LINE__, rw_group, test_bgn);
2854 /* Update info for sims */
2855 reg_file_set_group(rw_group);
2856 reg_file_set_stage(CAL_STAGE_VFIFO);
2857 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2859 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2861 /* USER Determine number of delay taps for each phase tap. */
2862 dtaps_per_ptap = DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
2863 seq->iocfg->delay_per_dqs_en_dchain_tap)
2866 for (d = 0; d <= dtaps_per_ptap; d += 2) {
2868 * In RLDRAMX we may be messing the delay of pins in
2869 * the same write rw_group but outside of the current read
2870 * the rw_group, but that's ok because we haven't calibrated
2874 scc_mgr_apply_group_all_out_delay_add_all_ranks(seq,
2879 for (p = 0; p <= seq->iocfg->dqdqs_out_phase_max; p++) {
2880 /* 1) Guaranteed Write */
2881 ret = rw_mgr_mem_calibrate_guaranteed_write(seq,
2887 /* 2) DQS Enable Calibration */
2888 ret = rw_mgr_mem_calibrate_dqs_enable_calibration(seq,
2892 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2896 /* 3) Centering DQ/DQS */
2898 * If doing read after write calibration, do not update
2899 * FOM now. Do it then.
2901 ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq,
2906 failed_substage = CAL_SUBSTAGE_VFIFO_CENTER;
2915 /* Calibration Stage 1 failed. */
2916 set_failing_group_stage(seq, rw_group, CAL_STAGE_VFIFO,
2920 /* Calibration Stage 1 completed OK. */
2923 * Reset the delay chains back to zero if they have moved > 1
2924 * (check for > 1 because loop will increase d even when pass in
2928 scc_mgr_zero_group(seq, rw_group, 1);
2934 * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
2935 * @rw_group: Read/Write Group
2936 * @test_bgn: Rank at which the test begins
2938 * Stage 3: DQ/DQS Centering.
2940 * This function implements UniPHY calibration Stage 3, as explained in
2941 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2943 static int rw_mgr_mem_calibrate_vfifo_end(struct socfpga_sdrseq *seq,
2949 debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
2951 /* Update info for sims. */
2952 reg_file_set_group(rw_group);
2953 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2954 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2956 ret = rw_mgr_mem_calibrate_dq_dqs_centering(seq, rw_group, test_bgn, 0,
2959 set_failing_group_stage(seq, rw_group,
2960 CAL_STAGE_VFIFO_AFTER_WRITES,
2961 CAL_SUBSTAGE_VFIFO_CENTER);
2966 * rw_mgr_mem_calibrate_lfifo() - Minimize latency
2968 * Stage 4: Minimize latency.
2970 * This function implements UniPHY calibration Stage 4, as explained in
2971 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
2972 * Calibrate LFIFO to find smallest read latency.
2974 static u32 rw_mgr_mem_calibrate_lfifo(struct socfpga_sdrseq *seq)
2978 debug("%s:%d\n", __func__, __LINE__);
2980 /* Update info for sims. */
2981 reg_file_set_stage(CAL_STAGE_LFIFO);
2982 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2984 /* Load up the patterns used by read calibration for all ranks */
2985 rw_mgr_mem_calibrate_read_load_patterns(seq, 0, 1);
2988 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
2989 debug_cond(DLEVEL >= 2, "%s:%d lfifo: read_lat=%u",
2990 __func__, __LINE__, seq->gbl.curr_read_lat);
2992 if (!rw_mgr_mem_calibrate_read_test_all_ranks(seq, 0,
2999 * Reduce read latency and see if things are
3000 * working correctly.
3002 seq->gbl.curr_read_lat--;
3003 } while (seq->gbl.curr_read_lat > 0);
3005 /* Reset the fifos to get pointers to known state. */
3006 writel(0, &phy_mgr_cmd->fifo_reset);
3009 /* Add a fudge factor to the read latency that was determined */
3010 seq->gbl.curr_read_lat += 2;
3011 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3012 debug_cond(DLEVEL >= 2,
3013 "%s:%d lfifo: success: using read_lat=%u\n",
3014 __func__, __LINE__, seq->gbl.curr_read_lat);
3016 set_failing_group_stage(seq, 0xff, CAL_STAGE_LFIFO,
3017 CAL_SUBSTAGE_READ_LATENCY);
3019 debug_cond(DLEVEL >= 2,
3020 "%s:%d lfifo: failed at initial read_lat=%u\n",
3021 __func__, __LINE__, seq->gbl.curr_read_lat);
3028 * search_window() - Search for the/part of the window with DM/DQS shift
3029 * @search_dm: If 1, search for the DM shift, if 0, search for DQS
3031 * @rank_bgn: Rank number
3032 * @write_group: Write Group
3033 * @bgn_curr: Current window begin
3034 * @end_curr: Current window end
3035 * @bgn_best: Current best window begin
3036 * @end_best: Current best window end
3037 * @win_best: Size of the best window
3038 * @new_dqs: New DQS value (only applicable if search_dm = 0).
3040 * Search for the/part of the window with DM/DQS shift.
3042 static void search_window(struct socfpga_sdrseq *seq,
3043 const int search_dm, const u32 rank_bgn,
3044 const u32 write_group, int *bgn_curr, int *end_curr,
3045 int *bgn_best, int *end_best, int *win_best,
3049 const int max = seq->iocfg->io_out1_delay_max - new_dqs;
3052 /* Search for the/part of the window with DM/DQS shift. */
3053 for (di = max; di >= 0; di -= DELTA_D) {
3056 scc_mgr_apply_group_dm_out1_delay(seq, d);
3058 /* For DQS, we go from 0...max */
3061 * Note: This only shifts DQS, so are we limiting
3062 * ourselves to width of DQ unnecessarily.
3064 scc_mgr_apply_group_dqs_io_and_oct_out1(seq,
3069 writel(0, &sdr_scc_mgr->update);
3071 if (rw_mgr_mem_calibrate_write_test(seq, rank_bgn, write_group,
3072 1, PASS_ALL_BITS, &bit_chk,
3074 /* Set current end of the window. */
3075 *end_curr = search_dm ? -d : d;
3078 * If a starting edge of our window has not been seen
3079 * this is our current start of the DM window.
3081 if (*bgn_curr == seq->iocfg->io_out1_delay_max + 1)
3082 *bgn_curr = search_dm ? -d : d;
3085 * If current window is bigger than best seen.
3086 * Set best seen to be current window.
3088 if ((*end_curr - *bgn_curr + 1) > *win_best) {
3089 *win_best = *end_curr - *bgn_curr + 1;
3090 *bgn_best = *bgn_curr;
3091 *end_best = *end_curr;
3094 /* We just saw a failing test. Reset temp edge. */
3095 *bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3096 *end_curr = seq->iocfg->io_out1_delay_max + 1;
3098 /* Early exit is only applicable to DQS. */
3103 * Early exit optimization: if the remaining delay
3104 * chain space is less than already seen largest
3105 * window we can exit.
3107 if (*win_best - 1 > seq->iocfg->io_out1_delay_max
3115 * rw_mgr_mem_calibrate_writes_center() - Center all windows
3116 * @rank_bgn: Rank number
3117 * @write_group: Write group
3118 * @test_bgn: Rank at which the test begins
3120 * Center all windows. Do per-bit-deskew to possibly increase size of
3124 rw_mgr_mem_calibrate_writes_center(struct socfpga_sdrseq *seq,
3125 const u32 rank_bgn, const u32 write_group,
3131 int left_edge[seq->rwcfg->mem_dq_per_write_dqs];
3132 int right_edge[seq->rwcfg->mem_dq_per_write_dqs];
3134 int mid_min, orig_mid_min;
3135 int new_dqs, start_dqs;
3136 int dq_margin, dqs_margin, dm_margin;
3137 int bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3138 int end_curr = seq->iocfg->io_out1_delay_max + 1;
3139 int bgn_best = seq->iocfg->io_out1_delay_max + 1;
3140 int end_best = seq->iocfg->io_out1_delay_max + 1;
3145 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
3149 start_dqs = readl((SDR_PHYGRP_SCCGRP_ADDRESS |
3150 SCC_MGR_IO_OUT1_DELAY_OFFSET) +
3151 (seq->rwcfg->mem_dq_per_write_dqs << 2));
3153 /* Per-bit deskew. */
3156 * Set the left and right edge of each bit to an illegal value.
3157 * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value.
3160 for (i = 0; i < seq->rwcfg->mem_dq_per_write_dqs; i++) {
3161 left_edge[i] = seq->iocfg->io_out1_delay_max + 1;
3162 right_edge[i] = seq->iocfg->io_out1_delay_max + 1;
3165 /* Search for the left edge of the window for each bit. */
3166 search_left_edge(seq, 1, rank_bgn, write_group, 0, test_bgn,
3168 left_edge, right_edge, 0);
3170 /* Search for the right edge of the window for each bit. */
3171 ret = search_right_edge(seq, 1, rank_bgn, write_group, 0,
3174 left_edge, right_edge, 0);
3176 set_failing_group_stage(seq, test_bgn + ret - 1,
3178 CAL_SUBSTAGE_WRITES_CENTER);
3182 min_index = get_window_mid_index(seq, 1, left_edge, right_edge,
3185 /* Determine the amount we can change DQS (which is -mid_min). */
3186 orig_mid_min = mid_min;
3187 new_dqs = start_dqs;
3189 debug_cond(DLEVEL >= 1,
3190 "%s:%d write_center: start_dqs=%d new_dqs=%d mid_min=%d\n",
3191 __func__, __LINE__, start_dqs, new_dqs, mid_min);
3193 /* Add delay to bring centre of all DQ windows to the same "level". */
3194 center_dq_windows(seq, 1, left_edge, right_edge, mid_min, orig_mid_min,
3195 min_index, 0, &dq_margin, &dqs_margin);
3198 scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
3199 writel(0, &sdr_scc_mgr->update);
3202 debug_cond(DLEVEL >= 2, "%s:%d write_center: DM\n", __func__, __LINE__);
3205 * Set the left and right edge of each bit to an illegal value.
3206 * Use (seq->iocfg->io_out1_delay_max + 1) as an illegal value.
3208 left_edge[0] = seq->iocfg->io_out1_delay_max + 1;
3209 right_edge[0] = seq->iocfg->io_out1_delay_max + 1;
3211 /* Search for the/part of the window with DM shift. */
3212 search_window(seq, 1, rank_bgn, write_group, &bgn_curr, &end_curr,
3213 &bgn_best, &end_best, &win_best, 0);
3215 /* Reset DM delay chains to 0. */
3216 scc_mgr_apply_group_dm_out1_delay(seq, 0);
3219 * Check to see if the current window nudges up aganist 0 delay.
3220 * If so we need to continue the search by shifting DQS otherwise DQS
3221 * search begins as a new search.
3223 if (end_curr != 0) {
3224 bgn_curr = seq->iocfg->io_out1_delay_max + 1;
3225 end_curr = seq->iocfg->io_out1_delay_max + 1;
3228 /* Search for the/part of the window with DQS shifts. */
3229 search_window(seq, 0, rank_bgn, write_group, &bgn_curr, &end_curr,
3230 &bgn_best, &end_best, &win_best, new_dqs);
3232 /* Assign left and right edge for cal and reporting. */
3233 left_edge[0] = -1 * bgn_best;
3234 right_edge[0] = end_best;
3236 debug_cond(DLEVEL >= 2, "%s:%d dm_calib: left=%d right=%d\n",
3237 __func__, __LINE__, left_edge[0], right_edge[0]);
3239 /* Move DQS (back to orig). */
3240 scc_mgr_apply_group_dqs_io_and_oct_out1(seq, write_group, new_dqs);
3244 /* Find middle of window for the DM bit. */
3245 mid = (left_edge[0] - right_edge[0]) / 2;
3247 /* Only move right, since we are not moving DQS/DQ. */
3251 /* dm_marign should fail if we never find a window. */
3255 dm_margin = left_edge[0] - mid;
3257 scc_mgr_apply_group_dm_out1_delay(seq, mid);
3258 writel(0, &sdr_scc_mgr->update);
3260 debug_cond(DLEVEL >= 2,
3261 "%s:%d dm_calib: left=%d right=%d mid=%d dm_margin=%d\n",
3262 __func__, __LINE__, left_edge[0], right_edge[0],
3264 /* Export values. */
3265 seq->gbl.fom_out += dq_margin + dqs_margin;
3267 debug_cond(DLEVEL >= 2,
3268 "%s:%d write_center: dq_margin=%d dqs_margin=%d dm_margin=%d\n",
3269 __func__, __LINE__, dq_margin, dqs_margin, dm_margin);
3272 * Do not remove this line as it makes sure all of our
3273 * decisions have been applied.
3275 writel(0, &sdr_scc_mgr->update);
3277 if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
3284 * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
3285 * @rank_bgn: Rank number
3286 * @group: Read/Write Group
3287 * @test_bgn: Rank at which the test begins
3289 * Stage 2: Write Calibration Part One.
3291 * This function implements UniPHY calibration Stage 2, as explained in
3292 * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
3294 static int rw_mgr_mem_calibrate_writes(struct socfpga_sdrseq *seq,
3295 const u32 rank_bgn, const u32 group,
3300 /* Update info for sims */
3301 debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
3303 reg_file_set_group(group);
3304 reg_file_set_stage(CAL_STAGE_WRITES);
3305 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3307 ret = rw_mgr_mem_calibrate_writes_center(seq, rank_bgn, group,
3310 set_failing_group_stage(seq, group, CAL_STAGE_WRITES,
3311 CAL_SUBSTAGE_WRITES_CENTER);
3317 * mem_precharge_and_activate() - Precharge all banks and activate
3319 * Precharge all banks and activate row 0 in bank "000..." and bank "111...".
3321 static void mem_precharge_and_activate(struct socfpga_sdrseq *seq)
3325 for (r = 0; r < seq->rwcfg->mem_number_of_ranks; r++) {
3327 set_rank_and_odt_mask(seq, r, RW_MGR_ODT_MODE_OFF);
3329 /* Precharge all banks. */
3330 writel(seq->rwcfg->precharge_all, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3331 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3333 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3334 writel(seq->rwcfg->activate_0_and_1_wait1,
3335 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3337 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3338 writel(seq->rwcfg->activate_0_and_1_wait2,
3339 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3341 /* Activate rows. */
3342 writel(seq->rwcfg->activate_0_and_1,
3343 SDR_PHYGRP_RWMGRGRP_ADDRESS |
3344 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3349 * mem_init_latency() - Configure memory RLAT and WLAT settings
3351 * Configure memory RLAT and WLAT parameters.
3353 static void mem_init_latency(struct socfpga_sdrseq *seq)
3356 * For AV/CV, LFIFO is hardened and always runs at full rate
3357 * so max latency in AFI clocks, used here, is correspondingly
3360 const u32 max_latency = (1 << seq->misccfg->max_latency_count_width)
3364 debug("%s:%d\n", __func__, __LINE__);
3367 * Read in write latency.
3368 * WL for Hard PHY does not include additive latency.
3370 wlat = readl(&data_mgr->t_wl_add);
3371 wlat += readl(&data_mgr->mem_t_add);
3373 seq->gbl.rw_wl_nop_cycles = wlat - 1;
3375 /* Read in readl latency. */
3376 rlat = readl(&data_mgr->t_rl_add);
3378 /* Set a pretty high read latency initially. */
3379 seq->gbl.curr_read_lat = rlat + 16;
3380 if (seq->gbl.curr_read_lat > max_latency)
3381 seq->gbl.curr_read_lat = max_latency;
3383 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3385 /* Advertise write latency. */
3386 writel(wlat, &phy_mgr_cfg->afi_wlat);
3390 * @mem_skip_calibrate() - Set VFIFO and LFIFO to instant-on settings
3392 * Set VFIFO and LFIFO to instant-on settings in skip calibration mode.
3394 static void mem_skip_calibrate(struct socfpga_sdrseq *seq)
3399 debug("%s:%d\n", __func__, __LINE__);
3400 /* Need to update every shadow register set used by the interface */
3401 for (r = 0; r < seq->rwcfg->mem_number_of_ranks;
3402 r += NUM_RANKS_PER_SHADOW_REG) {
3404 * Set output phase alignment settings appropriate for
3407 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3408 scc_mgr_set_dqs_en_phase(i, 0);
3409 if (seq->iocfg->dll_chain_length == 6)
3410 scc_mgr_set_dqdqs_output_phase(i, 6);
3412 scc_mgr_set_dqdqs_output_phase(i, 7);
3416 * Write data arrives to the I/O two cycles before write
3417 * latency is reached (720 deg).
3418 * -> due to bit-slip in a/c bus
3419 * -> to allow board skew where dqs is longer than ck
3420 * -> how often can this happen!?
3421 * -> can claim back some ptaps for high freq
3422 * support if we can relax this, but i digress...
3424 * The write_clk leads mem_ck by 90 deg
3425 * The minimum ptap of the OPA is 180 deg
3426 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3427 * The write_clk is always delayed by 2 ptaps
3429 * Hence, to make DQS aligned to CK, we need to delay
3431 * (720 - 90 - 180 - 2) *
3432 * (360 / seq->iocfg->dll_chain_length)
3434 * Dividing the above by
3435 (360 / seq->iocfg->dll_chain_length)
3436 * gives us the number of ptaps, which simplies to:
3438 * (1.25 * seq->iocfg->dll_chain_length - 2)
3440 scc_mgr_set_dqdqs_output_phase(i,
3441 ((125 * seq->iocfg->dll_chain_length)
3444 writel(0xff, &sdr_scc_mgr->dqs_ena);
3445 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3447 for (i = 0; i < seq->rwcfg->mem_if_write_dqs_width; i++) {
3448 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3449 SCC_MGR_GROUP_COUNTER_OFFSET);
3451 writel(0xff, &sdr_scc_mgr->dq_ena);
3452 writel(0xff, &sdr_scc_mgr->dm_ena);
3453 writel(0, &sdr_scc_mgr->update);
3456 /* Compensate for simulation model behaviour */
3457 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3458 scc_mgr_set_dqs_bus_in_delay(i, 10);
3459 scc_mgr_load_dqs(i);
3461 writel(0, &sdr_scc_mgr->update);
3464 * ArriaV has hard FIFOs that can only be initialized by incrementing
3467 vfifo_offset = seq->misccfg->calib_vfifo_offset;
3468 for (j = 0; j < vfifo_offset; j++)
3469 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3470 writel(0, &phy_mgr_cmd->fifo_reset);
3473 * For Arria V and Cyclone V with hard LFIFO, we get the skip-cal
3474 * setting from generation-time constant.
3476 seq->gbl.curr_read_lat = seq->misccfg->calib_lfifo_offset;
3477 writel(seq->gbl.curr_read_lat, &phy_mgr_cfg->phy_rlat);
3481 * mem_calibrate() - Memory calibration entry point.
3483 * Perform memory calibration.
3485 static u32 mem_calibrate(struct socfpga_sdrseq *seq)
3489 u32 write_group, write_test_bgn;
3490 u32 read_group, read_test_bgn;
3491 u32 run_groups, current_run;
3492 u32 failing_groups = 0;
3493 u32 group_failed = 0;
3495 const u32 rwdqs_ratio = seq->rwcfg->mem_if_read_dqs_width /
3496 seq->rwcfg->mem_if_write_dqs_width;
3498 debug("%s:%d\n", __func__, __LINE__);
3500 /* Initialize the data settings */
3501 seq->gbl.error_substage = CAL_SUBSTAGE_NIL;
3502 seq->gbl.error_stage = CAL_STAGE_NIL;
3503 seq->gbl.error_group = 0xff;
3504 seq->gbl.fom_in = 0;
3505 seq->gbl.fom_out = 0;
3507 /* Initialize WLAT and RLAT. */
3508 mem_init_latency(seq);
3510 /* Initialize bit slips. */
3511 mem_precharge_and_activate(seq);
3513 for (i = 0; i < seq->rwcfg->mem_if_read_dqs_width; i++) {
3514 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3515 SCC_MGR_GROUP_COUNTER_OFFSET);
3516 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
3518 scc_mgr_set_hhp_extras();
3520 scc_set_bypass_mode(i);
3523 /* Calibration is skipped. */
3524 if ((seq->dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3526 * Set VFIFO and LFIFO to instant-on settings in skip
3529 mem_skip_calibrate(seq);
3532 * Do not remove this line as it makes sure all of our
3533 * decisions have been applied.
3535 writel(0, &sdr_scc_mgr->update);
3539 /* Calibration is not skipped. */
3540 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3542 * Zero all delay chain/phase settings for all
3543 * groups and all shadow register sets.
3545 scc_mgr_zero_all(seq);
3549 for (write_group = 0, write_test_bgn = 0; write_group
3550 < seq->rwcfg->mem_if_write_dqs_width; write_group++,
3551 write_test_bgn += seq->rwcfg->mem_dq_per_write_dqs) {
3552 /* Initialize the group failure */
3555 current_run = run_groups & ((1 <<
3556 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3557 run_groups = run_groups >>
3558 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3560 if (current_run == 0)
3563 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3564 SCC_MGR_GROUP_COUNTER_OFFSET);
3565 scc_mgr_zero_group(seq, write_group, 0);
3567 for (read_group = write_group * rwdqs_ratio,
3569 read_group < (write_group + 1) * rwdqs_ratio;
3571 read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
3572 if (STATIC_CALIB_STEPS & CALIB_SKIP_VFIFO)
3575 /* Calibrate the VFIFO */
3576 if (rw_mgr_mem_calibrate_vfifo(seq, read_group,
3580 if (!(seq->gbl.phy_debug_mode_flags &
3581 PHY_DEBUG_SWEEP_ALL_GROUPS))
3584 /* The group failed, we're done. */
3588 /* Calibrate the output side */
3589 for (rank_bgn = 0, sr = 0;
3590 rank_bgn < seq->rwcfg->mem_number_of_ranks;
3591 rank_bgn += NUM_RANKS_PER_SHADOW_REG, sr++) {
3592 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3595 /* Not needed in quick mode! */
3596 if (STATIC_CALIB_STEPS &
3597 CALIB_SKIP_DELAY_SWEEPS)
3600 /* Calibrate WRITEs */
3601 if (!rw_mgr_mem_calibrate_writes(seq, rank_bgn,
3607 if (!(seq->gbl.phy_debug_mode_flags &
3608 PHY_DEBUG_SWEEP_ALL_GROUPS))
3612 /* Some group failed, we're done. */
3616 for (read_group = write_group * rwdqs_ratio,
3618 read_group < (write_group + 1) * rwdqs_ratio;
3620 read_test_bgn += seq->rwcfg->mem_dq_per_read_dqs) {
3621 if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
3624 if (!rw_mgr_mem_calibrate_vfifo_end(seq,
3629 if (!(seq->gbl.phy_debug_mode_flags &
3630 PHY_DEBUG_SWEEP_ALL_GROUPS))
3633 /* The group failed, we're done. */
3637 /* No group failed, continue as usual. */
3640 grp_failed: /* A group failed, increment the counter. */
3645 * USER If there are any failing groups then report
3648 if (failing_groups != 0)
3651 if (STATIC_CALIB_STEPS & CALIB_SKIP_LFIFO)
3654 /* Calibrate the LFIFO */
3655 if (!rw_mgr_mem_calibrate_lfifo(seq))
3660 * Do not remove this line as it makes sure all of our decisions
3661 * have been applied.
3663 writel(0, &sdr_scc_mgr->update);
3668 * run_mem_calibrate() - Perform memory calibration
3670 * This function triggers the entire memory calibration procedure.
3672 static int run_mem_calibrate(struct socfpga_sdrseq *seq)
3677 debug("%s:%d\n", __func__, __LINE__);
3679 /* Reset pass/fail status shown on afi_cal_success/fail */
3680 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3682 /* Stop tracking manager. */
3683 ctrl_cfg = readl(&sdr_ctrl->ctrl_cfg);
3684 writel(ctrl_cfg & ~SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
3685 &sdr_ctrl->ctrl_cfg);
3687 phy_mgr_initialize(seq);
3688 rw_mgr_mem_initialize(seq);
3690 /* Perform the actual memory calibration. */
3691 pass = mem_calibrate(seq);
3693 mem_precharge_and_activate(seq);
3694 writel(0, &phy_mgr_cmd->fifo_reset);
3697 rw_mgr_mem_handoff(seq);
3699 * In Hard PHY this is a 2-bit control:
3701 * 1: DDIO Mux Select
3703 writel(0x2, &phy_mgr_cfg->mux_sel);
3705 /* Start tracking manager. */
3706 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
3712 * debug_mem_calibrate() - Report result of memory calibration
3713 * @pass: Value indicating whether calibration passed or failed
3715 * This function reports the results of the memory calibration
3716 * and writes debug information into the register file.
3718 static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
3723 debug("%s: CALIBRATION PASSED\n", __FILE__);
3725 seq->gbl.fom_in /= 2;
3726 seq->gbl.fom_out /= 2;
3728 if (seq->gbl.fom_in > 0xff)
3729 seq->gbl.fom_in = 0xff;
3731 if (seq->gbl.fom_out > 0xff)
3732 seq->gbl.fom_out = 0xff;
3734 /* Update the FOM in the register file */
3735 debug_info = seq->gbl.fom_in;
3736 debug_info |= seq->gbl.fom_out << 8;
3737 writel(debug_info, &sdr_reg_file->fom);
3739 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3740 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3742 debug("%s: CALIBRATION FAILED\n", __FILE__);
3744 debug_info = seq->gbl.error_stage;
3745 debug_info |= seq->gbl.error_substage << 8;
3746 debug_info |= seq->gbl.error_group << 16;
3748 writel(debug_info, &sdr_reg_file->failing_stage);
3749 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3750 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3752 /* Update the failing group/stage in the register file */
3753 debug_info = seq->gbl.error_stage;
3754 debug_info |= seq->gbl.error_substage << 8;
3755 debug_info |= seq->gbl.error_group << 16;
3756 writel(debug_info, &sdr_reg_file->failing_stage);
3759 debug("%s: Calibration complete\n", __FILE__);
3763 * hc_initialize_rom_data() - Initialize ROM data
3765 * Initialize ROM data.
3767 static void hc_initialize_rom_data(void)
3769 unsigned int nelem = 0;
3770 const u32 *rom_init;
3773 socfpga_get_seq_inst_init(&rom_init, &nelem);
3774 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3775 for (i = 0; i < nelem; i++)
3776 writel(rom_init[i], addr + (i << 2));
3778 socfpga_get_seq_ac_init(&rom_init, &nelem);
3779 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3780 for (i = 0; i < nelem; i++)
3781 writel(rom_init[i], addr + (i << 2));
3785 * initialize_reg_file() - Initialize SDR register file
3787 * Initialize SDR register file.
3789 static void initialize_reg_file(struct socfpga_sdrseq *seq)
3791 /* Initialize the register file with the correct data */
3792 writel(seq->misccfg->reg_file_init_seq_signature,
3793 &sdr_reg_file->signature);
3794 writel(0, &sdr_reg_file->debug_data_addr);
3795 writel(0, &sdr_reg_file->cur_stage);
3796 writel(0, &sdr_reg_file->fom);
3797 writel(0, &sdr_reg_file->failing_stage);
3798 writel(0, &sdr_reg_file->debug1);
3799 writel(0, &sdr_reg_file->debug2);
3803 * initialize_hps_phy() - Initialize HPS PHY
3805 * Initialize HPS PHY.
3807 static void initialize_hps_phy(void)
3811 * Tracking also gets configured here because it's in the
3814 u32 trk_sample_count = 7500;
3815 u32 trk_long_idle_sample_count = (10 << 16) | 100;
3817 * Format is number of outer loops in the 16 MSB, sample
3822 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3823 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3824 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3825 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3826 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3827 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3829 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3830 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3832 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3833 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3835 writel(reg, &sdr_ctrl->phy_ctrl0);
3838 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3840 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3841 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3842 trk_long_idle_sample_count);
3843 writel(reg, &sdr_ctrl->phy_ctrl1);
3846 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3847 trk_long_idle_sample_count >>
3848 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3849 writel(reg, &sdr_ctrl->phy_ctrl2);
3853 * initialize_tracking() - Initialize tracking
3855 * Initialize the register file with usable initial data.
3857 static void initialize_tracking(struct socfpga_sdrseq *seq)
3860 * Initialize the register file with the correct data.
3861 * Compute usable version of value in case we skip full
3862 * computation later.
3864 writel(DIV_ROUND_UP(seq->iocfg->delay_per_opa_tap,
3865 seq->iocfg->delay_per_dchain_tap) - 1,
3866 &sdr_reg_file->dtaps_per_ptap);
3868 /* trk_sample_count */
3869 writel(7500, &sdr_reg_file->trk_sample_count);
3871 /* longidle outer loop [15:0] */
3872 writel((10 << 16) | (100 << 0), &sdr_reg_file->trk_longidle);
3875 * longidle sample count [31:24]
3876 * trfc, worst case of 933Mhz 4Gb [23:16]
3877 * trcd, worst case [15:8]
3880 writel((243 << 24) | (14 << 16) | (10 << 8) | (4 << 0),
3881 &sdr_reg_file->delays);
3884 if (dram_is_ddr(2)) {
3885 writel(0, &sdr_reg_file->trk_rw_mgr_addr);
3886 } else if (dram_is_ddr(3)) {
3887 writel((seq->rwcfg->idle << 24) |
3888 (seq->rwcfg->activate_1 << 16) |
3889 (seq->rwcfg->sgle_read << 8) |
3890 (seq->rwcfg->precharge_all << 0),
3891 &sdr_reg_file->trk_rw_mgr_addr);
3894 writel(seq->rwcfg->mem_if_read_dqs_width,
3895 &sdr_reg_file->trk_read_dqs_width);
3898 if (dram_is_ddr(2)) {
3899 writel(1000 << 0, &sdr_reg_file->trk_rfsh);
3900 } else if (dram_is_ddr(3)) {
3901 writel((seq->rwcfg->refresh_all << 24) | (1000 << 0),
3902 &sdr_reg_file->trk_rfsh);
3906 int sdram_calibration_full(struct socfpga_sdr *sdr)
3909 struct socfpga_sdrseq seq;
3912 * For size reasons, this file uses hard coded addresses.
3913 * Check if we are called with the correct address.
3915 if (sdr != (struct socfpga_sdr *)SOCFPGA_SDR_ADDRESS)
3918 memset(&seq, 0, sizeof(seq));
3920 seq.rwcfg = socfpga_get_sdram_rwmgr_config();
3921 seq.iocfg = socfpga_get_sdram_io_config();
3922 seq.misccfg = socfpga_get_sdram_misc_config();
3924 /* Set the calibration enabled by default */
3925 seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3927 * Only sweep all groups (regardless of fail state) by default
3928 * Set enabled read test by default.
3930 #if DISABLE_GUARANTEED_READ
3931 seq.gbl.phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3933 /* Initialize the register file */
3934 initialize_reg_file(&seq);
3936 /* Initialize any PHY CSR */
3937 initialize_hps_phy();
3939 scc_mgr_initialize();
3941 initialize_tracking(&seq);
3943 debug("%s: Preparing to start memory calibration\n", __FILE__);
3945 debug("%s:%d\n", __func__, __LINE__);
3946 debug_cond(DLEVEL >= 1,
3947 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3948 seq.rwcfg->mem_number_of_ranks,
3949 seq.rwcfg->mem_number_of_cs_per_dimm,
3950 seq.rwcfg->mem_dq_per_read_dqs,
3951 seq.rwcfg->mem_dq_per_write_dqs,
3952 seq.rwcfg->mem_virtual_groups_per_read_dqs,
3953 seq.rwcfg->mem_virtual_groups_per_write_dqs);
3954 debug_cond(DLEVEL >= 1,
3955 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3956 seq.rwcfg->mem_if_read_dqs_width,
3957 seq.rwcfg->mem_if_write_dqs_width,
3958 seq.rwcfg->mem_data_width, seq.rwcfg->mem_data_mask_width,
3959 seq.iocfg->delay_per_opa_tap,
3960 seq.iocfg->delay_per_dchain_tap);
3961 debug_cond(DLEVEL >= 1, "dtap_dqsen_delay=%u, dll=%u",
3962 seq.iocfg->delay_per_dqs_en_dchain_tap,
3963 seq.iocfg->dll_chain_length);
3964 debug_cond(DLEVEL >= 1,
3965 "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3966 seq.iocfg->dqs_en_phase_max, seq.iocfg->dqdqs_out_phase_max,
3967 seq.iocfg->dqs_en_delay_max, seq.iocfg->dqs_in_delay_max);
3968 debug_cond(DLEVEL >= 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3969 seq.iocfg->io_in_delay_max, seq.iocfg->io_out1_delay_max,
3970 seq.iocfg->io_out2_delay_max);
3971 debug_cond(DLEVEL >= 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3972 seq.iocfg->dqs_in_reserve, seq.iocfg->dqs_out_reserve);
3974 hc_initialize_rom_data();
3976 /* update info for sims */
3977 reg_file_set_stage(CAL_STAGE_NIL);
3978 reg_file_set_group(0);
3981 * Load global needed for those actions that require
3982 * some dynamic calibration support.
3984 seq.dyn_calib_steps = STATIC_CALIB_STEPS;
3986 * Load global to allow dynamic selection of delay loop settings
3987 * based on calibration mode.
3989 if (!(seq.dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3990 seq.skip_delay_mask = 0xff;
3992 seq.skip_delay_mask = 0x0;
3994 pass = run_mem_calibrate(&seq);
3995 debug_mem_calibrate(&seq, pass);