2 * Copyright Altera Corporation (C) 2012-2015
4 * SPDX-License-Identifier: BSD-3-Clause
9 #include <asm/arch/sdram.h>
10 #include "sequencer.h"
11 #include "sequencer_auto.h"
12 #include "sequencer_auto_ac_init.h"
13 #include "sequencer_auto_inst_init.h"
14 #include "sequencer_defines.h"
16 static struct socfpga_sdr_rw_load_manager *sdr_rw_load_mgr_regs =
17 (struct socfpga_sdr_rw_load_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0x800);
19 static struct socfpga_sdr_rw_load_jump_manager *sdr_rw_load_jump_mgr_regs =
20 (struct socfpga_sdr_rw_load_jump_manager *)(SDR_PHYGRP_RWMGRGRP_ADDRESS | 0xC00);
22 static struct socfpga_sdr_reg_file *sdr_reg_file =
23 (struct socfpga_sdr_reg_file *)SDR_PHYGRP_REGFILEGRP_ADDRESS;
25 static struct socfpga_sdr_scc_mgr *sdr_scc_mgr =
26 (struct socfpga_sdr_scc_mgr *)(SDR_PHYGRP_SCCGRP_ADDRESS | 0xe00);
28 static struct socfpga_phy_mgr_cmd *phy_mgr_cmd =
29 (struct socfpga_phy_mgr_cmd *)SDR_PHYGRP_PHYMGRGRP_ADDRESS;
31 static struct socfpga_phy_mgr_cfg *phy_mgr_cfg =
32 (struct socfpga_phy_mgr_cfg *)(SDR_PHYGRP_PHYMGRGRP_ADDRESS | 0x40);
34 static struct socfpga_data_mgr *data_mgr =
35 (struct socfpga_data_mgr *)SDR_PHYGRP_DATAMGRGRP_ADDRESS;
37 static struct socfpga_sdr_ctrl *sdr_ctrl =
38 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
43 * In order to reduce ROM size, most of the selectable calibration steps are
44 * decided at compile time based on the user's calibration mode selection,
45 * as captured by the STATIC_CALIB_STEPS selection below.
47 * However, to support simulation-time selection of fast simulation mode, where
48 * we skip everything except the bare minimum, we need a few of the steps to
49 * be dynamic. In those cases, we either use the DYNAMIC_CALIB_STEPS for the
50 * check, which is based on the rtl-supplied value, or we dynamically compute
51 * the value to use based on the dynamically-chosen calibration mode
55 #define STATIC_IN_RTL_SIM 0
56 #define STATIC_SKIP_DELAY_LOOPS 0
58 #define STATIC_CALIB_STEPS (STATIC_IN_RTL_SIM | CALIB_SKIP_FULL_TEST | \
59 STATIC_SKIP_DELAY_LOOPS)
61 /* calibration steps requested by the rtl */
62 uint16_t dyn_calib_steps;
65 * To make CALIB_SKIP_DELAY_LOOPS a dynamic conditional option
66 * instead of static, we use boolean logic to select between
67 * non-skip and skip values
69 * The mask is set to include all bits when not-skipping, but is
73 uint16_t skip_delay_mask; /* mask off bits when skipping/not-skipping */
75 #define SKIP_DELAY_LOOP_VALUE_OR_ZERO(non_skip_value) \
76 ((non_skip_value) & skip_delay_mask)
79 struct param_type *param;
80 uint32_t curr_shadow_reg;
82 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
83 uint32_t write_group, uint32_t use_dm,
84 uint32_t all_correct, uint32_t *bit_chk, uint32_t all_ranks);
86 static void set_failing_group_stage(uint32_t group, uint32_t stage,
90 * Only set the global stage if there was not been any other
93 if (gbl->error_stage == CAL_STAGE_NIL) {
94 gbl->error_substage = substage;
95 gbl->error_stage = stage;
96 gbl->error_group = group;
100 static void reg_file_set_group(u16 set_group)
102 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff0000, set_group << 16);
105 static void reg_file_set_stage(u8 set_stage)
107 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xffff, set_stage & 0xff);
110 static void reg_file_set_sub_stage(u8 set_sub_stage)
112 set_sub_stage &= 0xff;
113 clrsetbits_le32(&sdr_reg_file->cur_stage, 0xff00, set_sub_stage << 8);
116 static void initialize(void)
118 debug("%s:%d\n", __func__, __LINE__);
119 /* USER calibration has control over path to memory */
121 * In Hard PHY this is a 2-bit control:
125 writel(0x3, &phy_mgr_cfg->mux_sel);
127 /* USER memory clock is not stable we begin initialization */
128 writel(0, &phy_mgr_cfg->reset_mem_stbl);
130 /* USER calibration status all set to zero */
131 writel(0, &phy_mgr_cfg->cal_status);
133 writel(0, &phy_mgr_cfg->cal_debug_info);
135 if ((dyn_calib_steps & CALIB_SKIP_ALL) != CALIB_SKIP_ALL) {
136 param->read_correct_mask_vg = ((uint32_t)1 <<
137 (RW_MGR_MEM_DQ_PER_READ_DQS /
138 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
139 param->write_correct_mask_vg = ((uint32_t)1 <<
140 (RW_MGR_MEM_DQ_PER_READ_DQS /
141 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS)) - 1;
142 param->read_correct_mask = ((uint32_t)1 <<
143 RW_MGR_MEM_DQ_PER_READ_DQS) - 1;
144 param->write_correct_mask = ((uint32_t)1 <<
145 RW_MGR_MEM_DQ_PER_WRITE_DQS) - 1;
146 param->dm_correct_mask = ((uint32_t)1 <<
147 (RW_MGR_MEM_DATA_WIDTH / RW_MGR_MEM_DATA_MASK_WIDTH))
152 static void set_rank_and_odt_mask(uint32_t rank, uint32_t odt_mode)
154 uint32_t odt_mask_0 = 0;
155 uint32_t odt_mask_1 = 0;
156 uint32_t cs_and_odt_mask;
158 if (odt_mode == RW_MGR_ODT_MODE_READ_WRITE) {
159 if (RW_MGR_MEM_NUMBER_OF_RANKS == 1) {
167 } else if (RW_MGR_MEM_NUMBER_OF_RANKS == 2) {
169 if (RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM == 1) {
170 /* - Dual-Slot , Single-Rank
171 * (1 chip-select per DIMM)
173 * - RDIMM, 4 total CS (2 CS per DIMM)
175 * Since MEM_NUMBER_OF_RANKS is 2 they are
177 * with 2 CS each (special for RDIMM)
178 * Read: Turn on ODT on the opposite rank
179 * Write: Turn on ODT on all ranks
181 odt_mask_0 = 0x3 & ~(1 << rank);
185 * USER - Single-Slot , Dual-rank DIMMs
186 * (2 chip-selects per DIMM)
187 * USER Read: Turn on ODT off on all ranks
188 * USER Write: Turn on ODT on active rank
191 odt_mask_1 = 0x3 & (1 << rank);
196 * ----------+-----------------------+
199 * Read From +-----------------------+
200 * Rank | 3 | 2 | 1 | 0 |
201 * ----------+-----+-----+-----+-----+
202 * 0 | 0 | 1 | 0 | 0 |
203 * 1 | 1 | 0 | 0 | 0 |
204 * 2 | 0 | 0 | 0 | 1 |
205 * 3 | 0 | 0 | 1 | 0 |
206 * ----------+-----+-----+-----+-----+
209 * ----------+-----------------------+
212 * Write To +-----------------------+
213 * Rank | 3 | 2 | 1 | 0 |
214 * ----------+-----+-----+-----+-----+
215 * 0 | 0 | 1 | 0 | 1 |
216 * 1 | 1 | 0 | 1 | 0 |
217 * 2 | 0 | 1 | 0 | 1 |
218 * 3 | 1 | 0 | 1 | 0 |
219 * ----------+-----+-----+-----+-----+
246 (0xFF & ~(1 << rank)) |
247 ((0xFF & odt_mask_0) << 8) |
248 ((0xFF & odt_mask_1) << 16);
249 writel(cs_and_odt_mask, SDR_PHYGRP_RWMGRGRP_ADDRESS |
250 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
254 * scc_mgr_set() - Set SCC Manager register
255 * @off: Base offset in SCC Manager space
256 * @grp: Read/Write group
257 * @val: Value to be set
259 * This function sets the SCC Manager (Scan Chain Control Manager) register.
261 static void scc_mgr_set(u32 off, u32 grp, u32 val)
263 writel(val, SDR_PHYGRP_SCCGRP_ADDRESS | off | (grp << 2));
267 * scc_mgr_initialize() - Initialize SCC Manager registers
269 * Initialize SCC Manager registers.
271 static void scc_mgr_initialize(void)
274 * Clear register file for HPS. 16 (2^4) is the size of the
275 * full register file in the scc mgr:
276 * RFILE_DEPTH = 1 + log2(MEM_DQ_PER_DQS + 1 + MEM_DM_PER_DQS +
277 * MEM_IF_READ_DQS_WIDTH - 1);
281 for (i = 0; i < 16; i++) {
282 debug_cond(DLEVEL == 1, "%s:%d: Clearing SCC RFILE index %u\n",
283 __func__, __LINE__, i);
284 scc_mgr_set(SCC_MGR_HHP_RFILE_OFFSET, 0, i);
288 static void scc_mgr_set_dqdqs_output_phase(uint32_t write_group, uint32_t phase)
290 scc_mgr_set(SCC_MGR_DQDQS_OUT_PHASE_OFFSET, write_group, phase);
293 static void scc_mgr_set_dqs_bus_in_delay(uint32_t read_group, uint32_t delay)
295 scc_mgr_set(SCC_MGR_DQS_IN_DELAY_OFFSET, read_group, delay);
298 static void scc_mgr_set_dqs_en_phase(uint32_t read_group, uint32_t phase)
300 scc_mgr_set(SCC_MGR_DQS_EN_PHASE_OFFSET, read_group, phase);
303 static void scc_mgr_set_dqs_en_delay(uint32_t read_group, uint32_t delay)
305 scc_mgr_set(SCC_MGR_DQS_EN_DELAY_OFFSET, read_group, delay);
308 static void scc_mgr_set_dqs_io_in_delay(uint32_t delay)
310 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
314 static void scc_mgr_set_dq_in_delay(uint32_t dq_in_group, uint32_t delay)
316 scc_mgr_set(SCC_MGR_IO_IN_DELAY_OFFSET, dq_in_group, delay);
319 static void scc_mgr_set_dq_out1_delay(uint32_t dq_in_group, uint32_t delay)
321 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, dq_in_group, delay);
324 static void scc_mgr_set_dqs_out1_delay(uint32_t delay)
326 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET, RW_MGR_MEM_DQ_PER_WRITE_DQS,
330 static void scc_mgr_set_dm_out1_delay(uint32_t dm, uint32_t delay)
332 scc_mgr_set(SCC_MGR_IO_OUT1_DELAY_OFFSET,
333 RW_MGR_MEM_DQ_PER_WRITE_DQS + 1 + dm,
337 /* load up dqs config settings */
338 static void scc_mgr_load_dqs(uint32_t dqs)
340 writel(dqs, &sdr_scc_mgr->dqs_ena);
343 /* load up dqs io config settings */
344 static void scc_mgr_load_dqs_io(void)
346 writel(0, &sdr_scc_mgr->dqs_io_ena);
349 /* load up dq config settings */
350 static void scc_mgr_load_dq(uint32_t dq_in_group)
352 writel(dq_in_group, &sdr_scc_mgr->dq_ena);
355 /* load up dm config settings */
356 static void scc_mgr_load_dm(uint32_t dm)
358 writel(dm, &sdr_scc_mgr->dm_ena);
362 * scc_mgr_set_all_ranks() - Set SCC Manager register for all ranks
363 * @off: Base offset in SCC Manager space
364 * @grp: Read/Write group
365 * @val: Value to be set
366 * @update: If non-zero, trigger SCC Manager update for all ranks
368 * This function sets the SCC Manager (Scan Chain Control Manager) register
369 * and optionally triggers the SCC update for all ranks.
371 static void scc_mgr_set_all_ranks(const u32 off, const u32 grp, const u32 val,
376 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
377 r += NUM_RANKS_PER_SHADOW_REG) {
378 scc_mgr_set(off, grp, val);
380 if (update || (r == 0)) {
381 writel(grp, &sdr_scc_mgr->dqs_ena);
382 writel(0, &sdr_scc_mgr->update);
387 static void scc_mgr_set_dqs_en_phase_all_ranks(u32 read_group, u32 phase)
390 * USER although the h/w doesn't support different phases per
391 * shadow register, for simplicity our scc manager modeling
392 * keeps different phase settings per shadow reg, and it's
393 * important for us to keep them in sync to match h/w.
394 * for efficiency, the scan chain update should occur only
397 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_PHASE_OFFSET,
398 read_group, phase, 0);
401 static void scc_mgr_set_dqdqs_output_phase_all_ranks(uint32_t write_group,
405 * USER although the h/w doesn't support different phases per
406 * shadow register, for simplicity our scc manager modeling
407 * keeps different phase settings per shadow reg, and it's
408 * important for us to keep them in sync to match h/w.
409 * for efficiency, the scan chain update should occur only
412 scc_mgr_set_all_ranks(SCC_MGR_DQDQS_OUT_PHASE_OFFSET,
413 write_group, phase, 0);
416 static void scc_mgr_set_dqs_en_delay_all_ranks(uint32_t read_group,
420 * In shadow register mode, the T11 settings are stored in
421 * registers in the core, which are updated by the DQS_ENA
422 * signals. Not issuing the SCC_MGR_UPD command allows us to
423 * save lots of rank switching overhead, by calling
424 * select_shadow_regs_for_update with update_scan_chains
427 scc_mgr_set_all_ranks(SCC_MGR_DQS_EN_DELAY_OFFSET,
428 read_group, delay, 1);
429 writel(0, &sdr_scc_mgr->update);
433 * scc_mgr_set_oct_out1_delay() - Set OCT output delay
434 * @write_group: Write group
435 * @delay: Delay value
437 * This function sets the OCT output delay in SCC manager.
439 static void scc_mgr_set_oct_out1_delay(const u32 write_group, const u32 delay)
441 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
442 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
443 const int base = write_group * ratio;
446 * Load the setting in the SCC manager
447 * Although OCT affects only write data, the OCT delay is controlled
448 * by the DQS logic block which is instantiated once per read group.
449 * For protocols where a write group consists of multiple read groups,
450 * the setting must be set multiple times.
452 for (i = 0; i < ratio; i++)
453 scc_mgr_set(SCC_MGR_OCT_OUT1_DELAY_OFFSET, base + i, delay);
456 static void scc_mgr_set_hhp_extras(void)
459 * Load the fixed setting in the SCC manager
460 * bits: 0:0 = 1'b1 - dqs bypass
461 * bits: 1:1 = 1'b1 - dq bypass
462 * bits: 4:2 = 3'b001 - rfifo_mode
463 * bits: 6:5 = 2'b01 - rfifo clock_select
464 * bits: 7:7 = 1'b0 - separate gating from ungating setting
465 * bits: 8:8 = 1'b0 - separate OE from Output delay setting
467 uint32_t value = (0<<8) | (0<<7) | (1<<5) | (1<<2) | (1<<1) | (1<<0);
468 uint32_t addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_HHP_GLOBALS_OFFSET;
470 writel(value, addr + SCC_MGR_HHP_EXTRAS_OFFSET);
474 * USER Zero all DQS config
475 * TODO: maybe rename to scc_mgr_zero_dqs_config (or something)
477 static void scc_mgr_zero_all(void)
482 * USER Zero all DQS config settings, across all groups and all
485 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
486 NUM_RANKS_PER_SHADOW_REG) {
487 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
489 * The phases actually don't exist on a per-rank basis,
490 * but there's no harm updating them several times, so
491 * let's keep the code simple.
493 scc_mgr_set_dqs_bus_in_delay(i, IO_DQS_IN_RESERVE);
494 scc_mgr_set_dqs_en_phase(i, 0);
495 scc_mgr_set_dqs_en_delay(i, 0);
498 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
499 scc_mgr_set_dqdqs_output_phase(i, 0);
500 /* av/cv don't have out2 */
501 scc_mgr_set_oct_out1_delay(i, IO_DQS_OUT_RESERVE);
505 /* multicast to all DQS group enables */
506 writel(0xff, &sdr_scc_mgr->dqs_ena);
507 writel(0, &sdr_scc_mgr->update);
511 * scc_set_bypass_mode() - Set bypass mode and trigger SCC update
512 * @write_group: Write group
514 * Set bypass mode and trigger SCC update.
516 static void scc_set_bypass_mode(const u32 write_group)
518 /* Only needed once to set all groups, pins, DQ, DQS, DM. */
519 if (write_group == 0) {
520 debug_cond(DLEVEL == 1, "%s:%d Setting HHP Extras\n", __func__,
522 scc_mgr_set_hhp_extras();
523 debug_cond(DLEVEL == 1, "%s:%d Done Setting HHP Extras\n",
527 /* Multicast to all DQ enables. */
528 writel(0xff, &sdr_scc_mgr->dq_ena);
529 writel(0xff, &sdr_scc_mgr->dm_ena);
531 /* Update current DQS IO enable. */
532 writel(0, &sdr_scc_mgr->dqs_io_ena);
534 /* Update the DQS logic. */
535 writel(write_group, &sdr_scc_mgr->dqs_ena);
538 writel(0, &sdr_scc_mgr->update);
542 * scc_mgr_load_dqs_for_write_group() - Load DQS settings for Write Group
543 * @write_group: Write group
545 * Load DQS settings for Write Group, do not trigger SCC update.
547 static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
549 const int ratio = RW_MGR_MEM_IF_READ_DQS_WIDTH /
550 RW_MGR_MEM_IF_WRITE_DQS_WIDTH;
551 const int base = write_group * ratio;
554 * Load the setting in the SCC manager
555 * Although OCT affects only write data, the OCT delay is controlled
556 * by the DQS logic block which is instantiated once per read group.
557 * For protocols where a write group consists of multiple read groups,
558 * the setting must be set multiple times.
560 for (i = 0; i < ratio; i++)
561 writel(base + i, &sdr_scc_mgr->dqs_ena);
564 static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
569 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
570 NUM_RANKS_PER_SHADOW_REG) {
571 /* Zero all DQ config settings */
572 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
573 scc_mgr_set_dq_out1_delay(i, 0);
575 scc_mgr_set_dq_in_delay(i, 0);
578 /* multicast to all DQ enables */
579 writel(0xff, &sdr_scc_mgr->dq_ena);
581 /* Zero all DM config settings */
582 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
583 scc_mgr_set_dm_out1_delay(i, 0);
586 /* multicast to all DM enables */
587 writel(0xff, &sdr_scc_mgr->dm_ena);
589 /* zero all DQS io settings */
591 scc_mgr_set_dqs_io_in_delay(0);
592 /* av/cv don't have out2 */
593 scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
594 scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
595 scc_mgr_load_dqs_for_write_group(write_group);
597 /* multicast to all DQS IO enables (only 1) */
598 writel(0, &sdr_scc_mgr->dqs_io_ena);
600 /* hit update to zero everything */
601 writel(0, &sdr_scc_mgr->update);
606 * apply and load a particular input delay for the DQ pins in a group
607 * group_bgn is the index of the first dq pin (in the write group)
609 static void scc_mgr_apply_group_dq_in_delay(uint32_t group_bgn, uint32_t delay)
613 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
614 scc_mgr_set_dq_in_delay(p, delay);
620 * scc_mgr_apply_group_dq_out1_delay() - Apply and load an output delay for the DQ pins in a group
621 * @delay: Delay value
623 * Apply and load a particular output delay for the DQ pins in a group.
625 static void scc_mgr_apply_group_dq_out1_delay(const u32 delay)
629 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
630 scc_mgr_set_dq_out1_delay(i, delay);
635 /* apply and load a particular output delay for the DM pins in a group */
636 static void scc_mgr_apply_group_dm_out1_delay(uint32_t delay1)
640 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
641 scc_mgr_set_dm_out1_delay(i, delay1);
647 /* apply and load delay on both DQS and OCT out1 */
648 static void scc_mgr_apply_group_dqs_io_and_oct_out1(uint32_t write_group,
651 scc_mgr_set_dqs_out1_delay(delay);
652 scc_mgr_load_dqs_io();
654 scc_mgr_set_oct_out1_delay(write_group, delay);
655 scc_mgr_load_dqs_for_write_group(write_group);
658 /* apply a delay to the entire output side: DQ, DM, DQS, OCT */
659 static void scc_mgr_apply_group_all_out_delay_add(uint32_t write_group,
663 uint32_t i, p, new_delay;
666 for (i = 0, p = group_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
667 new_delay = READ_SCC_DQ_OUT2_DELAY;
670 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
671 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQ[%u,%u]:\
672 %u > %lu => %lu", __func__, __LINE__,
673 write_group, group_bgn, delay, i, p, new_delay,
674 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
675 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
676 new_delay = IO_IO_OUT2_DELAY_MAX;
683 for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
684 new_delay = READ_SCC_DM_IO_OUT2_DELAY;
687 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
688 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DM[%u]:\
689 %u > %lu => %lu\n", __func__, __LINE__,
690 write_group, group_bgn, delay, i, new_delay,
691 (long unsigned int)IO_IO_OUT2_DELAY_MAX,
692 (long unsigned int)IO_IO_OUT2_DELAY_MAX);
693 new_delay = IO_IO_OUT2_DELAY_MAX;
700 new_delay = READ_SCC_DQS_IO_OUT2_DELAY;
703 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
704 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
705 " adding %u to OUT1\n", __func__, __LINE__,
706 write_group, group_bgn, delay, new_delay,
707 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
708 new_delay - IO_IO_OUT2_DELAY_MAX);
709 scc_mgr_set_dqs_out1_delay(new_delay -
710 IO_IO_OUT2_DELAY_MAX);
711 new_delay = IO_IO_OUT2_DELAY_MAX;
714 scc_mgr_load_dqs_io();
717 new_delay = READ_SCC_OCT_OUT2_DELAY;
720 if (new_delay > IO_IO_OUT2_DELAY_MAX) {
721 debug_cond(DLEVEL == 1, "%s:%d (%u, %u, %u) DQS: %u > %d => %d;"
722 " adding %u to OUT1\n", __func__, __LINE__,
723 write_group, group_bgn, delay, new_delay,
724 IO_IO_OUT2_DELAY_MAX, IO_IO_OUT2_DELAY_MAX,
725 new_delay - IO_IO_OUT2_DELAY_MAX);
726 scc_mgr_set_oct_out1_delay(write_group, new_delay -
727 IO_IO_OUT2_DELAY_MAX);
728 new_delay = IO_IO_OUT2_DELAY_MAX;
731 scc_mgr_load_dqs_for_write_group(write_group);
735 * USER apply a delay to the entire output side (DQ, DM, DQS, OCT)
738 static void scc_mgr_apply_group_all_out_delay_add_all_ranks(
739 uint32_t write_group, uint32_t group_bgn, uint32_t delay)
743 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
744 r += NUM_RANKS_PER_SHADOW_REG) {
745 scc_mgr_apply_group_all_out_delay_add(write_group,
747 writel(0, &sdr_scc_mgr->update);
751 /* optimization used to recover some slots in ddr3 inst_rom */
752 /* could be applied to other protocols if we wanted to */
753 static void set_jump_as_return(void)
756 * to save space, we replace return with jump to special shared
757 * RETURN instruction so we set the counter to large value so that
760 writel(0xff, &sdr_rw_load_mgr_regs->load_cntr0);
761 writel(RW_MGR_RETURN, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
765 * should always use constants as argument to ensure all computations are
766 * performed at compile time
768 static void delay_for_n_mem_clocks(const uint32_t clocks)
775 debug("%s:%d: clocks=%u ... start\n", __func__, __LINE__, clocks);
778 afi_clocks = (clocks + AFI_RATE_RATIO-1) / AFI_RATE_RATIO;
779 /* scale (rounding up) to get afi clocks */
782 * Note, we don't bother accounting for being off a little bit
783 * because of a few extra instructions in outer loops
784 * Note, the loops have a test at the end, and do the test before
785 * the decrement, and so always perform the loop
786 * 1 time more than the counter value
788 if (afi_clocks == 0) {
790 } else if (afi_clocks <= 0x100) {
791 inner = afi_clocks-1;
794 } else if (afi_clocks <= 0x10000) {
796 outer = (afi_clocks-1) >> 8;
801 c_loop = (afi_clocks-1) >> 16;
805 * rom instructions are structured as follows:
807 * IDLE_LOOP2: jnz cntr0, TARGET_A
808 * IDLE_LOOP1: jnz cntr1, TARGET_B
811 * so, when doing nested loops, TARGET_A is set to IDLE_LOOP2, and
812 * TARGET_B is set to IDLE_LOOP2 as well
814 * if we have no outer loop, though, then we can use IDLE_LOOP1 only,
815 * and set TARGET_B to IDLE_LOOP1 and we skip IDLE_LOOP2 entirely
817 * a little confusing, but it helps save precious space in the inst_rom
818 * and sequencer rom and keeps the delays more accurate and reduces
821 if (afi_clocks <= 0x100) {
822 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
823 &sdr_rw_load_mgr_regs->load_cntr1);
825 writel(RW_MGR_IDLE_LOOP1,
826 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
828 writel(RW_MGR_IDLE_LOOP1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
829 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
831 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(inner),
832 &sdr_rw_load_mgr_regs->load_cntr0);
834 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(outer),
835 &sdr_rw_load_mgr_regs->load_cntr1);
837 writel(RW_MGR_IDLE_LOOP2,
838 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
840 writel(RW_MGR_IDLE_LOOP2,
841 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
843 /* hack to get around compiler not being smart enough */
844 if (afi_clocks <= 0x10000) {
845 /* only need to run once */
846 writel(RW_MGR_IDLE_LOOP2, SDR_PHYGRP_RWMGRGRP_ADDRESS |
847 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
850 writel(RW_MGR_IDLE_LOOP2,
851 SDR_PHYGRP_RWMGRGRP_ADDRESS |
852 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
853 } while (c_loop-- != 0);
856 debug("%s:%d clocks=%u ... end\n", __func__, __LINE__, clocks);
859 static void rw_mgr_mem_initialize(void)
862 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
863 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
865 debug("%s:%d\n", __func__, __LINE__);
867 /* The reset / cke part of initialization is broadcasted to all ranks */
868 writel(RW_MGR_RANK_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
869 RW_MGR_SET_CS_AND_ODT_MASK_OFFSET);
872 * Here's how you load register for a loop
873 * Counters are located @ 0x800
874 * Jump address are located @ 0xC00
875 * For both, registers 0 to 3 are selected using bits 3 and 2, like
876 * in 0x800, 0x804, 0x808, 0x80C and 0xC00, 0xC04, 0xC08, 0xC0C
877 * I know this ain't pretty, but Avalon bus throws away the 2 least
881 /* start with memory RESET activated */
886 * 200us @ 266MHz (3.75 ns) ~ 54000 clock cycles
887 * If a and b are the number of iteration in 2 nested loops
888 * it takes the following number of cycles to complete the operation:
889 * number_of_cycles = ((2 + n) * a + 2) * b
890 * where n is the number of instruction in the inner loop
891 * One possible solution is n = 0 , a = 256 , b = 106 => a = FF,
896 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR0_VAL),
897 &sdr_rw_load_mgr_regs->load_cntr0);
898 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR1_VAL),
899 &sdr_rw_load_mgr_regs->load_cntr1);
900 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TINIT_CNTR2_VAL),
901 &sdr_rw_load_mgr_regs->load_cntr2);
903 /* Load jump address */
904 writel(RW_MGR_INIT_RESET_0_CKE_0,
905 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
906 writel(RW_MGR_INIT_RESET_0_CKE_0,
907 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
908 writel(RW_MGR_INIT_RESET_0_CKE_0,
909 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
911 /* Execute count instruction */
912 writel(RW_MGR_INIT_RESET_0_CKE_0, grpaddr);
914 /* indicate that memory is stable */
915 writel(1, &phy_mgr_cfg->reset_mem_stbl);
918 * transition the RESET to high
923 * 500us @ 266MHz (3.75 ns) ~ 134000 clock cycles
924 * If a and b are the number of iteration in 2 nested loops
925 * it takes the following number of cycles to complete the operation
926 * number_of_cycles = ((2 + n) * a + 2) * b
927 * where n is the number of instruction in the inner loop
928 * One possible solution is n = 2 , a = 131 , b = 256 => a = 83,
933 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR0_VAL),
934 &sdr_rw_load_mgr_regs->load_cntr0);
935 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR1_VAL),
936 &sdr_rw_load_mgr_regs->load_cntr1);
937 writel(SKIP_DELAY_LOOP_VALUE_OR_ZERO(SEQ_TRESET_CNTR2_VAL),
938 &sdr_rw_load_mgr_regs->load_cntr2);
940 /* Load jump address */
941 writel(RW_MGR_INIT_RESET_1_CKE_0,
942 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
943 writel(RW_MGR_INIT_RESET_1_CKE_0,
944 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
945 writel(RW_MGR_INIT_RESET_1_CKE_0,
946 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
948 writel(RW_MGR_INIT_RESET_1_CKE_0, grpaddr);
950 /* bring up clock enable */
952 /* tXRP < 250 ck cycles */
953 delay_for_n_mem_clocks(250);
955 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
956 if (param->skip_ranks[r]) {
957 /* request to skip the rank */
962 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
965 * USER Use Mirror-ed commands for odd ranks if address
968 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
969 set_jump_as_return();
970 writel(RW_MGR_MRS2_MIRR, grpaddr);
971 delay_for_n_mem_clocks(4);
972 set_jump_as_return();
973 writel(RW_MGR_MRS3_MIRR, grpaddr);
974 delay_for_n_mem_clocks(4);
975 set_jump_as_return();
976 writel(RW_MGR_MRS1_MIRR, grpaddr);
977 delay_for_n_mem_clocks(4);
978 set_jump_as_return();
979 writel(RW_MGR_MRS0_DLL_RESET_MIRR, grpaddr);
981 set_jump_as_return();
982 writel(RW_MGR_MRS2, grpaddr);
983 delay_for_n_mem_clocks(4);
984 set_jump_as_return();
985 writel(RW_MGR_MRS3, grpaddr);
986 delay_for_n_mem_clocks(4);
987 set_jump_as_return();
988 writel(RW_MGR_MRS1, grpaddr);
989 set_jump_as_return();
990 writel(RW_MGR_MRS0_DLL_RESET, grpaddr);
992 set_jump_as_return();
993 writel(RW_MGR_ZQCL, grpaddr);
995 /* tZQinit = tDLLK = 512 ck cycles */
996 delay_for_n_mem_clocks(512);
1001 * At the end of calibration we have to program the user settings in, and
1002 * USER hand off the memory to the user.
1004 static void rw_mgr_mem_handoff(void)
1007 uint32_t grpaddr = SDR_PHYGRP_RWMGRGRP_ADDRESS |
1008 RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1010 debug("%s:%d\n", __func__, __LINE__);
1011 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
1012 if (param->skip_ranks[r])
1013 /* request to skip the rank */
1016 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
1018 /* precharge all banks ... */
1019 writel(RW_MGR_PRECHARGE_ALL, grpaddr);
1021 /* load up MR settings specified by user */
1024 * Use Mirror-ed commands for odd ranks if address
1027 if ((RW_MGR_MEM_ADDRESS_MIRRORING >> r) & 0x1) {
1028 set_jump_as_return();
1029 writel(RW_MGR_MRS2_MIRR, grpaddr);
1030 delay_for_n_mem_clocks(4);
1031 set_jump_as_return();
1032 writel(RW_MGR_MRS3_MIRR, grpaddr);
1033 delay_for_n_mem_clocks(4);
1034 set_jump_as_return();
1035 writel(RW_MGR_MRS1_MIRR, grpaddr);
1036 delay_for_n_mem_clocks(4);
1037 set_jump_as_return();
1038 writel(RW_MGR_MRS0_USER_MIRR, grpaddr);
1040 set_jump_as_return();
1041 writel(RW_MGR_MRS2, grpaddr);
1042 delay_for_n_mem_clocks(4);
1043 set_jump_as_return();
1044 writel(RW_MGR_MRS3, grpaddr);
1045 delay_for_n_mem_clocks(4);
1046 set_jump_as_return();
1047 writel(RW_MGR_MRS1, grpaddr);
1048 delay_for_n_mem_clocks(4);
1049 set_jump_as_return();
1050 writel(RW_MGR_MRS0_USER, grpaddr);
1053 * USER need to wait tMOD (12CK or 15ns) time before issuing
1054 * other commands, but we will have plenty of NIOS cycles before
1055 * actual handoff so its okay.
1061 * performs a guaranteed read on the patterns we are going to use during a
1062 * read test to ensure memory works
1064 static uint32_t rw_mgr_mem_calibrate_read_test_patterns(uint32_t rank_bgn,
1065 uint32_t group, uint32_t num_tries, uint32_t *bit_chk,
1069 uint32_t correct_mask_vg;
1070 uint32_t tmp_bit_chk;
1071 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1072 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1074 uint32_t base_rw_mgr;
1076 *bit_chk = param->read_correct_mask;
1077 correct_mask_vg = param->read_correct_mask_vg;
1079 for (r = rank_bgn; r < rank_end; r++) {
1080 if (param->skip_ranks[r])
1081 /* request to skip the rank */
1085 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1087 /* Load up a constant bursts of read commands */
1088 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1089 writel(RW_MGR_GUARANTEED_READ,
1090 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1092 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1093 writel(RW_MGR_GUARANTEED_READ_CONT,
1094 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1097 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1098 /* reset the fifos to get pointers to known state */
1100 writel(0, &phy_mgr_cmd->fifo_reset);
1101 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1102 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1104 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1105 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1107 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1108 writel(RW_MGR_GUARANTEED_READ, addr +
1109 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1112 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1113 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & (~base_rw_mgr));
1118 *bit_chk &= tmp_bit_chk;
1121 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1122 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1124 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1125 debug_cond(DLEVEL == 1, "%s:%d test_load_patterns(%u,ALL) => (%u == %u) =>\
1126 %lu\n", __func__, __LINE__, group, *bit_chk, param->read_correct_mask,
1127 (long unsigned int)(*bit_chk == param->read_correct_mask));
1128 return *bit_chk == param->read_correct_mask;
1131 static uint32_t rw_mgr_mem_calibrate_read_test_patterns_all_ranks
1132 (uint32_t group, uint32_t num_tries, uint32_t *bit_chk)
1134 return rw_mgr_mem_calibrate_read_test_patterns(0, group,
1135 num_tries, bit_chk, 1);
1138 /* load up the patterns we are going to use during a read test */
1139 static void rw_mgr_mem_calibrate_read_load_patterns(uint32_t rank_bgn,
1143 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1144 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1146 debug("%s:%d\n", __func__, __LINE__);
1147 for (r = rank_bgn; r < rank_end; r++) {
1148 if (param->skip_ranks[r])
1149 /* request to skip the rank */
1153 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1155 /* Load up a constant bursts */
1156 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr0);
1158 writel(RW_MGR_GUARANTEED_WRITE_WAIT0,
1159 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1161 writel(0x20, &sdr_rw_load_mgr_regs->load_cntr1);
1163 writel(RW_MGR_GUARANTEED_WRITE_WAIT1,
1164 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1166 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr2);
1168 writel(RW_MGR_GUARANTEED_WRITE_WAIT2,
1169 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1171 writel(0x04, &sdr_rw_load_mgr_regs->load_cntr3);
1173 writel(RW_MGR_GUARANTEED_WRITE_WAIT3,
1174 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1176 writel(RW_MGR_GUARANTEED_WRITE, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1177 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
1180 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1184 * try a read and see if it returns correct data back. has dummy reads
1185 * inserted into the mix used to align dqs enable. has more thorough checks
1186 * than the regular read test.
1188 static uint32_t rw_mgr_mem_calibrate_read_test(uint32_t rank_bgn, uint32_t group,
1189 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1190 uint32_t all_groups, uint32_t all_ranks)
1193 uint32_t correct_mask_vg;
1194 uint32_t tmp_bit_chk;
1195 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
1196 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
1198 uint32_t base_rw_mgr;
1200 *bit_chk = param->read_correct_mask;
1201 correct_mask_vg = param->read_correct_mask_vg;
1203 uint32_t quick_read_mode = (((STATIC_CALIB_STEPS) &
1204 CALIB_SKIP_DELAY_SWEEPS) && ENABLE_SUPER_QUICK_CALIBRATION);
1206 for (r = rank_bgn; r < rank_end; r++) {
1207 if (param->skip_ranks[r])
1208 /* request to skip the rank */
1212 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
1214 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr1);
1216 writel(RW_MGR_READ_B2B_WAIT1,
1217 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
1219 writel(0x10, &sdr_rw_load_mgr_regs->load_cntr2);
1220 writel(RW_MGR_READ_B2B_WAIT2,
1221 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
1223 if (quick_read_mode)
1224 writel(0x1, &sdr_rw_load_mgr_regs->load_cntr0);
1225 /* need at least two (1+1) reads to capture failures */
1226 else if (all_groups)
1227 writel(0x06, &sdr_rw_load_mgr_regs->load_cntr0);
1229 writel(0x32, &sdr_rw_load_mgr_regs->load_cntr0);
1231 writel(RW_MGR_READ_B2B,
1232 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
1234 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH *
1235 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS - 1,
1236 &sdr_rw_load_mgr_regs->load_cntr3);
1238 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr3);
1240 writel(RW_MGR_READ_B2B,
1241 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
1244 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS-1; ; vg--) {
1245 /* reset the fifos to get pointers to known state */
1246 writel(0, &phy_mgr_cmd->fifo_reset);
1247 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
1248 RW_MGR_RESET_READ_DATAPATH_OFFSET);
1250 tmp_bit_chk = tmp_bit_chk << (RW_MGR_MEM_DQ_PER_READ_DQS
1251 / RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS);
1254 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_ALL_GROUPS_OFFSET;
1256 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1258 writel(RW_MGR_READ_B2B, addr +
1259 ((group * RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS +
1262 base_rw_mgr = readl(SDR_PHYGRP_RWMGRGRP_ADDRESS);
1263 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
1268 *bit_chk &= tmp_bit_chk;
1271 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
1272 writel(RW_MGR_CLEAR_DQS_ENABLE, addr + (group << 2));
1275 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1276 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ALL,%u) =>\
1277 (%u == %u) => %lu", __func__, __LINE__, group,
1278 all_groups, *bit_chk, param->read_correct_mask,
1279 (long unsigned int)(*bit_chk ==
1280 param->read_correct_mask));
1281 return *bit_chk == param->read_correct_mask;
1283 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
1284 debug_cond(DLEVEL == 2, "%s:%d read_test(%u,ONE,%u) =>\
1285 (%u != %lu) => %lu\n", __func__, __LINE__,
1286 group, all_groups, *bit_chk, (long unsigned int)0,
1287 (long unsigned int)(*bit_chk != 0x00));
1288 return *bit_chk != 0x00;
1292 static uint32_t rw_mgr_mem_calibrate_read_test_all_ranks(uint32_t group,
1293 uint32_t num_tries, uint32_t all_correct, uint32_t *bit_chk,
1294 uint32_t all_groups)
1296 return rw_mgr_mem_calibrate_read_test(0, group, num_tries, all_correct,
1297 bit_chk, all_groups, 1);
1300 static void rw_mgr_incr_vfifo(uint32_t grp, uint32_t *v)
1302 writel(grp, &phy_mgr_cmd->inc_vfifo_hard_phy);
1306 static void rw_mgr_decr_vfifo(uint32_t grp, uint32_t *v)
1310 for (i = 0; i < VFIFO_SIZE-1; i++)
1311 rw_mgr_incr_vfifo(grp, v);
1314 static int find_vfifo_read(uint32_t grp, uint32_t *bit_chk)
1317 uint32_t fail_cnt = 0;
1318 uint32_t test_status;
1320 for (v = 0; v < VFIFO_SIZE; ) {
1321 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo %u\n",
1322 __func__, __LINE__, v);
1323 test_status = rw_mgr_mem_calibrate_read_test_all_ranks
1324 (grp, 1, PASS_ONE_BIT, bit_chk, 0);
1332 /* fiddle with FIFO */
1333 rw_mgr_incr_vfifo(grp, &v);
1336 if (v >= VFIFO_SIZE) {
1337 /* no failing read found!! Something must have gone wrong */
1338 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: vfifo failed\n",
1339 __func__, __LINE__);
1346 static int find_working_phase(uint32_t *grp, uint32_t *bit_chk,
1347 uint32_t dtaps_per_ptap, uint32_t *work_bgn,
1348 uint32_t *v, uint32_t *d, uint32_t *p,
1349 uint32_t *i, uint32_t *max_working_cnt)
1351 uint32_t found_begin = 0;
1352 uint32_t tmp_delay = 0;
1353 uint32_t test_status;
1355 for (*d = 0; *d <= dtaps_per_ptap; (*d)++, tmp_delay +=
1356 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1357 *work_bgn = tmp_delay;
1358 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1360 for (*i = 0; *i < VFIFO_SIZE; (*i)++) {
1361 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_bgn +=
1362 IO_DELAY_PER_OPA_TAP) {
1363 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1366 rw_mgr_mem_calibrate_read_test_all_ranks
1367 (*grp, 1, PASS_ONE_BIT, bit_chk, 0);
1370 *max_working_cnt = 1;
1379 if (*p > IO_DQS_EN_PHASE_MAX)
1380 /* fiddle with FIFO */
1381 rw_mgr_incr_vfifo(*grp, v);
1388 if (*i >= VFIFO_SIZE) {
1389 /* cannot find working solution */
1390 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: no vfifo/\
1391 ptap/dtap\n", __func__, __LINE__);
1398 static void sdr_backup_phase(uint32_t *grp, uint32_t *bit_chk,
1399 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1400 uint32_t *p, uint32_t *max_working_cnt)
1402 uint32_t found_begin = 0;
1405 /* Special case code for backing up a phase */
1407 *p = IO_DQS_EN_PHASE_MAX;
1408 rw_mgr_decr_vfifo(*grp, v);
1412 tmp_delay = *work_bgn - IO_DELAY_PER_OPA_TAP;
1413 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1415 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_bgn;
1416 (*d)++, tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1417 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1419 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1423 *work_bgn = tmp_delay;
1428 /* We have found a working dtap before the ptap found above */
1429 if (found_begin == 1)
1430 (*max_working_cnt)++;
1433 * Restore VFIFO to old state before we decremented it
1437 if (*p > IO_DQS_EN_PHASE_MAX) {
1439 rw_mgr_incr_vfifo(*grp, v);
1442 scc_mgr_set_dqs_en_delay_all_ranks(*grp, 0);
1445 static int sdr_nonworking_phase(uint32_t *grp, uint32_t *bit_chk,
1446 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1447 uint32_t *p, uint32_t *i, uint32_t *max_working_cnt,
1450 uint32_t found_end = 0;
1453 *work_end += IO_DELAY_PER_OPA_TAP;
1454 if (*p > IO_DQS_EN_PHASE_MAX) {
1455 /* fiddle with FIFO */
1457 rw_mgr_incr_vfifo(*grp, v);
1460 for (; *i < VFIFO_SIZE + 1; (*i)++) {
1461 for (; *p <= IO_DQS_EN_PHASE_MAX; (*p)++, *work_end
1462 += IO_DELAY_PER_OPA_TAP) {
1463 scc_mgr_set_dqs_en_phase_all_ranks(*grp, *p);
1465 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1466 (*grp, 1, PASS_ONE_BIT, bit_chk, 0)) {
1470 (*max_working_cnt)++;
1477 if (*p > IO_DQS_EN_PHASE_MAX) {
1478 /* fiddle with FIFO */
1479 rw_mgr_incr_vfifo(*grp, v);
1484 if (*i >= VFIFO_SIZE + 1) {
1485 /* cannot see edge of failing read */
1486 debug_cond(DLEVEL == 2, "%s:%d sdr_nonworking_phase: end:\
1487 failed\n", __func__, __LINE__);
1494 static int sdr_find_window_centre(uint32_t *grp, uint32_t *bit_chk,
1495 uint32_t *work_bgn, uint32_t *v, uint32_t *d,
1496 uint32_t *p, uint32_t *work_mid,
1502 *work_mid = (*work_bgn + *work_end) / 2;
1504 debug_cond(DLEVEL == 2, "work_bgn=%d work_end=%d work_mid=%d\n",
1505 *work_bgn, *work_end, *work_mid);
1506 /* Get the middle delay to be less than a VFIFO delay */
1507 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX;
1508 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1510 debug_cond(DLEVEL == 2, "vfifo ptap delay %d\n", tmp_delay);
1511 while (*work_mid > tmp_delay)
1512 *work_mid -= tmp_delay;
1513 debug_cond(DLEVEL == 2, "new work_mid %d\n", *work_mid);
1516 for (*p = 0; *p <= IO_DQS_EN_PHASE_MAX && tmp_delay < *work_mid;
1517 (*p)++, tmp_delay += IO_DELAY_PER_OPA_TAP)
1519 tmp_delay -= IO_DELAY_PER_OPA_TAP;
1520 debug_cond(DLEVEL == 2, "new p %d, tmp_delay=%d\n", (*p) - 1, tmp_delay);
1521 for (*d = 0; *d <= IO_DQS_EN_DELAY_MAX && tmp_delay < *work_mid; (*d)++,
1522 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP)
1524 debug_cond(DLEVEL == 2, "new d %d, tmp_delay=%d\n", *d, tmp_delay);
1526 scc_mgr_set_dqs_en_phase_all_ranks(*grp, (*p) - 1);
1527 scc_mgr_set_dqs_en_delay_all_ranks(*grp, *d);
1530 * push vfifo until we can successfully calibrate. We can do this
1531 * because the largest possible margin in 1 VFIFO cycle.
1533 for (i = 0; i < VFIFO_SIZE; i++) {
1534 debug_cond(DLEVEL == 2, "find_dqs_en_phase: center: vfifo=%u\n",
1536 if (rw_mgr_mem_calibrate_read_test_all_ranks(*grp, 1,
1542 /* fiddle with FIFO */
1543 rw_mgr_incr_vfifo(*grp, v);
1546 if (i >= VFIFO_SIZE) {
1547 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center: \
1548 failed\n", __func__, __LINE__);
1555 /* find a good dqs enable to use */
1556 static uint32_t rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(uint32_t grp)
1558 uint32_t v, d, p, i;
1559 uint32_t max_working_cnt;
1561 uint32_t dtaps_per_ptap;
1562 uint32_t work_bgn, work_mid, work_end;
1563 uint32_t found_passing_read, found_failing_read, initial_failing_dtap;
1565 debug("%s:%d %u\n", __func__, __LINE__, grp);
1567 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
1569 scc_mgr_set_dqs_en_delay_all_ranks(grp, 0);
1570 scc_mgr_set_dqs_en_phase_all_ranks(grp, 0);
1572 /* ************************************************************** */
1573 /* * Step 0 : Determine number of delay taps for each phase tap * */
1574 dtaps_per_ptap = IO_DELAY_PER_OPA_TAP/IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1576 /* ********************************************************* */
1577 /* * Step 1 : First push vfifo until we get a failing read * */
1578 v = find_vfifo_read(grp, &bit_chk);
1580 max_working_cnt = 0;
1582 /* ******************************************************** */
1583 /* * step 2: find first working phase, increment in ptaps * */
1585 if (find_working_phase(&grp, &bit_chk, dtaps_per_ptap, &work_bgn, &v, &d,
1586 &p, &i, &max_working_cnt) == 0)
1589 work_end = work_bgn;
1592 * If d is 0 then the working window covers a phase tap and
1593 * we can follow the old procedure otherwise, we've found the beginning,
1594 * and we need to increment the dtaps until we find the end.
1597 /* ********************************************************* */
1598 /* * step 3a: if we have room, back off by one and
1599 increment in dtaps * */
1601 sdr_backup_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1604 /* ********************************************************* */
1605 /* * step 4a: go forward from working phase to non working
1606 phase, increment in ptaps * */
1607 if (sdr_nonworking_phase(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1608 &i, &max_working_cnt, &work_end) == 0)
1611 /* ********************************************************* */
1612 /* * step 5a: back off one from last, increment in dtaps * */
1614 /* Special case code for backing up a phase */
1616 p = IO_DQS_EN_PHASE_MAX;
1617 rw_mgr_decr_vfifo(grp, &v);
1622 work_end -= IO_DELAY_PER_OPA_TAP;
1623 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1625 /* * The actual increment of dtaps is done outside of
1626 the if/else loop to share code */
1629 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p: \
1630 vfifo=%u ptap=%u\n", __func__, __LINE__,
1633 /* ******************************************************* */
1634 /* * step 3-5b: Find the right edge of the window using
1636 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase:vfifo=%u \
1637 ptap=%u dtap=%u bgn=%u\n", __func__, __LINE__,
1640 work_end = work_bgn;
1642 /* * The actual increment of dtaps is done outside of the
1643 if/else loop to share code */
1645 /* Only here to counterbalance a subtract later on which is
1646 not needed if this branch of the algorithm is taken */
1650 /* The dtap increment to find the failing edge is done here */
1651 for (; d <= IO_DQS_EN_DELAY_MAX; d++, work_end +=
1652 IO_DELAY_PER_DQS_EN_DCHAIN_TAP) {
1653 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1654 end-2: dtap=%u\n", __func__, __LINE__, d);
1655 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1657 if (!rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1664 /* Go back to working dtap */
1666 work_end -= IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
1668 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: v/p/d: vfifo=%u \
1669 ptap=%u dtap=%u end=%u\n", __func__, __LINE__,
1670 v, p, d-1, work_end);
1672 if (work_end < work_bgn) {
1674 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: end-2: \
1675 failed\n", __func__, __LINE__);
1679 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: found range [%u,%u]\n",
1680 __func__, __LINE__, work_bgn, work_end);
1682 /* *************************************************************** */
1684 * * We need to calculate the number of dtaps that equal a ptap
1685 * * To do that we'll back up a ptap and re-find the edge of the
1686 * * window using dtaps
1689 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: calculate dtaps_per_ptap \
1690 for tracking\n", __func__, __LINE__);
1692 /* Special case code for backing up a phase */
1694 p = IO_DQS_EN_PHASE_MAX;
1695 rw_mgr_decr_vfifo(grp, &v);
1696 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1697 cycle/phase: v=%u p=%u\n", __func__, __LINE__,
1701 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: backedup \
1702 phase only: v=%u p=%u", __func__, __LINE__,
1706 scc_mgr_set_dqs_en_phase_all_ranks(grp, p);
1709 * Increase dtap until we first see a passing read (in case the
1710 * window is smaller than a ptap),
1711 * and then a failing read to mark the edge of the window again
1714 /* Find a passing read */
1715 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find passing read\n",
1716 __func__, __LINE__);
1717 found_passing_read = 0;
1718 found_failing_read = 0;
1719 initial_failing_dtap = d;
1720 for (; d <= IO_DQS_EN_DELAY_MAX; d++) {
1721 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: testing \
1722 read d=%u\n", __func__, __LINE__, d);
1723 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1725 if (rw_mgr_mem_calibrate_read_test_all_ranks(grp, 1,
1728 found_passing_read = 1;
1733 if (found_passing_read) {
1734 /* Find a failing read */
1735 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: find failing \
1736 read\n", __func__, __LINE__);
1737 for (d = d + 1; d <= IO_DQS_EN_DELAY_MAX; d++) {
1738 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: \
1739 testing read d=%u\n", __func__, __LINE__, d);
1740 scc_mgr_set_dqs_en_delay_all_ranks(grp, d);
1742 if (!rw_mgr_mem_calibrate_read_test_all_ranks
1743 (grp, 1, PASS_ONE_BIT, &bit_chk, 0)) {
1744 found_failing_read = 1;
1749 debug_cond(DLEVEL == 1, "%s:%d find_dqs_en_phase: failed to \
1750 calculate dtaps", __func__, __LINE__);
1751 debug_cond(DLEVEL == 1, "per ptap. Fall back on static value\n");
1755 * The dynamically calculated dtaps_per_ptap is only valid if we
1756 * found a passing/failing read. If we didn't, it means d hit the max
1757 * (IO_DQS_EN_DELAY_MAX). Otherwise, dtaps_per_ptap retains its
1758 * statically calculated value.
1760 if (found_passing_read && found_failing_read)
1761 dtaps_per_ptap = d - initial_failing_dtap;
1763 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
1764 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: dtaps_per_ptap=%u \
1765 - %u = %u", __func__, __LINE__, d,
1766 initial_failing_dtap, dtaps_per_ptap);
1768 /* ******************************************** */
1769 /* * step 6: Find the centre of the window * */
1770 if (sdr_find_window_centre(&grp, &bit_chk, &work_bgn, &v, &d, &p,
1771 &work_mid, &work_end) == 0)
1774 debug_cond(DLEVEL == 2, "%s:%d find_dqs_en_phase: center found: \
1775 vfifo=%u ptap=%u dtap=%u\n", __func__, __LINE__,
1781 * Try rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase across different
1782 * dq_in_delay values
1785 rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
1786 (uint32_t write_group, uint32_t read_group, uint32_t test_bgn)
1794 const uint32_t delay_step = IO_IO_IN_DELAY_MAX /
1795 (RW_MGR_MEM_DQ_PER_READ_DQS-1);
1796 /* we start at zero, so have one less dq to devide among */
1798 debug("%s:%d (%u,%u,%u)", __func__, __LINE__, write_group, read_group,
1801 /* try different dq_in_delays since the dq path is shorter than dqs */
1803 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1804 r += NUM_RANKS_PER_SHADOW_REG) {
1805 for (i = 0, p = test_bgn, d = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++, d += delay_step) {
1806 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_\
1807 vfifo_find_dqs_", __func__, __LINE__);
1808 debug_cond(DLEVEL == 1, "en_phase_sweep_dq_in_delay: g=%u/%u ",
1809 write_group, read_group);
1810 debug_cond(DLEVEL == 1, "r=%u, i=%u p=%u d=%u\n", r, i , p, d);
1811 scc_mgr_set_dq_in_delay(p, d);
1814 writel(0, &sdr_scc_mgr->update);
1817 found = rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase(read_group);
1819 debug_cond(DLEVEL == 1, "%s:%d rw_mgr_mem_calibrate_vfifo_find_dqs_\
1820 en_phase_sweep_dq", __func__, __LINE__);
1821 debug_cond(DLEVEL == 1, "_in_delay: g=%u/%u found=%u; Reseting delay \
1822 chain to zero\n", write_group, read_group, found);
1824 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
1825 r += NUM_RANKS_PER_SHADOW_REG) {
1826 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS;
1828 scc_mgr_set_dq_in_delay(p, 0);
1831 writel(0, &sdr_scc_mgr->update);
1837 /* per-bit deskew DQ and center */
1838 static uint32_t rw_mgr_mem_calibrate_vfifo_center(uint32_t rank_bgn,
1839 uint32_t write_group, uint32_t read_group, uint32_t test_bgn,
1840 uint32_t use_read_test, uint32_t update_fom)
1842 uint32_t i, p, d, min_index;
1844 * Store these as signed since there are comparisons with
1848 uint32_t sticky_bit_chk;
1849 int32_t left_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1850 int32_t right_edge[RW_MGR_MEM_DQ_PER_READ_DQS];
1851 int32_t final_dq[RW_MGR_MEM_DQ_PER_READ_DQS];
1853 int32_t orig_mid_min, mid_min;
1854 int32_t new_dqs, start_dqs, start_dqs_en, shift_dq, final_dqs,
1856 int32_t dq_margin, dqs_margin;
1858 uint32_t temp_dq_in_delay1, temp_dq_in_delay2;
1861 debug("%s:%d: %u %u", __func__, __LINE__, read_group, test_bgn);
1863 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_DQS_IN_DELAY_OFFSET;
1864 start_dqs = readl(addr + (read_group << 2));
1865 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
1866 start_dqs_en = readl(addr + ((read_group << 2)
1867 - IO_DQS_EN_DELAY_OFFSET));
1869 /* set the left and right edge of each bit to an illegal value */
1870 /* use (IO_IO_IN_DELAY_MAX + 1) as an illegal value */
1872 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1873 left_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1874 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1877 /* Search for the left edge of the window for each bit */
1878 for (d = 0; d <= IO_IO_IN_DELAY_MAX; d++) {
1879 scc_mgr_apply_group_dq_in_delay(write_group, test_bgn, d);
1881 writel(0, &sdr_scc_mgr->update);
1884 * Stop searching when the read test doesn't pass AND when
1885 * we've seen a passing read on every bit.
1887 if (use_read_test) {
1888 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1889 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1892 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1895 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1896 (read_group - (write_group *
1897 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1898 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1899 stop = (bit_chk == 0);
1901 sticky_bit_chk = sticky_bit_chk | bit_chk;
1902 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1903 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(left): dtap=%u => %u == %u \
1904 && %u", __func__, __LINE__, d,
1906 param->read_correct_mask, stop);
1911 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
1913 /* Remember a passing test as the
1917 /* If a left edge has not been seen yet,
1918 then a future passing test will mark
1919 this edge as the right edge */
1921 IO_IO_IN_DELAY_MAX + 1) {
1922 right_edge[i] = -(d + 1);
1925 bit_chk = bit_chk >> 1;
1930 /* Reset DQ delay chains to 0 */
1931 scc_mgr_apply_group_dq_in_delay(test_bgn, 0);
1933 for (i = RW_MGR_MEM_DQ_PER_READ_DQS - 1;; i--) {
1934 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
1935 %d right_edge[%u]: %d\n", __func__, __LINE__,
1936 i, left_edge[i], i, right_edge[i]);
1939 * Check for cases where we haven't found the left edge,
1940 * which makes our assignment of the the right edge invalid.
1941 * Reset it to the illegal value.
1943 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) && (
1944 right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1945 right_edge[i] = IO_IO_IN_DELAY_MAX + 1;
1946 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: reset \
1947 right_edge[%u]: %d\n", __func__, __LINE__,
1952 * Reset sticky bit (except for bits where we have seen
1953 * both the left and right edge).
1955 sticky_bit_chk = sticky_bit_chk << 1;
1956 if ((left_edge[i] != IO_IO_IN_DELAY_MAX + 1) &&
1957 (right_edge[i] != IO_IO_IN_DELAY_MAX + 1)) {
1958 sticky_bit_chk = sticky_bit_chk | 1;
1965 /* Search for the right edge of the window for each bit */
1966 for (d = 0; d <= IO_DQS_IN_DELAY_MAX - start_dqs; d++) {
1967 scc_mgr_set_dqs_bus_in_delay(read_group, d + start_dqs);
1968 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
1969 uint32_t delay = d + start_dqs_en;
1970 if (delay > IO_DQS_EN_DELAY_MAX)
1971 delay = IO_DQS_EN_DELAY_MAX;
1972 scc_mgr_set_dqs_en_delay(read_group, delay);
1974 scc_mgr_load_dqs(read_group);
1976 writel(0, &sdr_scc_mgr->update);
1979 * Stop searching when the read test doesn't pass AND when
1980 * we've seen a passing read on every bit.
1982 if (use_read_test) {
1983 stop = !rw_mgr_mem_calibrate_read_test(rank_bgn,
1984 read_group, NUM_READ_PB_TESTS, PASS_ONE_BIT,
1987 rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
1990 bit_chk = bit_chk >> (RW_MGR_MEM_DQ_PER_READ_DQS *
1991 (read_group - (write_group *
1992 RW_MGR_MEM_IF_READ_DQS_WIDTH /
1993 RW_MGR_MEM_IF_WRITE_DQS_WIDTH)));
1994 stop = (bit_chk == 0);
1996 sticky_bit_chk = sticky_bit_chk | bit_chk;
1997 stop = stop && (sticky_bit_chk == param->read_correct_mask);
1999 debug_cond(DLEVEL == 2, "%s:%d vfifo_center(right): dtap=%u => %u == \
2000 %u && %u", __func__, __LINE__, d,
2001 sticky_bit_chk, param->read_correct_mask, stop);
2006 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2008 /* Remember a passing test as
2013 /* If a right edge has not been
2014 seen yet, then a future passing
2015 test will mark this edge as the
2017 if (right_edge[i] ==
2018 IO_IO_IN_DELAY_MAX + 1) {
2019 left_edge[i] = -(d + 1);
2022 /* d = 0 failed, but it passed
2023 when testing the left edge,
2024 so it must be marginal,
2026 if (right_edge[i] ==
2027 IO_IO_IN_DELAY_MAX + 1 &&
2033 /* If a right edge has not been
2034 seen yet, then a future passing
2035 test will mark this edge as the
2037 else if (right_edge[i] ==
2038 IO_IO_IN_DELAY_MAX +
2040 left_edge[i] = -(d + 1);
2045 debug_cond(DLEVEL == 2, "%s:%d vfifo_center[r,\
2046 d=%u]: ", __func__, __LINE__, d);
2047 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d ",
2048 (int)(bit_chk & 1), i, left_edge[i]);
2049 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2051 bit_chk = bit_chk >> 1;
2056 /* Check that all bits have a window */
2057 for (i = 0; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2058 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: left_edge[%u]: \
2059 %d right_edge[%u]: %d", __func__, __LINE__,
2060 i, left_edge[i], i, right_edge[i]);
2061 if ((left_edge[i] == IO_IO_IN_DELAY_MAX + 1) || (right_edge[i]
2062 == IO_IO_IN_DELAY_MAX + 1)) {
2064 * Restore delay chain settings before letting the loop
2065 * in rw_mgr_mem_calibrate_vfifo to retry different
2066 * dqs/ck relationships.
2068 scc_mgr_set_dqs_bus_in_delay(read_group, start_dqs);
2069 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2070 scc_mgr_set_dqs_en_delay(read_group,
2073 scc_mgr_load_dqs(read_group);
2074 writel(0, &sdr_scc_mgr->update);
2076 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: failed to \
2077 find edge [%u]: %d %d", __func__, __LINE__,
2078 i, left_edge[i], right_edge[i]);
2079 if (use_read_test) {
2080 set_failing_group_stage(read_group *
2081 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2083 CAL_SUBSTAGE_VFIFO_CENTER);
2085 set_failing_group_stage(read_group *
2086 RW_MGR_MEM_DQ_PER_READ_DQS + i,
2087 CAL_STAGE_VFIFO_AFTER_WRITES,
2088 CAL_SUBSTAGE_VFIFO_CENTER);
2094 /* Find middle of window for each DQ bit */
2095 mid_min = left_edge[0] - right_edge[0];
2097 for (i = 1; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++) {
2098 mid = left_edge[i] - right_edge[i];
2099 if (mid < mid_min) {
2106 * -mid_min/2 represents the amount that we need to move DQS.
2107 * If mid_min is odd and positive we'll need to add one to
2108 * make sure the rounding in further calculations is correct
2109 * (always bias to the right), so just add 1 for all positive values.
2114 mid_min = mid_min / 2;
2116 debug_cond(DLEVEL == 1, "%s:%d vfifo_center: mid_min=%d (index=%u)\n",
2117 __func__, __LINE__, mid_min, min_index);
2119 /* Determine the amount we can change DQS (which is -mid_min) */
2120 orig_mid_min = mid_min;
2121 new_dqs = start_dqs - mid_min;
2122 if (new_dqs > IO_DQS_IN_DELAY_MAX)
2123 new_dqs = IO_DQS_IN_DELAY_MAX;
2124 else if (new_dqs < 0)
2127 mid_min = start_dqs - new_dqs;
2128 debug_cond(DLEVEL == 1, "vfifo_center: new mid_min=%d new_dqs=%d\n",
2131 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2132 if (start_dqs_en - mid_min > IO_DQS_EN_DELAY_MAX)
2133 mid_min += start_dqs_en - mid_min - IO_DQS_EN_DELAY_MAX;
2134 else if (start_dqs_en - mid_min < 0)
2135 mid_min += start_dqs_en - mid_min;
2137 new_dqs = start_dqs - mid_min;
2139 debug_cond(DLEVEL == 1, "vfifo_center: start_dqs=%d start_dqs_en=%d \
2140 new_dqs=%d mid_min=%d\n", start_dqs,
2141 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS ? start_dqs_en : -1,
2144 /* Initialize data for export structures */
2145 dqs_margin = IO_IO_IN_DELAY_MAX + 1;
2146 dq_margin = IO_IO_IN_DELAY_MAX + 1;
2148 /* add delay to bring centre of all DQ windows to the same "level" */
2149 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_READ_DQS; i++, p++) {
2150 /* Use values before divide by 2 to reduce round off error */
2151 shift_dq = (left_edge[i] - right_edge[i] -
2152 (left_edge[min_index] - right_edge[min_index]))/2 +
2153 (orig_mid_min - mid_min);
2155 debug_cond(DLEVEL == 2, "vfifo_center: before: \
2156 shift_dq[%u]=%d\n", i, shift_dq);
2158 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_IN_DELAY_OFFSET;
2159 temp_dq_in_delay1 = readl(addr + (p << 2));
2160 temp_dq_in_delay2 = readl(addr + (i << 2));
2162 if (shift_dq + (int32_t)temp_dq_in_delay1 >
2163 (int32_t)IO_IO_IN_DELAY_MAX) {
2164 shift_dq = (int32_t)IO_IO_IN_DELAY_MAX - temp_dq_in_delay2;
2165 } else if (shift_dq + (int32_t)temp_dq_in_delay1 < 0) {
2166 shift_dq = -(int32_t)temp_dq_in_delay1;
2168 debug_cond(DLEVEL == 2, "vfifo_center: after: \
2169 shift_dq[%u]=%d\n", i, shift_dq);
2170 final_dq[i] = temp_dq_in_delay1 + shift_dq;
2171 scc_mgr_set_dq_in_delay(p, final_dq[i]);
2174 debug_cond(DLEVEL == 2, "vfifo_center: margin[%u]=[%d,%d]\n", i,
2175 left_edge[i] - shift_dq + (-mid_min),
2176 right_edge[i] + shift_dq - (-mid_min));
2177 /* To determine values for export structures */
2178 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2179 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2181 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2182 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2185 final_dqs = new_dqs;
2186 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS)
2187 final_dqs_en = start_dqs_en - mid_min;
2190 if (IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS) {
2191 scc_mgr_set_dqs_en_delay(read_group, final_dqs_en);
2192 scc_mgr_load_dqs(read_group);
2196 scc_mgr_set_dqs_bus_in_delay(read_group, final_dqs);
2197 scc_mgr_load_dqs(read_group);
2198 debug_cond(DLEVEL == 2, "%s:%d vfifo_center: dq_margin=%d \
2199 dqs_margin=%d", __func__, __LINE__,
2200 dq_margin, dqs_margin);
2203 * Do not remove this line as it makes sure all of our decisions
2204 * have been applied. Apply the update bit.
2206 writel(0, &sdr_scc_mgr->update);
2208 return (dq_margin >= 0) && (dqs_margin >= 0);
2212 * calibrate the read valid prediction FIFO.
2214 * - read valid prediction will consist of finding a good DQS enable phase,
2215 * DQS enable delay, DQS input phase, and DQS input delay.
2216 * - we also do a per-bit deskew on the DQ lines.
2218 static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
2221 uint32_t p, d, rank_bgn, sr;
2222 uint32_t dtaps_per_ptap;
2225 uint32_t grp_calibrated;
2226 uint32_t write_group, write_test_bgn;
2227 uint32_t failed_substage;
2229 debug("%s:%d: %u %u\n", __func__, __LINE__, read_group, test_bgn);
2231 /* update info for sims */
2232 reg_file_set_stage(CAL_STAGE_VFIFO);
2234 write_group = read_group;
2235 write_test_bgn = test_bgn;
2237 /* USER Determine number of delay taps for each phase tap */
2240 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
2242 tmp_delay += IO_DELAY_PER_DQS_EN_DCHAIN_TAP;
2247 /* update info for sims */
2248 reg_file_set_group(read_group);
2252 reg_file_set_sub_stage(CAL_SUBSTAGE_GUARANTEED_READ);
2253 failed_substage = CAL_SUBSTAGE_GUARANTEED_READ;
2255 for (d = 0; d <= dtaps_per_ptap && grp_calibrated == 0; d += 2) {
2257 * In RLDRAMX we may be messing the delay of pins in
2258 * the same write group but outside of the current read
2259 * the group, but that's ok because we haven't
2260 * calibrated output side yet.
2263 scc_mgr_apply_group_all_out_delay_add_all_ranks
2264 (write_group, write_test_bgn, d);
2267 for (p = 0; p <= IO_DQDQS_OUT_PHASE_MAX && grp_calibrated == 0;
2269 /* set a particular dqdqs phase */
2270 scc_mgr_set_dqdqs_output_phase_all_ranks(read_group, p);
2272 debug_cond(DLEVEL == 1, "%s:%d calibrate_vfifo: g=%u \
2273 p=%u d=%u\n", __func__, __LINE__,
2277 * Load up the patterns used by read calibration
2278 * using current DQDQS phase.
2280 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2281 if (!(gbl->phy_debug_mode_flags &
2282 PHY_DEBUG_DISABLE_GUARANTEED_READ)) {
2283 if (!rw_mgr_mem_calibrate_read_test_patterns_all_ranks
2284 (read_group, 1, &bit_chk)) {
2285 debug_cond(DLEVEL == 1, "%s:%d Guaranteed read test failed:",
2286 __func__, __LINE__);
2287 debug_cond(DLEVEL == 1, " g=%u p=%u d=%u\n",
2295 if (rw_mgr_mem_calibrate_vfifo_find_dqs_en_phase_sweep_dq_in_delay
2296 (write_group, read_group, test_bgn)) {
2298 * USER Read per-bit deskew can be done on a
2299 * per shadow register basis.
2301 for (rank_bgn = 0, sr = 0;
2302 rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2303 rank_bgn += NUM_RANKS_PER_SHADOW_REG,
2306 * Determine if this set of ranks
2307 * should be skipped entirely.
2309 if (!param->skip_shadow_regs[sr]) {
2311 * If doing read after write
2312 * calibration, do not update
2313 * FOM, now - do it then.
2315 if (!rw_mgr_mem_calibrate_vfifo_center
2316 (rank_bgn, write_group,
2317 read_group, test_bgn, 1, 0)) {
2320 CAL_SUBSTAGE_VFIFO_CENTER;
2326 failed_substage = CAL_SUBSTAGE_DQS_EN_PHASE;
2331 if (grp_calibrated == 0) {
2332 set_failing_group_stage(write_group, CAL_STAGE_VFIFO,
2338 * Reset the delay chains back to zero if they have moved > 1
2339 * (check for > 1 because loop will increase d even when pass in
2343 scc_mgr_zero_group(write_group, write_test_bgn, 1);
2348 /* VFIFO Calibration -- Read Deskew Calibration after write deskew */
2349 static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
2352 uint32_t rank_bgn, sr;
2353 uint32_t grp_calibrated;
2354 uint32_t write_group;
2356 debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
2358 /* update info for sims */
2360 reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
2361 reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
2363 write_group = read_group;
2365 /* update info for sims */
2366 reg_file_set_group(read_group);
2369 /* Read per-bit deskew can be done on a per shadow register basis */
2370 for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
2371 rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
2372 /* Determine if this set of ranks should be skipped entirely */
2373 if (!param->skip_shadow_regs[sr]) {
2374 /* This is the last calibration round, update FOM here */
2375 if (!rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
2386 if (grp_calibrated == 0) {
2387 set_failing_group_stage(write_group,
2388 CAL_STAGE_VFIFO_AFTER_WRITES,
2389 CAL_SUBSTAGE_VFIFO_CENTER);
2396 /* Calibrate LFIFO to find smallest read latency */
2397 static uint32_t rw_mgr_mem_calibrate_lfifo(void)
2402 debug("%s:%d\n", __func__, __LINE__);
2404 /* update info for sims */
2405 reg_file_set_stage(CAL_STAGE_LFIFO);
2406 reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
2408 /* Load up the patterns used by read calibration for all ranks */
2409 rw_mgr_mem_calibrate_read_load_patterns(0, 1);
2413 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2414 debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
2415 __func__, __LINE__, gbl->curr_read_lat);
2417 if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
2425 /* reduce read latency and see if things are working */
2427 gbl->curr_read_lat--;
2428 } while (gbl->curr_read_lat > 0);
2430 /* reset the fifos to get pointers to known state */
2432 writel(0, &phy_mgr_cmd->fifo_reset);
2435 /* add a fudge factor to the read latency that was determined */
2436 gbl->curr_read_lat += 2;
2437 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
2438 debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
2439 read_lat=%u\n", __func__, __LINE__,
2440 gbl->curr_read_lat);
2443 set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
2444 CAL_SUBSTAGE_READ_LATENCY);
2446 debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
2447 read_lat=%u\n", __func__, __LINE__,
2448 gbl->curr_read_lat);
2454 * issue write test command.
2455 * two variants are provided. one that just tests a write pattern and
2456 * another that tests datamask functionality.
2458 static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
2461 uint32_t mcc_instruction;
2462 uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
2463 ENABLE_SUPER_QUICK_CALIBRATION);
2464 uint32_t rw_wl_nop_cycles;
2468 * Set counter and jump addresses for the right
2469 * number of NOP cycles.
2470 * The number of supported NOP cycles can range from -1 to infinity
2471 * Three different cases are handled:
2473 * 1. For a number of NOP cycles greater than 0, the RW Mgr looping
2474 * mechanism will be used to insert the right number of NOPs
2476 * 2. For a number of NOP cycles equals to 0, the micro-instruction
2477 * issuing the write command will jump straight to the
2478 * micro-instruction that turns on DQS (for DDRx), or outputs write
2479 * data (for RLD), skipping
2480 * the NOP micro-instruction all together
2482 * 3. A number of NOP cycles equal to -1 indicates that DQS must be
2483 * turned on in the same micro-instruction that issues the write
2484 * command. Then we need
2485 * to directly jump to the micro-instruction that sends out the data
2487 * NOTE: Implementing this mechanism uses 2 RW Mgr jump-counters
2488 * (2 and 3). One jump-counter (0) is used to perform multiple
2489 * write-read operations.
2490 * one counter left to issue this command in "multiple-group" mode
2493 rw_wl_nop_cycles = gbl->rw_wl_nop_cycles;
2495 if (rw_wl_nop_cycles == -1) {
2497 * CNTR 2 - We want to execute the special write operation that
2498 * turns on DQS right away and then skip directly to the
2499 * instruction that sends out the data. We set the counter to a
2500 * large number so that the jump is always taken.
2502 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2504 /* CNTR 3 - Not used */
2506 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1;
2507 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA,
2508 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2509 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2510 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2512 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0_WL_1;
2513 writel(RW_MGR_LFSR_WR_RD_BANK_0_DATA,
2514 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2515 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2516 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2518 } else if (rw_wl_nop_cycles == 0) {
2520 * CNTR 2 - We want to skip the NOP operation and go straight
2521 * to the DQS enable instruction. We set the counter to a large
2522 * number so that the jump is always taken.
2524 writel(0xFF, &sdr_rw_load_mgr_regs->load_cntr2);
2526 /* CNTR 3 - Not used */
2528 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2529 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS,
2530 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2532 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2533 writel(RW_MGR_LFSR_WR_RD_BANK_0_DQS,
2534 &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2538 * CNTR 2 - In this case we want to execute the next instruction
2539 * and NOT take the jump. So we set the counter to 0. The jump
2540 * address doesn't count.
2542 writel(0x0, &sdr_rw_load_mgr_regs->load_cntr2);
2543 writel(0x0, &sdr_rw_load_jump_mgr_regs->load_jump_add2);
2546 * CNTR 3 - Set the nop counter to the number of cycles we
2547 * need to loop for, minus 1.
2549 writel(rw_wl_nop_cycles - 1, &sdr_rw_load_mgr_regs->load_cntr3);
2551 mcc_instruction = RW_MGR_LFSR_WR_RD_DM_BANK_0;
2552 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP,
2553 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2555 mcc_instruction = RW_MGR_LFSR_WR_RD_BANK_0;
2556 writel(RW_MGR_LFSR_WR_RD_BANK_0_NOP,
2557 &sdr_rw_load_jump_mgr_regs->load_jump_add3);
2561 writel(0, SDR_PHYGRP_RWMGRGRP_ADDRESS |
2562 RW_MGR_RESET_READ_DATAPATH_OFFSET);
2564 if (quick_write_mode)
2565 writel(0x08, &sdr_rw_load_mgr_regs->load_cntr0);
2567 writel(0x40, &sdr_rw_load_mgr_regs->load_cntr0);
2569 writel(mcc_instruction, &sdr_rw_load_jump_mgr_regs->load_jump_add0);
2572 * CNTR 1 - This is used to ensure enough time elapses
2573 * for read data to come back.
2575 writel(0x30, &sdr_rw_load_mgr_regs->load_cntr1);
2578 writel(RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT,
2579 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2581 writel(RW_MGR_LFSR_WR_RD_BANK_0_WAIT,
2582 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
2585 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
2586 writel(mcc_instruction, addr + (group << 2));
2589 /* Test writes, can check for a single bit pass or multiple bit pass */
2590 static uint32_t rw_mgr_mem_calibrate_write_test(uint32_t rank_bgn,
2591 uint32_t write_group, uint32_t use_dm, uint32_t all_correct,
2592 uint32_t *bit_chk, uint32_t all_ranks)
2595 uint32_t correct_mask_vg;
2596 uint32_t tmp_bit_chk;
2598 uint32_t rank_end = all_ranks ? RW_MGR_MEM_NUMBER_OF_RANKS :
2599 (rank_bgn + NUM_RANKS_PER_SHADOW_REG);
2600 uint32_t addr_rw_mgr;
2601 uint32_t base_rw_mgr;
2603 *bit_chk = param->write_correct_mask;
2604 correct_mask_vg = param->write_correct_mask_vg;
2606 for (r = rank_bgn; r < rank_end; r++) {
2607 if (param->skip_ranks[r]) {
2608 /* request to skip the rank */
2613 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_READ_WRITE);
2616 addr_rw_mgr = SDR_PHYGRP_RWMGRGRP_ADDRESS;
2617 for (vg = RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS-1; ; vg--) {
2618 /* reset the fifos to get pointers to known state */
2619 writel(0, &phy_mgr_cmd->fifo_reset);
2621 tmp_bit_chk = tmp_bit_chk <<
2622 (RW_MGR_MEM_DQ_PER_WRITE_DQS /
2623 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
2624 rw_mgr_mem_calibrate_write_test_issue(write_group *
2625 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS+vg,
2628 base_rw_mgr = readl(addr_rw_mgr);
2629 tmp_bit_chk = tmp_bit_chk | (correct_mask_vg & ~(base_rw_mgr));
2633 *bit_chk &= tmp_bit_chk;
2637 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2638 debug_cond(DLEVEL == 2, "write_test(%u,%u,ALL) : %u == \
2639 %u => %lu", write_group, use_dm,
2640 *bit_chk, param->write_correct_mask,
2641 (long unsigned int)(*bit_chk ==
2642 param->write_correct_mask));
2643 return *bit_chk == param->write_correct_mask;
2645 set_rank_and_odt_mask(0, RW_MGR_ODT_MODE_OFF);
2646 debug_cond(DLEVEL == 2, "write_test(%u,%u,ONE) : %u != ",
2647 write_group, use_dm, *bit_chk);
2648 debug_cond(DLEVEL == 2, "%lu" " => %lu", (long unsigned int)0,
2649 (long unsigned int)(*bit_chk != 0));
2650 return *bit_chk != 0x00;
2655 * center all windows. do per-bit-deskew to possibly increase size of
2658 static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
2659 uint32_t write_group, uint32_t test_bgn)
2661 uint32_t i, p, min_index;
2664 * Store these as signed since there are comparisons with
2668 uint32_t sticky_bit_chk;
2669 int32_t left_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2670 int32_t right_edge[RW_MGR_MEM_DQ_PER_WRITE_DQS];
2672 int32_t mid_min, orig_mid_min;
2673 int32_t new_dqs, start_dqs, shift_dq;
2674 int32_t dq_margin, dqs_margin, dm_margin;
2676 uint32_t temp_dq_out1_delay;
2679 debug("%s:%d %u %u", __func__, __LINE__, write_group, test_bgn);
2683 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2684 start_dqs = readl(addr +
2685 (RW_MGR_MEM_DQ_PER_WRITE_DQS << 2));
2687 /* per-bit deskew */
2690 * set the left and right edge of each bit to an illegal value
2691 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value.
2694 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2695 left_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2696 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2699 /* Search for the left edge of the window for each bit */
2700 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX; d++) {
2701 scc_mgr_apply_group_dq_out1_delay(write_group, d);
2703 writel(0, &sdr_scc_mgr->update);
2706 * Stop searching when the read test doesn't pass AND when
2707 * we've seen a passing read on every bit.
2709 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2710 0, PASS_ONE_BIT, &bit_chk, 0);
2711 sticky_bit_chk = sticky_bit_chk | bit_chk;
2712 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2713 debug_cond(DLEVEL == 2, "write_center(left): dtap=%d => %u \
2714 == %u && %u [bit_chk= %u ]\n",
2715 d, sticky_bit_chk, param->write_correct_mask,
2721 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2724 * Remember a passing test as the
2730 * If a left edge has not been seen
2731 * yet, then a future passing test will
2732 * mark this edge as the right edge.
2735 IO_IO_OUT1_DELAY_MAX + 1) {
2736 right_edge[i] = -(d + 1);
2739 debug_cond(DLEVEL == 2, "write_center[l,d=%d):", d);
2740 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2741 (int)(bit_chk & 1), i, left_edge[i]);
2742 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2744 bit_chk = bit_chk >> 1;
2749 /* Reset DQ delay chains to 0 */
2750 scc_mgr_apply_group_dq_out1_delay(0);
2752 for (i = RW_MGR_MEM_DQ_PER_WRITE_DQS - 1;; i--) {
2753 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2754 %d right_edge[%u]: %d\n", __func__, __LINE__,
2755 i, left_edge[i], i, right_edge[i]);
2758 * Check for cases where we haven't found the left edge,
2759 * which makes our assignment of the the right edge invalid.
2760 * Reset it to the illegal value.
2762 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) &&
2763 (right_edge[i] != IO_IO_OUT1_DELAY_MAX + 1)) {
2764 right_edge[i] = IO_IO_OUT1_DELAY_MAX + 1;
2765 debug_cond(DLEVEL == 2, "%s:%d write_center: reset \
2766 right_edge[%u]: %d\n", __func__, __LINE__,
2771 * Reset sticky bit (except for bits where we have
2772 * seen the left edge).
2774 sticky_bit_chk = sticky_bit_chk << 1;
2775 if ((left_edge[i] != IO_IO_OUT1_DELAY_MAX + 1))
2776 sticky_bit_chk = sticky_bit_chk | 1;
2782 /* Search for the right edge of the window for each bit */
2783 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - start_dqs; d++) {
2784 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
2787 writel(0, &sdr_scc_mgr->update);
2790 * Stop searching when the read test doesn't pass AND when
2791 * we've seen a passing read on every bit.
2793 stop = !rw_mgr_mem_calibrate_write_test(rank_bgn, write_group,
2794 0, PASS_ONE_BIT, &bit_chk, 0);
2796 sticky_bit_chk = sticky_bit_chk | bit_chk;
2797 stop = stop && (sticky_bit_chk == param->write_correct_mask);
2799 debug_cond(DLEVEL == 2, "write_center (right): dtap=%u => %u == \
2800 %u && %u\n", d, sticky_bit_chk,
2801 param->write_correct_mask, stop);
2805 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS;
2807 /* d = 0 failed, but it passed when
2808 testing the left edge, so it must be
2809 marginal, set it to -1 */
2810 if (right_edge[i] ==
2811 IO_IO_OUT1_DELAY_MAX + 1 &&
2813 IO_IO_OUT1_DELAY_MAX + 1) {
2820 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2823 * Remember a passing test as
2830 * If a right edge has not
2831 * been seen yet, then a future
2832 * passing test will mark this
2833 * edge as the left edge.
2835 if (right_edge[i] ==
2836 IO_IO_OUT1_DELAY_MAX + 1)
2837 left_edge[i] = -(d + 1);
2840 * d = 0 failed, but it passed
2841 * when testing the left edge,
2842 * so it must be marginal, set
2845 if (right_edge[i] ==
2846 IO_IO_OUT1_DELAY_MAX + 1 &&
2848 IO_IO_OUT1_DELAY_MAX + 1)
2851 * If a right edge has not been
2852 * seen yet, then a future
2853 * passing test will mark this
2854 * edge as the left edge.
2856 else if (right_edge[i] ==
2857 IO_IO_OUT1_DELAY_MAX +
2859 left_edge[i] = -(d + 1);
2862 debug_cond(DLEVEL == 2, "write_center[r,d=%d):", d);
2863 debug_cond(DLEVEL == 2, "bit_chk_test=%d left_edge[%u]: %d",
2864 (int)(bit_chk & 1), i, left_edge[i]);
2865 debug_cond(DLEVEL == 2, "right_edge[%u]: %d\n", i,
2867 bit_chk = bit_chk >> 1;
2872 /* Check that all bits have a window */
2873 for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2874 debug_cond(DLEVEL == 2, "%s:%d write_center: left_edge[%u]: \
2875 %d right_edge[%u]: %d", __func__, __LINE__,
2876 i, left_edge[i], i, right_edge[i]);
2877 if ((left_edge[i] == IO_IO_OUT1_DELAY_MAX + 1) ||
2878 (right_edge[i] == IO_IO_OUT1_DELAY_MAX + 1)) {
2879 set_failing_group_stage(test_bgn + i,
2881 CAL_SUBSTAGE_WRITES_CENTER);
2886 /* Find middle of window for each DQ bit */
2887 mid_min = left_edge[0] - right_edge[0];
2889 for (i = 1; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
2890 mid = left_edge[i] - right_edge[i];
2891 if (mid < mid_min) {
2898 * -mid_min/2 represents the amount that we need to move DQS.
2899 * If mid_min is odd and positive we'll need to add one to
2900 * make sure the rounding in further calculations is correct
2901 * (always bias to the right), so just add 1 for all positive values.
2905 mid_min = mid_min / 2;
2906 debug_cond(DLEVEL == 1, "%s:%d write_center: mid_min=%d\n", __func__,
2909 /* Determine the amount we can change DQS (which is -mid_min) */
2910 orig_mid_min = mid_min;
2911 new_dqs = start_dqs;
2913 debug_cond(DLEVEL == 1, "%s:%d write_center: start_dqs=%d new_dqs=%d \
2914 mid_min=%d\n", __func__, __LINE__, start_dqs, new_dqs, mid_min);
2915 /* Initialize data for export structures */
2916 dqs_margin = IO_IO_OUT1_DELAY_MAX + 1;
2917 dq_margin = IO_IO_OUT1_DELAY_MAX + 1;
2919 /* add delay to bring centre of all DQ windows to the same "level" */
2920 for (i = 0, p = test_bgn; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++, p++) {
2921 /* Use values before divide by 2 to reduce round off error */
2922 shift_dq = (left_edge[i] - right_edge[i] -
2923 (left_edge[min_index] - right_edge[min_index]))/2 +
2924 (orig_mid_min - mid_min);
2926 debug_cond(DLEVEL == 2, "%s:%d write_center: before: shift_dq \
2927 [%u]=%d\n", __func__, __LINE__, i, shift_dq);
2929 addr = SDR_PHYGRP_SCCGRP_ADDRESS | SCC_MGR_IO_OUT1_DELAY_OFFSET;
2930 temp_dq_out1_delay = readl(addr + (i << 2));
2931 if (shift_dq + (int32_t)temp_dq_out1_delay >
2932 (int32_t)IO_IO_OUT1_DELAY_MAX) {
2933 shift_dq = (int32_t)IO_IO_OUT1_DELAY_MAX - temp_dq_out1_delay;
2934 } else if (shift_dq + (int32_t)temp_dq_out1_delay < 0) {
2935 shift_dq = -(int32_t)temp_dq_out1_delay;
2937 debug_cond(DLEVEL == 2, "write_center: after: shift_dq[%u]=%d\n",
2939 scc_mgr_set_dq_out1_delay(i, temp_dq_out1_delay + shift_dq);
2942 debug_cond(DLEVEL == 2, "write_center: margin[%u]=[%d,%d]\n", i,
2943 left_edge[i] - shift_dq + (-mid_min),
2944 right_edge[i] + shift_dq - (-mid_min));
2945 /* To determine values for export structures */
2946 if (left_edge[i] - shift_dq + (-mid_min) < dq_margin)
2947 dq_margin = left_edge[i] - shift_dq + (-mid_min);
2949 if (right_edge[i] + shift_dq - (-mid_min) < dqs_margin)
2950 dqs_margin = right_edge[i] + shift_dq - (-mid_min);
2954 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
2955 writel(0, &sdr_scc_mgr->update);
2958 debug_cond(DLEVEL == 2, "%s:%d write_center: DM\n", __func__, __LINE__);
2961 * set the left and right edge of each bit to an illegal value,
2962 * use (IO_IO_OUT1_DELAY_MAX + 1) as an illegal value,
2964 left_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2965 right_edge[0] = IO_IO_OUT1_DELAY_MAX + 1;
2966 int32_t bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
2967 int32_t end_curr = IO_IO_OUT1_DELAY_MAX + 1;
2968 int32_t bgn_best = IO_IO_OUT1_DELAY_MAX + 1;
2969 int32_t end_best = IO_IO_OUT1_DELAY_MAX + 1;
2970 int32_t win_best = 0;
2972 /* Search for the/part of the window with DM shift */
2973 for (d = IO_IO_OUT1_DELAY_MAX; d >= 0; d -= DELTA_D) {
2974 scc_mgr_apply_group_dm_out1_delay(d);
2975 writel(0, &sdr_scc_mgr->update);
2977 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
2978 PASS_ALL_BITS, &bit_chk,
2980 /* USE Set current end of the window */
2983 * If a starting edge of our window has not been seen
2984 * this is our current start of the DM window.
2986 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
2990 * If current window is bigger than best seen.
2991 * Set best seen to be current window.
2993 if ((end_curr-bgn_curr+1) > win_best) {
2994 win_best = end_curr-bgn_curr+1;
2995 bgn_best = bgn_curr;
2996 end_best = end_curr;
2999 /* We just saw a failing test. Reset temp edge */
3000 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3001 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3006 /* Reset DM delay chains to 0 */
3007 scc_mgr_apply_group_dm_out1_delay(0);
3010 * Check to see if the current window nudges up aganist 0 delay.
3011 * If so we need to continue the search by shifting DQS otherwise DQS
3012 * search begins as a new search. */
3013 if (end_curr != 0) {
3014 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3015 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3018 /* Search for the/part of the window with DQS shifts */
3019 for (d = 0; d <= IO_IO_OUT1_DELAY_MAX - new_dqs; d += DELTA_D) {
3021 * Note: This only shifts DQS, so are we limiting ourselve to
3022 * width of DQ unnecessarily.
3024 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group,
3027 writel(0, &sdr_scc_mgr->update);
3028 if (rw_mgr_mem_calibrate_write_test(rank_bgn, write_group, 1,
3029 PASS_ALL_BITS, &bit_chk,
3031 /* USE Set current end of the window */
3034 * If a beginning edge of our window has not been seen
3035 * this is our current begin of the DM window.
3037 if (bgn_curr == IO_IO_OUT1_DELAY_MAX + 1)
3041 * If current window is bigger than best seen. Set best
3042 * seen to be current window.
3044 if ((end_curr-bgn_curr+1) > win_best) {
3045 win_best = end_curr-bgn_curr+1;
3046 bgn_best = bgn_curr;
3047 end_best = end_curr;
3050 /* We just saw a failing test. Reset temp edge */
3051 bgn_curr = IO_IO_OUT1_DELAY_MAX + 1;
3052 end_curr = IO_IO_OUT1_DELAY_MAX + 1;
3054 /* Early exit optimization: if ther remaining delay
3055 chain space is less than already seen largest window
3058 (IO_IO_OUT1_DELAY_MAX - new_dqs - d)) {
3064 /* assign left and right edge for cal and reporting; */
3065 left_edge[0] = -1*bgn_best;
3066 right_edge[0] = end_best;
3068 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d\n", __func__,
3069 __LINE__, left_edge[0], right_edge[0]);
3071 /* Move DQS (back to orig) */
3072 scc_mgr_apply_group_dqs_io_and_oct_out1(write_group, new_dqs);
3076 /* Find middle of window for the DM bit */
3077 mid = (left_edge[0] - right_edge[0]) / 2;
3079 /* only move right, since we are not moving DQS/DQ */
3083 /* dm_marign should fail if we never find a window */
3087 dm_margin = left_edge[0] - mid;
3089 scc_mgr_apply_group_dm_out1_delay(mid);
3090 writel(0, &sdr_scc_mgr->update);
3092 debug_cond(DLEVEL == 2, "%s:%d dm_calib: left=%d right=%d mid=%d \
3093 dm_margin=%d\n", __func__, __LINE__, left_edge[0],
3094 right_edge[0], mid, dm_margin);
3096 gbl->fom_out += dq_margin + dqs_margin;
3098 debug_cond(DLEVEL == 2, "%s:%d write_center: dq_margin=%d \
3099 dqs_margin=%d dm_margin=%d\n", __func__, __LINE__,
3100 dq_margin, dqs_margin, dm_margin);
3103 * Do not remove this line as it makes sure all of our
3104 * decisions have been applied.
3106 writel(0, &sdr_scc_mgr->update);
3107 return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
3110 /* calibrate the write operations */
3111 static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
3114 /* update info for sims */
3115 debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
3117 reg_file_set_stage(CAL_STAGE_WRITES);
3118 reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
3120 reg_file_set_group(g);
3122 if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
3123 set_failing_group_stage(g, CAL_STAGE_WRITES,
3124 CAL_SUBSTAGE_WRITES_CENTER);
3131 /* precharge all banks and activate row 0 in bank "000..." and bank "111..." */
3132 static void mem_precharge_and_activate(void)
3136 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r++) {
3137 if (param->skip_ranks[r]) {
3138 /* request to skip the rank */
3143 set_rank_and_odt_mask(r, RW_MGR_ODT_MODE_OFF);
3145 /* precharge all banks ... */
3146 writel(RW_MGR_PRECHARGE_ALL, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3147 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3149 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr0);
3150 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT1,
3151 &sdr_rw_load_jump_mgr_regs->load_jump_add0);
3153 writel(0x0F, &sdr_rw_load_mgr_regs->load_cntr1);
3154 writel(RW_MGR_ACTIVATE_0_AND_1_WAIT2,
3155 &sdr_rw_load_jump_mgr_regs->load_jump_add1);
3158 writel(RW_MGR_ACTIVATE_0_AND_1, SDR_PHYGRP_RWMGRGRP_ADDRESS |
3159 RW_MGR_RUN_SINGLE_GROUP_OFFSET);
3163 /* Configure various memory related parameters. */
3164 static void mem_config(void)
3166 uint32_t rlat, wlat;
3167 uint32_t rw_wl_nop_cycles;
3168 uint32_t max_latency;
3170 debug("%s:%d\n", __func__, __LINE__);
3171 /* read in write and read latency */
3172 wlat = readl(&data_mgr->t_wl_add);
3173 wlat += readl(&data_mgr->mem_t_add);
3175 /* WL for hard phy does not include additive latency */
3178 * add addtional write latency to offset the address/command extra
3179 * clock cycle. We change the AC mux setting causing AC to be delayed
3180 * by one mem clock cycle. Only do this for DDR3
3184 rlat = readl(&data_mgr->t_rl_add);
3186 rw_wl_nop_cycles = wlat - 2;
3187 gbl->rw_wl_nop_cycles = rw_wl_nop_cycles;
3190 * For AV/CV, lfifo is hardened and always runs at full rate so
3191 * max latency in AFI clocks, used here, is correspondingly smaller.
3193 max_latency = (1<<MAX_LATENCY_COUNT_WIDTH)/1 - 1;
3194 /* configure for a burst length of 8 */
3197 /* Adjust Write Latency for Hard PHY */
3200 /* set a pretty high read latency initially */
3201 gbl->curr_read_lat = rlat + 16;
3203 if (gbl->curr_read_lat > max_latency)
3204 gbl->curr_read_lat = max_latency;
3206 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3208 /* advertise write latency */
3209 gbl->curr_write_lat = wlat;
3210 writel(wlat - 2, &phy_mgr_cfg->afi_wlat);
3212 /* initialize bit slips */
3213 mem_precharge_and_activate();
3216 /* Set VFIFO and LFIFO to instant-on settings in skip calibration mode */
3217 static void mem_skip_calibrate(void)
3219 uint32_t vfifo_offset;
3222 debug("%s:%d\n", __func__, __LINE__);
3223 /* Need to update every shadow register set used by the interface */
3224 for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
3225 r += NUM_RANKS_PER_SHADOW_REG) {
3227 * Set output phase alignment settings appropriate for
3230 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3231 scc_mgr_set_dqs_en_phase(i, 0);
3232 #if IO_DLL_CHAIN_LENGTH == 6
3233 scc_mgr_set_dqdqs_output_phase(i, 6);
3235 scc_mgr_set_dqdqs_output_phase(i, 7);
3240 * Write data arrives to the I/O two cycles before write
3241 * latency is reached (720 deg).
3242 * -> due to bit-slip in a/c bus
3243 * -> to allow board skew where dqs is longer than ck
3244 * -> how often can this happen!?
3245 * -> can claim back some ptaps for high freq
3246 * support if we can relax this, but i digress...
3248 * The write_clk leads mem_ck by 90 deg
3249 * The minimum ptap of the OPA is 180 deg
3250 * Each ptap has (360 / IO_DLL_CHAIN_LENGH) deg of delay
3251 * The write_clk is always delayed by 2 ptaps
3253 * Hence, to make DQS aligned to CK, we need to delay
3255 * (720 - 90 - 180 - 2 * (360 / IO_DLL_CHAIN_LENGTH))
3257 * Dividing the above by (360 / IO_DLL_CHAIN_LENGTH)
3258 * gives us the number of ptaps, which simplies to:
3260 * (1.25 * IO_DLL_CHAIN_LENGTH - 2)
3262 scc_mgr_set_dqdqs_output_phase(i, (1.25 *
3263 IO_DLL_CHAIN_LENGTH - 2));
3265 writel(0xff, &sdr_scc_mgr->dqs_ena);
3266 writel(0xff, &sdr_scc_mgr->dqs_io_ena);
3268 for (i = 0; i < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; i++) {
3269 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3270 SCC_MGR_GROUP_COUNTER_OFFSET);
3272 writel(0xff, &sdr_scc_mgr->dq_ena);
3273 writel(0xff, &sdr_scc_mgr->dm_ena);
3274 writel(0, &sdr_scc_mgr->update);
3277 /* Compensate for simulation model behaviour */
3278 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3279 scc_mgr_set_dqs_bus_in_delay(i, 10);
3280 scc_mgr_load_dqs(i);
3282 writel(0, &sdr_scc_mgr->update);
3285 * ArriaV has hard FIFOs that can only be initialized by incrementing
3288 vfifo_offset = CALIB_VFIFO_OFFSET;
3289 for (j = 0; j < vfifo_offset; j++) {
3290 writel(0xff, &phy_mgr_cmd->inc_vfifo_hard_phy);
3292 writel(0, &phy_mgr_cmd->fifo_reset);
3295 * For ACV with hard lfifo, we get the skip-cal setting from
3296 * generation-time constant.
3298 gbl->curr_read_lat = CALIB_LFIFO_OFFSET;
3299 writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
3302 /* Memory calibration entry point */
3303 static uint32_t mem_calibrate(void)
3306 uint32_t rank_bgn, sr;
3307 uint32_t write_group, write_test_bgn;
3308 uint32_t read_group, read_test_bgn;
3309 uint32_t run_groups, current_run;
3310 uint32_t failing_groups = 0;
3311 uint32_t group_failed = 0;
3312 uint32_t sr_failed = 0;
3314 debug("%s:%d\n", __func__, __LINE__);
3315 /* Initialize the data settings */
3317 gbl->error_substage = CAL_SUBSTAGE_NIL;
3318 gbl->error_stage = CAL_STAGE_NIL;
3319 gbl->error_group = 0xff;
3325 for (i = 0; i < RW_MGR_MEM_IF_READ_DQS_WIDTH; i++) {
3326 writel(i, SDR_PHYGRP_SCCGRP_ADDRESS |
3327 SCC_MGR_GROUP_COUNTER_OFFSET);
3328 scc_set_bypass_mode(i);
3331 if ((dyn_calib_steps & CALIB_SKIP_ALL) == CALIB_SKIP_ALL) {
3333 * Set VFIFO and LFIFO to instant-on settings in skip
3336 mem_skip_calibrate();
3338 for (i = 0; i < NUM_CALIB_REPEAT; i++) {
3340 * Zero all delay chain/phase settings for all
3341 * groups and all shadow register sets.
3345 run_groups = ~param->skip_groups;
3347 for (write_group = 0, write_test_bgn = 0; write_group
3348 < RW_MGR_MEM_IF_WRITE_DQS_WIDTH; write_group++,
3349 write_test_bgn += RW_MGR_MEM_DQ_PER_WRITE_DQS) {
3350 /* Initialized the group failure */
3353 current_run = run_groups & ((1 <<
3354 RW_MGR_NUM_DQS_PER_WRITE_GROUP) - 1);
3355 run_groups = run_groups >>
3356 RW_MGR_NUM_DQS_PER_WRITE_GROUP;
3358 if (current_run == 0)
3361 writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
3362 SCC_MGR_GROUP_COUNTER_OFFSET);
3363 scc_mgr_zero_group(write_group, write_test_bgn,
3366 for (read_group = write_group *
3367 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3368 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3370 read_group < (write_group + 1) *
3371 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3372 RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3374 read_group++, read_test_bgn +=
3375 RW_MGR_MEM_DQ_PER_READ_DQS) {
3376 /* Calibrate the VFIFO */
3377 if (!((STATIC_CALIB_STEPS) &
3378 CALIB_SKIP_VFIFO)) {
3379 if (!rw_mgr_mem_calibrate_vfifo
3385 phy_debug_mode_flags &
3386 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3393 /* Calibrate the output side */
3394 if (group_failed == 0) {
3395 for (rank_bgn = 0, sr = 0; rank_bgn
3396 < RW_MGR_MEM_NUMBER_OF_RANKS;
3398 NUM_RANKS_PER_SHADOW_REG,
3401 if (!((STATIC_CALIB_STEPS) &
3402 CALIB_SKIP_WRITES)) {
3403 if ((STATIC_CALIB_STEPS)
3404 & CALIB_SKIP_DELAY_SWEEPS) {
3405 /* not needed in quick mode! */
3408 * Determine if this set of
3409 * ranks should be skipped
3412 if (!param->skip_shadow_regs[sr]) {
3413 if (!rw_mgr_mem_calibrate_writes
3414 (rank_bgn, write_group,
3418 phy_debug_mode_flags &
3419 PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3431 if (group_failed == 0) {
3432 for (read_group = write_group *
3433 RW_MGR_MEM_IF_READ_DQS_WIDTH /
3434 RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3436 read_group < (write_group + 1)
3437 * RW_MGR_MEM_IF_READ_DQS_WIDTH
3438 / RW_MGR_MEM_IF_WRITE_DQS_WIDTH &&
3440 read_group++, read_test_bgn +=
3441 RW_MGR_MEM_DQ_PER_READ_DQS) {
3442 if (!((STATIC_CALIB_STEPS) &
3443 CALIB_SKIP_WRITES)) {
3444 if (!rw_mgr_mem_calibrate_vfifo_end
3445 (read_group, read_test_bgn)) {
3448 if (!(gbl->phy_debug_mode_flags
3449 & PHY_DEBUG_SWEEP_ALL_GROUPS)) {
3457 if (group_failed != 0)
3462 * USER If there are any failing groups then report
3465 if (failing_groups != 0)
3468 /* Calibrate the LFIFO */
3469 if (!((STATIC_CALIB_STEPS) & CALIB_SKIP_LFIFO)) {
3471 * If we're skipping groups as part of debug,
3472 * don't calibrate LFIFO.
3474 if (param->skip_groups == 0) {
3475 if (!rw_mgr_mem_calibrate_lfifo())
3483 * Do not remove this line as it makes sure all of our decisions
3484 * have been applied.
3486 writel(0, &sdr_scc_mgr->update);
3490 static uint32_t run_mem_calibrate(void)
3493 uint32_t debug_info;
3495 debug("%s:%d\n", __func__, __LINE__);
3497 /* Reset pass/fail status shown on afi_cal_success/fail */
3498 writel(PHY_MGR_CAL_RESET, &phy_mgr_cfg->cal_status);
3500 /* stop tracking manger */
3501 uint32_t ctrlcfg = readl(&sdr_ctrl->ctrl_cfg);
3503 writel(ctrlcfg & 0xFFBFFFFF, &sdr_ctrl->ctrl_cfg);
3506 rw_mgr_mem_initialize();
3508 pass = mem_calibrate();
3510 mem_precharge_and_activate();
3511 writel(0, &phy_mgr_cmd->fifo_reset);
3515 * Don't return control of the PHY back to AFI when in debug mode.
3517 if ((gbl->phy_debug_mode_flags & PHY_DEBUG_IN_DEBUG_MODE) == 0) {
3518 rw_mgr_mem_handoff();
3520 * In Hard PHY this is a 2-bit control:
3522 * 1: DDIO Mux Select
3524 writel(0x2, &phy_mgr_cfg->mux_sel);
3527 writel(ctrlcfg, &sdr_ctrl->ctrl_cfg);
3530 printf("%s: CALIBRATION PASSED\n", __FILE__);
3535 if (gbl->fom_in > 0xff)
3538 if (gbl->fom_out > 0xff)
3539 gbl->fom_out = 0xff;
3541 /* Update the FOM in the register file */
3542 debug_info = gbl->fom_in;
3543 debug_info |= gbl->fom_out << 8;
3544 writel(debug_info, &sdr_reg_file->fom);
3546 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3547 writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
3549 printf("%s: CALIBRATION FAILED\n", __FILE__);
3551 debug_info = gbl->error_stage;
3552 debug_info |= gbl->error_substage << 8;
3553 debug_info |= gbl->error_group << 16;
3555 writel(debug_info, &sdr_reg_file->failing_stage);
3556 writel(debug_info, &phy_mgr_cfg->cal_debug_info);
3557 writel(PHY_MGR_CAL_FAIL, &phy_mgr_cfg->cal_status);
3559 /* Update the failing group/stage in the register file */
3560 debug_info = gbl->error_stage;
3561 debug_info |= gbl->error_substage << 8;
3562 debug_info |= gbl->error_group << 16;
3563 writel(debug_info, &sdr_reg_file->failing_stage);
3570 * hc_initialize_rom_data() - Initialize ROM data
3572 * Initialize ROM data.
3574 static void hc_initialize_rom_data(void)
3578 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_INST_ROM_WRITE_OFFSET;
3579 for (i = 0; i < ARRAY_SIZE(inst_rom_init); i++)
3580 writel(inst_rom_init[i], addr + (i << 2));
3582 addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_AC_ROM_WRITE_OFFSET;
3583 for (i = 0; i < ARRAY_SIZE(ac_rom_init); i++)
3584 writel(ac_rom_init[i], addr + (i << 2));
3588 * initialize_reg_file() - Initialize SDR register file
3590 * Initialize SDR register file.
3592 static void initialize_reg_file(void)
3594 /* Initialize the register file with the correct data */
3595 writel(REG_FILE_INIT_SEQ_SIGNATURE, &sdr_reg_file->signature);
3596 writel(0, &sdr_reg_file->debug_data_addr);
3597 writel(0, &sdr_reg_file->cur_stage);
3598 writel(0, &sdr_reg_file->fom);
3599 writel(0, &sdr_reg_file->failing_stage);
3600 writel(0, &sdr_reg_file->debug1);
3601 writel(0, &sdr_reg_file->debug2);
3605 * initialize_hps_phy() - Initialize HPS PHY
3607 * Initialize HPS PHY.
3609 static void initialize_hps_phy(void)
3613 * Tracking also gets configured here because it's in the
3616 uint32_t trk_sample_count = 7500;
3617 uint32_t trk_long_idle_sample_count = (10 << 16) | 100;
3619 * Format is number of outer loops in the 16 MSB, sample
3624 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET(2);
3625 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET(1);
3626 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET(1);
3627 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET(1);
3628 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET(0);
3629 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET(1);
3631 * This field selects the intrinsic latency to RDATA_EN/FULL path.
3632 * 00-bypass, 01- add 5 cycles, 10- add 10 cycles, 11- add 15 cycles.
3634 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET(0);
3635 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET(
3637 writel(reg, &sdr_ctrl->phy_ctrl0);
3640 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET(
3642 SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH);
3643 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(
3644 trk_long_idle_sample_count);
3645 writel(reg, &sdr_ctrl->phy_ctrl1);
3648 reg |= SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(
3649 trk_long_idle_sample_count >>
3650 SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH);
3651 writel(reg, &sdr_ctrl->phy_ctrl2);
3654 static void initialize_tracking(void)
3656 uint32_t concatenated_longidle = 0x0;
3657 uint32_t concatenated_delays = 0x0;
3658 uint32_t concatenated_rw_addr = 0x0;
3659 uint32_t concatenated_refresh = 0x0;
3660 uint32_t trk_sample_count = 7500;
3661 uint32_t dtaps_per_ptap;
3665 * compute usable version of value in case we skip full
3670 while (tmp_delay < IO_DELAY_PER_OPA_TAP) {
3672 tmp_delay += IO_DELAY_PER_DCHAIN_TAP;
3676 concatenated_longidle = concatenated_longidle ^ 10;
3677 /*longidle outer loop */
3678 concatenated_longidle = concatenated_longidle << 16;
3679 concatenated_longidle = concatenated_longidle ^ 100;
3680 /*longidle sample count */
3681 concatenated_delays = concatenated_delays ^ 243;
3682 /* trfc, worst case of 933Mhz 4Gb */
3683 concatenated_delays = concatenated_delays << 8;
3684 concatenated_delays = concatenated_delays ^ 14;
3685 /* trcd, worst case */
3686 concatenated_delays = concatenated_delays << 8;
3687 concatenated_delays = concatenated_delays ^ 10;
3689 concatenated_delays = concatenated_delays << 8;
3690 concatenated_delays = concatenated_delays ^ 4;
3693 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_IDLE;
3694 concatenated_rw_addr = concatenated_rw_addr << 8;
3695 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_ACTIVATE_1;
3696 concatenated_rw_addr = concatenated_rw_addr << 8;
3697 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_SGLE_READ;
3698 concatenated_rw_addr = concatenated_rw_addr << 8;
3699 concatenated_rw_addr = concatenated_rw_addr ^ RW_MGR_PRECHARGE_ALL;
3701 concatenated_refresh = concatenated_refresh ^ RW_MGR_REFRESH_ALL;
3702 concatenated_refresh = concatenated_refresh << 24;
3703 concatenated_refresh = concatenated_refresh ^ 1000; /* trefi */
3705 /* Initialize the register file with the correct data */
3706 writel(dtaps_per_ptap, &sdr_reg_file->dtaps_per_ptap);
3707 writel(trk_sample_count, &sdr_reg_file->trk_sample_count);
3708 writel(concatenated_longidle, &sdr_reg_file->trk_longidle);
3709 writel(concatenated_delays, &sdr_reg_file->delays);
3710 writel(concatenated_rw_addr, &sdr_reg_file->trk_rw_mgr_addr);
3711 writel(RW_MGR_MEM_IF_READ_DQS_WIDTH, &sdr_reg_file->trk_read_dqs_width);
3712 writel(concatenated_refresh, &sdr_reg_file->trk_rfsh);
3715 int sdram_calibration_full(void)
3717 struct param_type my_param;
3718 struct gbl_type my_gbl;
3725 /* Initialize the debug mode flags */
3726 gbl->phy_debug_mode_flags = 0;
3727 /* Set the calibration enabled by default */
3728 gbl->phy_debug_mode_flags |= PHY_DEBUG_ENABLE_CAL_RPT;
3730 * Only sweep all groups (regardless of fail state) by default
3731 * Set enabled read test by default.
3733 #if DISABLE_GUARANTEED_READ
3734 gbl->phy_debug_mode_flags |= PHY_DEBUG_DISABLE_GUARANTEED_READ;
3736 /* Initialize the register file */
3737 initialize_reg_file();
3739 /* Initialize any PHY CSR */
3740 initialize_hps_phy();
3742 scc_mgr_initialize();
3744 initialize_tracking();
3746 /* USER Enable all ranks, groups */
3747 for (i = 0; i < RW_MGR_MEM_NUMBER_OF_RANKS; i++)
3748 param->skip_ranks[i] = 0;
3749 for (i = 0; i < NUM_SHADOW_REGS; ++i)
3750 param->skip_shadow_regs[i] = 0;
3751 param->skip_groups = 0;
3753 printf("%s: Preparing to start memory calibration\n", __FILE__);
3755 debug("%s:%d\n", __func__, __LINE__);
3756 debug_cond(DLEVEL == 1,
3757 "DDR3 FULL_RATE ranks=%u cs/dimm=%u dq/dqs=%u,%u vg/dqs=%u,%u ",
3758 RW_MGR_MEM_NUMBER_OF_RANKS, RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM,
3759 RW_MGR_MEM_DQ_PER_READ_DQS, RW_MGR_MEM_DQ_PER_WRITE_DQS,
3760 RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS,
3761 RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS);
3762 debug_cond(DLEVEL == 1,
3763 "dqs=%u,%u dq=%u dm=%u ptap_delay=%u dtap_delay=%u ",
3764 RW_MGR_MEM_IF_READ_DQS_WIDTH, RW_MGR_MEM_IF_WRITE_DQS_WIDTH,
3765 RW_MGR_MEM_DATA_WIDTH, RW_MGR_MEM_DATA_MASK_WIDTH,
3766 IO_DELAY_PER_OPA_TAP, IO_DELAY_PER_DCHAIN_TAP);
3767 debug_cond(DLEVEL == 1, "dtap_dqsen_delay=%u, dll=%u",
3768 IO_DELAY_PER_DQS_EN_DCHAIN_TAP, IO_DLL_CHAIN_LENGTH);
3769 debug_cond(DLEVEL == 1, "max values: en_p=%u dqdqs_p=%u en_d=%u dqs_in_d=%u ",
3770 IO_DQS_EN_PHASE_MAX, IO_DQDQS_OUT_PHASE_MAX,
3771 IO_DQS_EN_DELAY_MAX, IO_DQS_IN_DELAY_MAX);
3772 debug_cond(DLEVEL == 1, "io_in_d=%u io_out1_d=%u io_out2_d=%u ",
3773 IO_IO_IN_DELAY_MAX, IO_IO_OUT1_DELAY_MAX,
3774 IO_IO_OUT2_DELAY_MAX);
3775 debug_cond(DLEVEL == 1, "dqs_in_reserve=%u dqs_out_reserve=%u\n",
3776 IO_DQS_IN_RESERVE, IO_DQS_OUT_RESERVE);
3778 hc_initialize_rom_data();
3780 /* update info for sims */
3781 reg_file_set_stage(CAL_STAGE_NIL);
3782 reg_file_set_group(0);
3785 * Load global needed for those actions that require
3786 * some dynamic calibration support.
3788 dyn_calib_steps = STATIC_CALIB_STEPS;
3790 * Load global to allow dynamic selection of delay loop settings
3791 * based on calibration mode.
3793 if (!(dyn_calib_steps & CALIB_SKIP_DELAY_LOOPS))
3794 skip_delay_mask = 0xff;
3796 skip_delay_mask = 0x0;
3798 pass = run_mem_calibrate();
3800 printf("%s: Calibration complete\n", __FILE__);