1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
16 #include "sdram_soc64.h"
18 #include <asm/arch/firewall.h>
19 #include <asm/arch/system_manager.h>
20 #include <asm/arch/reset_manager.h>
22 #include <dm/device_compat.h>
23 #include <linux/sizes.h>
25 #define PGTABLE_OFF 0x4000
27 u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
29 return readl(plat->iomhc + reg);
32 u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
34 return readl(plat->hmc + reg);
37 u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
40 return writel(data, plat->hmc + reg);
43 u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
46 return writel(data, plat->ddr_sch + reg);
49 int emif_clear(struct altera_sdram_platdata *plat)
51 hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
53 return wait_for_bit_le32((const void *)(plat->hmc +
55 DDR_HMC_RSTHANDSHAKE_MASK,
59 int emif_reset(struct altera_sdram_platdata *plat)
63 c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
64 s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
66 debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
67 c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
68 hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
69 hmc_readl(plat, DRAMSTS));
71 if (s2c && emif_clear(plat)) {
72 printf("DDR: emif_clear() failed\n");
76 debug("DDR: Triggerring emif reset\n");
77 hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
79 /* if seq2core[3] = 0, we are good */
80 ret = wait_for_bit_le32((const void *)(plat->hmc +
82 DDR_HMC_SEQ2CORE_INT_RESP_MASK,
85 printf("DDR: failed to get ack from EMIF\n");
89 ret = emif_clear(plat);
91 printf("DDR: emif_clear() failed\n");
95 debug("DDR: %s triggered successly\n", __func__);
99 int poll_hmc_clock_status(void)
101 return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
102 SYSMGR_SOC64_HMC_CLK),
103 SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
106 void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
110 if (addr % CONFIG_SYS_CACHELINE_SIZE) {
111 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
116 if (size % CONFIG_SYS_CACHELINE_SIZE) {
117 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
122 /* Use DC ZVA instruction to clear memory to zeros by a cache line */
123 for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
124 asm volatile("dc zva, %0"
128 addr += CONFIG_SYS_CACHELINE_SIZE;
132 void sdram_init_ecc_bits(bd_t *bd)
134 phys_size_t size, size_init;
135 phys_addr_t start_addr;
137 unsigned int start = get_timer(0);
141 start_addr = bd->bi_dram[0].start;
142 size = bd->bi_dram[0].size;
144 /* Initialize small block for page table */
145 memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
146 gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
147 gd->arch.tlb_size = PGTABLE_SIZE;
148 start_addr += PGTABLE_SIZE + PGTABLE_OFF;
149 size -= (PGTABLE_OFF + PGTABLE_SIZE);
154 size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
155 sdram_clear_mem(start_addr, size_init);
157 start_addr += size_init;
162 if (bank >= CONFIG_NR_DRAM_BANKS)
165 start_addr = bd->bi_dram[bank].start;
166 size = bd->bi_dram[bank].size;
172 printf("SDRAM-ECC: Initialized success with %d ms\n",
173 (unsigned int)get_timer(start));
176 void sdram_size_check(bd_t *bd)
178 phys_size_t total_ram_check = 0;
179 phys_size_t ram_check = 0;
180 phys_addr_t start = 0;
183 /* Sanity check ensure correct SDRAM size specified */
184 debug("DDR: Running SDRAM size sanity check\n");
186 for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
187 start = bd->bi_dram[bank].start;
188 while (ram_check < bd->bi_dram[bank].size) {
189 ram_check += get_ram_size((void *)(start + ram_check),
192 total_ram_check += ram_check;
196 /* If the ram_size is 2GB smaller, we can assume the IO space is
197 * not mapped in. gd->ram_size is the actual size of the dram
198 * not the accessible size.
200 if (total_ram_check != gd->ram_size) {
201 puts("DDR: SDRAM size check failed!\n");
205 debug("DDR: SDRAM size check passed!\n");
209 * sdram_calculate_size() - Calculate SDRAM size
211 * Calculate SDRAM device size based on SDRAM controller parameters.
212 * Size is specified in bytes.
214 phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
216 u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
218 phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
219 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
220 DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
221 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
222 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
224 size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
225 DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
230 static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
232 struct altera_sdram_platdata *plat = dev->platdata;
235 addr = dev_read_addr_index(dev, 0);
236 if (addr == FDT_ADDR_T_NONE)
238 plat->ddr_sch = (void __iomem *)addr;
240 addr = dev_read_addr_index(dev, 1);
241 if (addr == FDT_ADDR_T_NONE)
243 plat->iomhc = (void __iomem *)addr;
245 addr = dev_read_addr_index(dev, 2);
246 if (addr == FDT_ADDR_T_NONE)
248 plat->hmc = (void __iomem *)addr;
253 static int altera_sdram_probe(struct udevice *dev)
256 struct altera_sdram_priv *priv = dev_get_priv(dev);
258 ret = reset_get_bulk(dev, &priv->resets);
260 dev_err(dev, "Can't get reset: %d\n", ret);
263 reset_deassert_bulk(&priv->resets);
265 if (sdram_mmr_init_full(dev) != 0) {
266 puts("SDRAM init failed.\n");
273 reset_release_bulk(&priv->resets);
277 static int altera_sdram_get_info(struct udevice *dev,
278 struct ram_info *info)
280 struct altera_sdram_priv *priv = dev_get_priv(dev);
282 info->base = priv->info.base;
283 info->size = priv->info.size;
288 static struct ram_ops altera_sdram_ops = {
289 .get_info = altera_sdram_get_info,
292 static const struct udevice_id altera_sdram_ids[] = {
293 { .compatible = "altr,sdr-ctl-s10" },
294 { .compatible = "intel,sdr-ctl-agilex" },
298 U_BOOT_DRIVER(altera_sdram) = {
299 .name = "altr_sdr_ctl",
301 .of_match = altera_sdram_ids,
302 .ops = &altera_sdram_ops,
303 .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
304 .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
305 .probe = altera_sdram_probe,
306 .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),