drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <div64.h>
  11 #include <fdtdec.h>
  12 #include <ram.h>
  13 #include <reset.h>
  14 #include "sdram_s10.h"
  15 #include <wait_bit.h>
  16 #include <asm/arch/firewall_s10.h>
  17 #include <asm/arch/system_manager.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/io.h>
  20 #include <linux/sizes.h>
  21
  22 struct altera_sdram_priv {
  23         struct ram_info info;
  24         struct reset_ctl_bulk resets;
  25 };
  26
  27 struct altera_sdram_platdata {
  28         void __iomem *hmc;
  29         void __iomem *ddr_sch;
  30         void __iomem *iomhc;
  31 };
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 static const struct socfpga_system_manager *sysmgr_regs =
  36                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  37
  38 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  39
  40 #define PGTABLE_OFF     0x4000
  41
  42 /* The followring are the supported configurations */
  43 u32 ddr_config[] = {
  44         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  45         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  46         DDR_CONFIG(0, 3, 10, 12),
  47         DDR_CONFIG(0, 3,  9, 13),
  48         DDR_CONFIG(0, 3, 10, 13),
  49         DDR_CONFIG(0, 3,  9, 14),
  50         DDR_CONFIG(0, 3, 10, 14),
  51         DDR_CONFIG(0, 3, 10, 15),
  52         DDR_CONFIG(0, 3, 11, 14),
  53         DDR_CONFIG(0, 3, 11, 15),
  54         DDR_CONFIG(0, 3, 10, 16),
  55         DDR_CONFIG(0, 3, 11, 16),
  56         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  57         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  58         DDR_CONFIG(1, 3, 10, 14),
  59         DDR_CONFIG(1, 4, 10, 14),
  60         DDR_CONFIG(1, 3, 10, 15),
  61         DDR_CONFIG(1, 4, 10, 15),
  62         DDR_CONFIG(1, 3, 10, 16),
  63         DDR_CONFIG(1, 4, 10, 16),
  64         DDR_CONFIG(1, 3, 10, 17),
  65         DDR_CONFIG(1, 4, 10, 17),
  66 };
  67
  68 static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  69 {
  70         return readl(plat->iomhc + reg);
  71 }
  72
  73 static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  74 {
  75         return readl(plat->hmc + reg);
  76 }
  77
  78 static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  79                           u32 data, u32 reg)
  80 {
  81         return writel(data, plat->hmc + reg);
  82 }
  83
  84 static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  85                           u32 reg)
  86 {
  87         return writel(data, plat->ddr_sch + reg);
  88 }
  89
  90 int match_ddr_conf(u32 ddr_conf)
  91 {
  92         int i;
  93
  94         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  95                 if (ddr_conf == ddr_config[i])
  96                         return i;
  97         }
  98         return 0;
  99 }
 100
 101 static int emif_clear(struct altera_sdram_platdata *plat)
 102 {
 103         hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
 104
 105         return wait_for_bit_le32((const void *)(plat->hmc +
 106                                  RSTHANDSHAKESTAT),
 107                                  DDR_HMC_RSTHANDSHAKE_MASK,
 108                                  false, 1000, false);
 109 }
 110
 111 static int emif_reset(struct altera_sdram_platdata *plat)
 112 {
 113         u32 c2s, s2c, ret;
 114
 115         c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
 116         s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
 117
 118         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 119               c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
 120               hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
 121               hmc_readl(plat, DRAMSTS));
 122
 123         if (s2c && emif_clear(plat)) {
 124                 printf("DDR: emif_clear() failed\n");
 125                 return -1;
 126         }
 127
 128         debug("DDR: Triggerring emif reset\n");
 129         hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 130
 131         /* if seq2core[3] = 0, we are good */
 132         ret = wait_for_bit_le32((const void *)(plat->hmc +
 133                                  RSTHANDSHAKESTAT),
 134                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
 135                                  false, 1000, false);
 136         if (ret) {
 137                 printf("DDR: failed to get ack from EMIF\n");
 138                 return ret;
 139         }
 140
 141         ret = emif_clear(plat);
 142         if (ret) {
 143                 printf("DDR: emif_clear() failed\n");
 144                 return ret;
 145         }
 146
 147         debug("DDR: %s triggered successly\n", __func__);
 148         return 0;
 149 }
 150
 151 static int poll_hmc_clock_status(void)
 152 {
 153         return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
 154                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 155 }
 156
 157 static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
 158 {
 159         phys_size_t i;
 160
 161         if (addr % CONFIG_SYS_CACHELINE_SIZE) {
 162                 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
 163                        addr);
 164                 hang();
 165         }
 166
 167         if (size % CONFIG_SYS_CACHELINE_SIZE) {
 168                 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
 169                        size);
 170                 hang();
 171         }
 172
 173         /* Use DC ZVA instruction to clear memory to zeros by a cache line */
 174         for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
 175                 asm volatile("dc zva, %0"
 176                      :
 177                      : "r"(addr)
 178                      : "memory");
 179                 addr += CONFIG_SYS_CACHELINE_SIZE;
 180         }
 181 }
 182
 183 static void sdram_init_ecc_bits(bd_t *bd)
 184 {
 185         phys_size_t size, size_init;
 186         phys_addr_t start_addr;
 187         int bank = 0;
 188         unsigned int start = get_timer(0);
 189
 190         icache_enable();
 191
 192         start_addr = bd->bi_dram[0].start;
 193         size = bd->bi_dram[0].size;
 194
 195         /* Initialize small block for page table */
 196         memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
 197         gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
 198         gd->arch.tlb_size = PGTABLE_SIZE;
 199         start_addr += PGTABLE_SIZE + PGTABLE_OFF;
 200         size -= (PGTABLE_OFF + PGTABLE_SIZE);
 201         dcache_enable();
 202
 203         while (1) {
 204                 while (size) {
 205                         size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
 206                         sdram_clear_mem(start_addr, size_init);
 207                         size -= size_init;
 208                         start_addr += size_init;
 209                         WATCHDOG_RESET();
 210                 }
 211
 212                 bank++;
 213                 if (bank >= CONFIG_NR_DRAM_BANKS)
 214                         break;
 215
 216                 start_addr = bd->bi_dram[bank].start;
 217                 size = bd->bi_dram[bank].size;
 218         }
 219
 220         dcache_disable();
 221         icache_disable();
 222
 223         printf("SDRAM-ECC: Initialized success with %d ms\n",
 224                (unsigned int)get_timer(start));
 225 }
 226
 227 static void sdram_size_check(bd_t *bd)
 228 {
 229         phys_size_t total_ram_check = 0;
 230         phys_size_t ram_check = 0;
 231         phys_addr_t start = 0;
 232         int bank;
 233
 234         /* Sanity check ensure correct SDRAM size specified */
 235         debug("DDR: Running SDRAM size sanity check\n");
 236
 237         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 238                 start = bd->bi_dram[bank].start;
 239                 while (ram_check < bd->bi_dram[bank].size) {
 240                         ram_check += get_ram_size((void *)(start + ram_check),
 241                                                  (phys_size_t)SZ_1G);
 242                 }
 243                 total_ram_check += ram_check;
 244                 ram_check = 0;
 245         }
 246
 247         /* If the ram_size is 2GB smaller, we can assume the IO space is
 248          * not mapped in.  gd->ram_size is the actual size of the dram
 249          * not the accessible size.
 250          */
 251         if (total_ram_check != gd->ram_size) {
 252                 puts("DDR: SDRAM size check failed!\n");
 253                 hang();
 254         }
 255
 256         debug("DDR: SDRAM size check passed!\n");
 257 }
 258
 259 /**
 260  * sdram_calculate_size() - Calculate SDRAM size
 261  *
 262  * Calculate SDRAM device size based on SDRAM controller parameters.
 263  * Size is specified in bytes.
 264  */
 265 static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
 266 {
 267         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 268
 269         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 270                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 271                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 272                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 273                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 274
 275         size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
 276                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 277
 278         return size;
 279 }
 280
 281 /**
 282  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 283  *
 284  * Initialize the SDRAM MMR.
 285  */
 286 static int sdram_mmr_init_full(struct udevice *dev)
 287 {
 288         struct altera_sdram_platdata *plat = dev->platdata;
 289         struct altera_sdram_priv *priv = dev_get_priv(dev);
 290         u32 update_value, io48_value, ddrioctl;
 291         u32 i;
 292         int ret;
 293         phys_size_t hw_size;
 294         bd_t bd = {0};
 295
 296         /* Enable access to DDR from CPU master */
 297         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
 298                      CCU_ADBASE_DI_MASK);
 299         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
 300                      CCU_ADBASE_DI_MASK);
 301         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
 302                      CCU_ADBASE_DI_MASK);
 303         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
 304                      CCU_ADBASE_DI_MASK);
 305         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
 306                      CCU_ADBASE_DI_MASK);
 307         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
 308                      CCU_ADBASE_DI_MASK);
 309         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
 310                      CCU_ADBASE_DI_MASK);
 311
 312         /* Enable access to DDR from IO master */
 313         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
 314                      CCU_ADBASE_DI_MASK);
 315         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
 316                      CCU_ADBASE_DI_MASK);
 317         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 318                      CCU_ADBASE_DI_MASK);
 319         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 320                      CCU_ADBASE_DI_MASK);
 321         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 322                      CCU_ADBASE_DI_MASK);
 323         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 324                      CCU_ADBASE_DI_MASK);
 325
 326         /* this enables nonsecure access to DDR */
 327         /* mpuregion0addr_limit */
 328         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 329         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 330
 331         /* nonmpuregion0addr_limit */
 332         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 333                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 334         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 335
 336         /* Enable mpuregion0enable and nonmpuregion0enable */
 337         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 338                               FW_MPU_DDR_SCR_EN_SET);
 339
 340         /* Ensure HMC clock is running */
 341         if (poll_hmc_clock_status()) {
 342                 puts("DDR: Error as HMC clock not running\n");
 343                 return -1;
 344         }
 345
 346         /* Try 3 times to do a calibration */
 347         for (i = 0; i < 3; i++) {
 348                 ret = wait_for_bit_le32((const void *)(plat->hmc +
 349                                         DDRCALSTAT),
 350                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 351                                         false);
 352                 if (!ret)
 353                         break;
 354
 355                 emif_reset(plat);
 356         }
 357
 358         if (ret) {
 359                 puts("DDR: Error as SDRAM calibration failed\n");
 360                 return -1;
 361         }
 362         debug("DDR: Calibration success\n");
 363
 364         u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
 365         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 366         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 367         u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
 368         u32 caltim0 = hmc_readl(plat, CALTIMING0);
 369         u32 caltim1 = hmc_readl(plat, CALTIMING1);
 370         u32 caltim2 = hmc_readl(plat, CALTIMING2);
 371         u32 caltim3 = hmc_readl(plat, CALTIMING3);
 372         u32 caltim4 = hmc_readl(plat, CALTIMING4);
 373         u32 caltim9 = hmc_readl(plat, CALTIMING9);
 374
 375         /*
 376          * Configure the DDR IO size [0xFFCFB008]
 377          * niosreserve0: Used to indicate DDR width &
 378          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 379          *      bit[8]   = 1 if user-mode OCT is present
 380          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 381          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 382          * niosreserve1: IP ADCDS version encoded as 16 bit value
 383          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 384          *                          3=EAP, 4-6 are reserved)
 385          *      bit[5:3] = Service Pack # (e.g. 1)
 386          *      bit[9:6] = Minor Release #
 387          *      bit[14:10] = Major Release #
 388          */
 389         update_value = hmc_readl(plat, NIOSRESERVED0);
 390         hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
 391         ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
 392
 393         /* enable HPS interface to HMC */
 394         hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 395
 396         /* Set the DDR Configuration */
 397         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 398                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 399                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 400                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 401                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 402
 403         update_value = match_ddr_conf(io48_value);
 404         if (update_value)
 405                 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
 406
 407         /* Configure HMC dramaddrw */
 408         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
 409
 410         /*
 411          * Configure DDR timing
 412          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 413          *  WRTOMISS = WL + tWR + tRP + tRCD and
 414          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 415          *  First part of equation is in memory clock units so divide by 2
 416          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 417          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 418          */
 419         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 420
 421         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 422                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 423                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 424                        (burst_len >> 2);
 425         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 426                        (burst_len >> 1)) >> 1) -
 427                       /* Up to here was in memory cycles so divide by 2 */
 428                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 429                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 430                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 431
 432         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 433                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 434                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 435                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 436                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 437                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 438                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 439                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 440                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 441                         (((ddrioctl == 1) ? 1 : 0) <<
 442                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 443                         DDR_SCH_DDRTIMING);
 444
 445         /* Configure DDR mode [precharge = 0] */
 446         ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
 447                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 448                         DDR_SCH_DDRMODE);
 449
 450         /* Configure the read latency */
 451         ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 452                         DDR_READ_LATENCY_DELAY,
 453                         DDR_SCH_READ_LATENCY);
 454
 455         /*
 456          * Configuring timing values concerning activate commands
 457          * [FAWBANK alway 1 because always 4 bank DDR]
 458          */
 459         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 460                          DDR_SCH_ACTIVATE_RRD_OFF) |
 461                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 462                          DDR_SCH_ACTIVATE_FAW_OFF) |
 463                         (DDR_ACTIVATE_FAWBANK <<
 464                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 465                         DDR_SCH_ACTIVATE);
 466
 467         /*
 468          * Configuring timing values concerning device to device data bus
 469          * ownership change
 470          */
 471         ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 472                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 473                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 474                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 475                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 476                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 477                         DDR_SCH_DEVTODEV);
 478
 479         /* assigning the SDRAM size */
 480         unsigned long long size = sdram_calculate_size(plat);
 481         /* If the size is invalid, use default Config size */
 482         if (size <= 0)
 483                 hw_size = PHYS_SDRAM_1_SIZE;
 484         else
 485                 hw_size = size;
 486
 487         /* Get bank configuration from devicetree */
 488         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 489                                      (phys_size_t *)&gd->ram_size, &bd);
 490         if (ret) {
 491                 puts("DDR: Failed to decode memory node\n");
 492                 return -1;
 493         }
 494
 495         if (gd->ram_size != hw_size)
 496                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 497
 498         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 499
 500         /* Enable or disable the SDRAM ECC */
 501         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 502                 setbits_le32(plat->hmc + ECCCTRL1,
 503                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 504                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 505                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 506                 clrbits_le32(plat->hmc + ECCCTRL1,
 507                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 508                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 509                 setbits_le32(plat->hmc + ECCCTRL2,
 510                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 511                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 512                 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 513
 514                 /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
 515                 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 516
 517                 /* Initialize memory content if not from warm reset */
 518                 if (!cpu_has_been_warmreset())
 519                         sdram_init_ecc_bits(&bd);
 520         } else {
 521                 clrbits_le32(plat->hmc + ECCCTRL1,
 522                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 523                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 524                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 525                 clrbits_le32(plat->hmc + ECCCTRL2,
 526                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 527                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 528         }
 529
 530         sdram_size_check(&bd);
 531
 532         priv->info.base = bd.bi_dram[0].start;
 533         priv->info.size = gd->ram_size;
 534
 535         debug("DDR: HMC init success\n");
 536         return 0;
 537 }
 538
 539 static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
 540 {
 541         struct altera_sdram_platdata *plat = dev->platdata;
 542         fdt_addr_t addr;
 543
 544         addr = dev_read_addr_index(dev, 0);
 545         if (addr == FDT_ADDR_T_NONE)
 546                 return -EINVAL;
 547         plat->ddr_sch = (void __iomem *)addr;
 548
 549         addr = dev_read_addr_index(dev, 1);
 550         if (addr == FDT_ADDR_T_NONE)
 551                 return -EINVAL;
 552         plat->iomhc = (void __iomem *)addr;
 553
 554         addr = dev_read_addr_index(dev, 2);
 555         if (addr == FDT_ADDR_T_NONE)
 556                 return -EINVAL;
 557         plat->hmc = (void __iomem *)addr;
 558
 559         return 0;
 560 }
 561
 562 static int altera_sdram_probe(struct udevice *dev)
 563 {
 564         int ret;
 565         struct altera_sdram_priv *priv = dev_get_priv(dev);
 566
 567         ret = reset_get_bulk(dev, &priv->resets);
 568         if (ret) {
 569                 dev_err(dev, "Can't get reset: %d\n", ret);
 570                 return -ENODEV;
 571         }
 572         reset_deassert_bulk(&priv->resets);
 573
 574         if (sdram_mmr_init_full(dev) != 0) {
 575                 puts("SDRAM init failed.\n");
 576                 goto failed;
 577         }
 578
 579         return 0;
 580
 581 failed:
 582         reset_release_bulk(&priv->resets);
 583         return -ENODEV;
 584 }
 585
 586 static int altera_sdram_get_info(struct udevice *dev,
 587                                  struct ram_info *info)
 588 {
 589         struct altera_sdram_priv *priv = dev_get_priv(dev);
 590
 591         info->base = priv->info.base;
 592         info->size = priv->info.size;
 593
 594         return 0;
 595 }
 596
 597 static struct ram_ops altera_sdram_ops = {
 598         .get_info = altera_sdram_get_info,
 599 };
 600
 601 static const struct udevice_id altera_sdram_ids[] = {
 602         { .compatible = "altr,sdr-ctl-s10" },
 603         { /* sentinel */ }
 604 };
 605
 606 U_BOOT_DRIVER(altera_sdram) = {
 607         .name = "altr_sdr_ctl",
 608         .id = UCLASS_RAM,
 609         .of_match = altera_sdram_ids,
 610         .ops = &altera_sdram_ops,
 611         .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
 612         .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
 613         .probe = altera_sdram_probe,
 614         .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
 615 };