drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <errno.h>
   9 #include <div64.h>
  10 #include <fdtdec.h>
  11 #include <asm/io.h>
  12 #include <wait_bit.h>
  13 #include <asm/arch/firewall_s10.h>
  14 #include <asm/arch/sdram_s10.h>
  15 #include <asm/arch/system_manager.h>
  16 #include <asm/arch/reset_manager.h>
  17 #include <linux/sizes.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static const struct socfpga_system_manager *sysmgr_regs =
  22                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  23
  24 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  25
  26 #define PGTABLE_OFF     0x4000
  27
  28 /* The followring are the supported configurations */
  29 u32 ddr_config[] = {
  30         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  31         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  32         DDR_CONFIG(0, 3, 10, 12),
  33         DDR_CONFIG(0, 3,  9, 13),
  34         DDR_CONFIG(0, 3, 10, 13),
  35         DDR_CONFIG(0, 3,  9, 14),
  36         DDR_CONFIG(0, 3, 10, 14),
  37         DDR_CONFIG(0, 3, 10, 15),
  38         DDR_CONFIG(0, 3, 11, 14),
  39         DDR_CONFIG(0, 3, 11, 15),
  40         DDR_CONFIG(0, 3, 10, 16),
  41         DDR_CONFIG(0, 3, 11, 16),
  42         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  43         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  44         DDR_CONFIG(1, 3, 10, 14),
  45         DDR_CONFIG(1, 4, 10, 14),
  46         DDR_CONFIG(1, 3, 10, 15),
  47         DDR_CONFIG(1, 4, 10, 15),
  48         DDR_CONFIG(1, 3, 10, 16),
  49         DDR_CONFIG(1, 4, 10, 16),
  50         DDR_CONFIG(1, 3, 10, 17),
  51         DDR_CONFIG(1, 4, 10, 17),
  52 };
  53
  54 static u32 hmc_readl(u32 reg)
  55 {
  56         return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg)));
  57 }
  58
  59 static u32 hmc_ecc_readl(u32 reg)
  60 {
  61         return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
  62 }
  63
  64 static u32 hmc_ecc_writel(u32 data, u32 reg)
  65 {
  66         return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg));
  67 }
  68
  69 static u32 ddr_sch_writel(u32 data, u32 reg)
  70 {
  71         return writel(data,
  72                       (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg));
  73 }
  74
  75 int match_ddr_conf(u32 ddr_conf)
  76 {
  77         int i;
  78
  79         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  80                 if (ddr_conf == ddr_config[i])
  81                         return i;
  82         }
  83         return 0;
  84 }
  85
  86 static int emif_clear(void)
  87 {
  88         hmc_ecc_writel(0, RSTHANDSHAKECTRL);
  89
  90         return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
  91                                  RSTHANDSHAKESTAT),
  92                                  DDR_HMC_RSTHANDSHAKE_MASK,
  93                                  false, 1000, false);
  94 }
  95
  96 static int emif_reset(void)
  97 {
  98         u32 c2s, s2c, ret;
  99
 100         c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
 101         s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
 102
 103         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 104               c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1),
 105               hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS));
 106
 107         if (s2c && emif_clear()) {
 108                 printf("DDR: emif_clear() failed\n");
 109                 return -1;
 110         }
 111
 112         debug("DDR: Triggerring emif reset\n");
 113         hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 114
 115         /* if seq2core[3] = 0, we are good */
 116         ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
 117                                  RSTHANDSHAKESTAT),
 118                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
 119                                  false, 1000, false);
 120         if (ret) {
 121                 printf("DDR: failed to get ack from EMIF\n");
 122                 return ret;
 123         }
 124
 125         ret = emif_clear();
 126         if (ret) {
 127                 printf("DDR: emif_clear() failed\n");
 128                 return ret;
 129         }
 130
 131         debug("DDR: %s triggered successly\n", __func__);
 132         return 0;
 133 }
 134
 135 static int poll_hmc_clock_status(void)
 136 {
 137         return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
 138                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 139 }
 140
 141 static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
 142 {
 143         phys_size_t i;
 144
 145         if (addr % CONFIG_SYS_CACHELINE_SIZE) {
 146                 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
 147                        addr);
 148                 hang();
 149         }
 150
 151         if (size % CONFIG_SYS_CACHELINE_SIZE) {
 152                 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
 153                        size);
 154                 hang();
 155         }
 156
 157         /* Use DC ZVA instruction to clear memory to zeros by a cache line */
 158         for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
 159                 asm volatile("dc zva, %0"
 160                      :
 161                      : "r"(addr)
 162                      : "memory");
 163                 addr += CONFIG_SYS_CACHELINE_SIZE;
 164         }
 165 }
 166
 167 static void sdram_init_ecc_bits(bd_t *bd)
 168 {
 169         phys_size_t size, size_init;
 170         phys_addr_t start_addr;
 171         int bank = 0;
 172         unsigned int start = get_timer(0);
 173
 174         icache_enable();
 175
 176         start_addr = bd->bi_dram[0].start;
 177         size = bd->bi_dram[0].size;
 178
 179         /* Initialize small block for page table */
 180         memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
 181         gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
 182         gd->arch.tlb_size = PGTABLE_SIZE;
 183         start_addr += PGTABLE_SIZE + PGTABLE_OFF;
 184         size -= (PGTABLE_OFF + PGTABLE_SIZE);
 185         dcache_enable();
 186
 187         while (1) {
 188                 while (size) {
 189                         size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
 190                         sdram_clear_mem(start_addr, size_init);
 191                         size -= size_init;
 192                         start_addr += size_init;
 193                         WATCHDOG_RESET();
 194                 }
 195
 196                 bank++;
 197                 if (bank >= CONFIG_NR_DRAM_BANKS)
 198                         break;
 199
 200                 start_addr = bd->bi_dram[bank].start;
 201                 size = bd->bi_dram[bank].size;
 202         }
 203
 204         dcache_disable();
 205         icache_disable();
 206
 207         printf("SDRAM-ECC: Initialized success with %d ms\n",
 208                (unsigned int)get_timer(start));
 209 }
 210
 211 static void sdram_size_check(bd_t *bd)
 212 {
 213         phys_size_t total_ram_check = 0;
 214         phys_size_t ram_check = 0;
 215         phys_addr_t start = 0;
 216         int bank;
 217
 218         /* Sanity check ensure correct SDRAM size specified */
 219         debug("DDR: Running SDRAM size sanity check\n");
 220
 221         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 222                 start = bd->bi_dram[bank].start;
 223                 while (ram_check < bd->bi_dram[bank].size) {
 224                         ram_check += get_ram_size((void *)(start + ram_check),
 225                                                  (phys_size_t)SZ_1G);
 226                 }
 227                 total_ram_check += ram_check;
 228                 ram_check = 0;
 229         }
 230
 231         /* If the ram_size is 2GB smaller, we can assume the IO space is
 232          * not mapped in.  gd->ram_size is the actual size of the dram
 233          * not the accessible size.
 234          */
 235         if (total_ram_check != gd->ram_size) {
 236                 puts("DDR: SDRAM size check failed!\n");
 237                 hang();
 238         }
 239
 240         debug("DDR: SDRAM size check passed!\n");
 241 }
 242
 243 /**
 244  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 245  *
 246  * Initialize the SDRAM MMR.
 247  */
 248 int sdram_mmr_init_full(unsigned int unused)
 249 {
 250         u32 update_value, io48_value, ddrioctl;
 251         u32 i;
 252         int ret;
 253         phys_size_t hw_size;
 254         bd_t bd = {0};
 255
 256         /* Enable access to DDR from CPU master */
 257         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
 258                      CCU_ADBASE_DI_MASK);
 259         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
 260                      CCU_ADBASE_DI_MASK);
 261         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
 262                      CCU_ADBASE_DI_MASK);
 263         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
 264                      CCU_ADBASE_DI_MASK);
 265         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
 266                      CCU_ADBASE_DI_MASK);
 267         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
 268                      CCU_ADBASE_DI_MASK);
 269         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
 270                      CCU_ADBASE_DI_MASK);
 271
 272         /* Enable access to DDR from IO master */
 273         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
 274                      CCU_ADBASE_DI_MASK);
 275         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
 276                      CCU_ADBASE_DI_MASK);
 277         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 278                      CCU_ADBASE_DI_MASK);
 279         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 280                      CCU_ADBASE_DI_MASK);
 281         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 282                      CCU_ADBASE_DI_MASK);
 283         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 284                      CCU_ADBASE_DI_MASK);
 285
 286         /* this enables nonsecure access to DDR */
 287         /* mpuregion0addr_limit */
 288         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 289         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 290
 291         /* nonmpuregion0addr_limit */
 292         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 293                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 294         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 295
 296         /* Enable mpuregion0enable and nonmpuregion0enable */
 297         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 298                               FW_MPU_DDR_SCR_EN_SET);
 299
 300         /* Ensure HMC clock is running */
 301         if (poll_hmc_clock_status()) {
 302                 puts("DDR: Error as HMC clock not running\n");
 303                 return -1;
 304         }
 305
 306         /* release DDR scheduler from reset */
 307         socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 308
 309         /* Try 3 times to do a calibration */
 310         for (i = 0; i < 3; i++) {
 311                 ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS +
 312                                         DDRCALSTAT),
 313                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 314                                         false);
 315                 if (!ret)
 316                         break;
 317
 318                 emif_reset();
 319         }
 320
 321         if (ret) {
 322                 puts("DDR: Error as SDRAM calibration failed\n");
 323                 return -1;
 324         }
 325         debug("DDR: Calibration success\n");
 326
 327         u32 ctrlcfg0 = hmc_readl(CTRLCFG0);
 328         u32 ctrlcfg1 = hmc_readl(CTRLCFG1);
 329         u32 dramaddrw = hmc_readl(DRAMADDRW);
 330         u32 dramtim0 = hmc_readl(DRAMTIMING0);
 331         u32 caltim0 = hmc_readl(CALTIMING0);
 332         u32 caltim1 = hmc_readl(CALTIMING1);
 333         u32 caltim2 = hmc_readl(CALTIMING2);
 334         u32 caltim3 = hmc_readl(CALTIMING3);
 335         u32 caltim4 = hmc_readl(CALTIMING4);
 336         u32 caltim9 = hmc_readl(CALTIMING9);
 337
 338         /*
 339          * Configure the DDR IO size [0xFFCFB008]
 340          * niosreserve0: Used to indicate DDR width &
 341          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 342          *      bit[8]   = 1 if user-mode OCT is present
 343          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 344          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 345          * niosreserve1: IP ADCDS version encoded as 16 bit value
 346          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 347          *                          3=EAP, 4-6 are reserved)
 348          *      bit[5:3] = Service Pack # (e.g. 1)
 349          *      bit[9:6] = Minor Release #
 350          *      bit[14:10] = Major Release #
 351          */
 352         update_value = hmc_readl(NIOSRESERVED0);
 353         hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL);
 354         ddrioctl = hmc_ecc_readl(DDRIOCTRL);
 355
 356         /* enable HPS interface to HMC */
 357         hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 358
 359         /* Set the DDR Configuration */
 360         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 361                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 362                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 363                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 364                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 365
 366         update_value = match_ddr_conf(io48_value);
 367         if (update_value)
 368                 ddr_sch_writel(update_value, DDR_SCH_DDRCONF);
 369
 370         /* Configure HMC dramaddrw */
 371         hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH);
 372
 373         /*
 374          * Configure DDR timing
 375          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 376          *  WRTOMISS = WL + tWR + tRP + tRCD and
 377          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 378          *  First part of equation is in memory clock units so divide by 2
 379          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 380          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 381          */
 382         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 383
 384         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 385                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 386                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 387                        (burst_len >> 2);
 388         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 389                        (burst_len >> 1)) >> 1) -
 390                       /* Up to here was in memory cycles so divide by 2 */
 391                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 392                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 393                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 394
 395         ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 396                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 397                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 398                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 399                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 400                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 401                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 402                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 403                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 404                         (((ddrioctl == 1) ? 1 : 0) <<
 405                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 406                         DDR_SCH_DDRTIMING);
 407
 408         /* Configure DDR mode [precharge = 0] */
 409         ddr_sch_writel(((ddrioctl ? 0 : 1) <<
 410                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 411                         DDR_SCH_DDRMODE);
 412
 413         /* Configure the read latency */
 414         ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 415                         DDR_READ_LATENCY_DELAY,
 416                         DDR_SCH_READ_LATENCY);
 417
 418         /*
 419          * Configuring timing values concerning activate commands
 420          * [FAWBANK alway 1 because always 4 bank DDR]
 421          */
 422         ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 423                          DDR_SCH_ACTIVATE_RRD_OFF) |
 424                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 425                          DDR_SCH_ACTIVATE_FAW_OFF) |
 426                         (DDR_ACTIVATE_FAWBANK <<
 427                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 428                         DDR_SCH_ACTIVATE);
 429
 430         /*
 431          * Configuring timing values concerning device to device data bus
 432          * ownership change
 433          */
 434         ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 435                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 436                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 437                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 438                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 439                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 440                         DDR_SCH_DEVTODEV);
 441
 442         /* assigning the SDRAM size */
 443         unsigned long long size = sdram_calculate_size();
 444         /* If the size is invalid, use default Config size */
 445         if (size <= 0)
 446                 hw_size = PHYS_SDRAM_1_SIZE;
 447         else
 448                 hw_size = size;
 449
 450         /* Get bank configuration from devicetree */
 451         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 452                                      (phys_size_t *)&gd->ram_size, &bd);
 453         if (ret) {
 454                 puts("DDR: Failed to decode memory node\n");
 455                 return -1;
 456         }
 457
 458         if (gd->ram_size != hw_size)
 459                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 460
 461         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 462
 463         /* Enable or disable the SDRAM ECC */
 464         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 465                 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 466                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 467                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 468                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 469                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 470                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 471                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 472                 setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 473                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 474                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 475                 writel(DDR_HMC_ERRINTEN_INTMASK,
 476                        SOCFPGA_SDR_ADDRESS + ERRINTENS);
 477
 478                 /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
 479                 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 480
 481                 /* Initialize memory content if not from warm reset */
 482                 if (!cpu_has_been_warmreset())
 483                         sdram_init_ecc_bits(&bd);
 484         } else {
 485                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1,
 486                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 487                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 488                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 489                 clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2,
 490                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 491                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 492         }
 493
 494         sdram_size_check(&bd);
 495
 496         debug("DDR: HMC init success\n");
 497         return 0;
 498 }
 499
 500 /**
 501  * sdram_calculate_size() - Calculate SDRAM size
 502  *
 503  * Calculate SDRAM device size based on SDRAM controller parameters.
 504  * Size is specified in bytes.
 505  */
 506 phys_size_t sdram_calculate_size(void)
 507 {
 508         u32 dramaddrw = hmc_readl(DRAMADDRW);
 509
 510         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 511                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 512                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 513                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 514                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 515
 516         size *= (2 << (hmc_ecc_readl(DDRIOCTRL) &
 517                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 518
 519         return size;
 520 }