1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
15 #include "sdram_s10.h"
17 #include <asm/arch/firewall.h>
18 #include <asm/arch/reset_manager.h>
20 #include <linux/sizes.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
26 /* The followring are the supported configurations */
28 /* DDR_CONFIG(Address order,Bank,Column,Row) */
29 /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
30 DDR_CONFIG(0, 3, 10, 12),
31 DDR_CONFIG(0, 3, 9, 13),
32 DDR_CONFIG(0, 3, 10, 13),
33 DDR_CONFIG(0, 3, 9, 14),
34 DDR_CONFIG(0, 3, 10, 14),
35 DDR_CONFIG(0, 3, 10, 15),
36 DDR_CONFIG(0, 3, 11, 14),
37 DDR_CONFIG(0, 3, 11, 15),
38 DDR_CONFIG(0, 3, 10, 16),
39 DDR_CONFIG(0, 3, 11, 16),
40 DDR_CONFIG(0, 3, 12, 15), /* 0xa */
41 /* List for DDR4 only (pinout order > chip, bank, row, column) */
42 DDR_CONFIG(1, 3, 10, 14),
43 DDR_CONFIG(1, 4, 10, 14),
44 DDR_CONFIG(1, 3, 10, 15),
45 DDR_CONFIG(1, 4, 10, 15),
46 DDR_CONFIG(1, 3, 10, 16),
47 DDR_CONFIG(1, 4, 10, 16),
48 DDR_CONFIG(1, 3, 10, 17),
49 DDR_CONFIG(1, 4, 10, 17),
52 int match_ddr_conf(u32 ddr_conf)
56 for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
57 if (ddr_conf == ddr_config[i])
64 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
66 * Initialize the SDRAM MMR.
68 int sdram_mmr_init_full(struct udevice *dev)
70 struct altera_sdram_platdata *plat = dev->platdata;
71 struct altera_sdram_priv *priv = dev_get_priv(dev);
72 u32 update_value, io48_value, ddrioctl;
78 /* Enable access to DDR from CPU master */
79 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
81 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
83 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
85 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
87 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
89 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
91 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
94 /* Enable access to DDR from IO master */
95 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
97 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
99 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
101 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
103 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
105 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
108 /* Enable access to DDR from TCU */
109 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
111 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
113 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
115 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
117 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
119 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
122 /* this enables nonsecure access to DDR */
123 /* mpuregion0addr_limit */
124 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
125 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
127 /* nonmpuregion0addr_limit */
128 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
129 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
130 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
132 /* Enable mpuregion0enable and nonmpuregion0enable */
133 FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
134 FW_MPU_DDR_SCR_EN_SET);
136 /* Ensure HMC clock is running */
137 if (poll_hmc_clock_status()) {
138 puts("DDR: Error as HMC clock not running\n");
142 /* Try 3 times to do a calibration */
143 for (i = 0; i < 3; i++) {
144 ret = wait_for_bit_le32((const void *)(plat->hmc +
146 DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
155 puts("DDR: Error as SDRAM calibration failed\n");
158 debug("DDR: Calibration success\n");
160 u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
161 u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
162 u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
163 u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
164 u32 caltim0 = hmc_readl(plat, CALTIMING0);
165 u32 caltim1 = hmc_readl(plat, CALTIMING1);
166 u32 caltim2 = hmc_readl(plat, CALTIMING2);
167 u32 caltim3 = hmc_readl(plat, CALTIMING3);
168 u32 caltim4 = hmc_readl(plat, CALTIMING4);
169 u32 caltim9 = hmc_readl(plat, CALTIMING9);
172 * Configure the DDR IO size [0xFFCFB008]
173 * niosreserve0: Used to indicate DDR width &
174 * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
175 * bit[8] = 1 if user-mode OCT is present
176 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
177 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
178 * niosreserve1: IP ADCDS version encoded as 16 bit value
179 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
180 * 3=EAP, 4-6 are reserved)
181 * bit[5:3] = Service Pack # (e.g. 1)
182 * bit[9:6] = Minor Release #
183 * bit[14:10] = Major Release #
185 update_value = hmc_readl(plat, NIOSRESERVED0);
186 hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
187 ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
189 /* enable HPS interface to HMC */
190 hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
192 /* Set the DDR Configuration */
193 io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
194 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
195 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
196 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
197 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
199 update_value = match_ddr_conf(io48_value);
201 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
203 /* Configure HMC dramaddrw */
204 hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
207 * Configure DDR timing
208 * RDTOMISS = tRTP + tRP + tRCD - BL/2
209 * WRTOMISS = WL + tWR + tRP + tRCD and
210 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
211 * First part of equation is in memory clock units so divide by 2
212 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
213 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
215 u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
217 update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
218 CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
219 CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
221 io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
222 (burst_len >> 1)) >> 1) -
223 /* Up to here was in memory cycles so divide by 2 */
224 CALTIMING1_CFG_RD_TO_WR(caltim1) +
225 CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
226 CALTIMING4_CFG_PCH_TO_VALID(caltim4));
228 ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
229 DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
230 (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
231 (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
232 ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
233 (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
234 DDR_SCH_DDRTIMING_RDTOWR_OFF) |
235 (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
236 DDR_SCH_DDRTIMING_WRTORD_OFF) |
237 (((ddrioctl == 1) ? 1 : 0) <<
238 DDR_SCH_DDRTIMING_BWRATIO_OFF)),
241 /* Configure DDR mode [precharge = 0] */
242 ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
243 DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
246 /* Configure the read latency */
247 ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
248 DDR_READ_LATENCY_DELAY,
249 DDR_SCH_READ_LATENCY);
252 * Configuring timing values concerning activate commands
253 * [FAWBANK alway 1 because always 4 bank DDR]
255 ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
256 DDR_SCH_ACTIVATE_RRD_OFF) |
257 (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
258 DDR_SCH_ACTIVATE_FAW_OFF) |
259 (DDR_ACTIVATE_FAWBANK <<
260 DDR_SCH_ACTIVATE_FAWBANK_OFF)),
264 * Configuring timing values concerning device to device data bus
267 ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
268 DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
269 (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
270 DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
271 (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
272 DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
275 /* assigning the SDRAM size */
276 unsigned long long size = sdram_calculate_size(plat);
277 /* If the size is invalid, use default Config size */
279 hw_size = PHYS_SDRAM_1_SIZE;
283 /* Get bank configuration from devicetree */
284 ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
285 (phys_size_t *)&gd->ram_size, &bd);
287 puts("DDR: Failed to decode memory node\n");
291 if (gd->ram_size != hw_size)
292 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
294 printf("DDR: %lld MiB\n", gd->ram_size >> 20);
296 /* Enable or disable the SDRAM ECC */
297 if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
298 setbits_le32(plat->hmc + ECCCTRL1,
299 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
300 DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
301 DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
302 clrbits_le32(plat->hmc + ECCCTRL1,
303 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
304 DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
305 setbits_le32(plat->hmc + ECCCTRL2,
306 (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
307 DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
308 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
310 /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
311 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
313 /* Initialize memory content if not from warm reset */
314 if (!cpu_has_been_warmreset())
315 sdram_init_ecc_bits(&bd);
317 clrbits_le32(plat->hmc + ECCCTRL1,
318 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
319 DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
320 DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
321 clrbits_le32(plat->hmc + ECCCTRL2,
322 (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
323 DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
326 sdram_size_check(&bd);
328 priv->info.base = bd.bi_dram[0].start;
329 priv->info.size = gd->ram_size;
331 debug("DDR: HMC init success\n");