drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <ram.h>
  14 #include <reset.h>
  15 #include "sdram_s10.h"
  16 #include <wait_bit.h>
  17 #include <asm/arch/firewall.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22
  23 struct altera_sdram_priv {
  24         struct ram_info info;
  25         struct reset_ctl_bulk resets;
  26 };
  27
  28 struct altera_sdram_platdata {
  29         void __iomem *hmc;
  30         void __iomem *ddr_sch;
  31         void __iomem *iomhc;
  32 };
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  37
  38 #define PGTABLE_OFF     0x4000
  39
  40 /* The followring are the supported configurations */
  41 u32 ddr_config[] = {
  42         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  43         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  44         DDR_CONFIG(0, 3, 10, 12),
  45         DDR_CONFIG(0, 3,  9, 13),
  46         DDR_CONFIG(0, 3, 10, 13),
  47         DDR_CONFIG(0, 3,  9, 14),
  48         DDR_CONFIG(0, 3, 10, 14),
  49         DDR_CONFIG(0, 3, 10, 15),
  50         DDR_CONFIG(0, 3, 11, 14),
  51         DDR_CONFIG(0, 3, 11, 15),
  52         DDR_CONFIG(0, 3, 10, 16),
  53         DDR_CONFIG(0, 3, 11, 16),
  54         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  55         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  56         DDR_CONFIG(1, 3, 10, 14),
  57         DDR_CONFIG(1, 4, 10, 14),
  58         DDR_CONFIG(1, 3, 10, 15),
  59         DDR_CONFIG(1, 4, 10, 15),
  60         DDR_CONFIG(1, 3, 10, 16),
  61         DDR_CONFIG(1, 4, 10, 16),
  62         DDR_CONFIG(1, 3, 10, 17),
  63         DDR_CONFIG(1, 4, 10, 17),
  64 };
  65
  66 static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  67 {
  68         return readl(plat->iomhc + reg);
  69 }
  70
  71 static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  72 {
  73         return readl(plat->hmc + reg);
  74 }
  75
  76 static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  77                           u32 data, u32 reg)
  78 {
  79         return writel(data, plat->hmc + reg);
  80 }
  81
  82 static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  83                           u32 reg)
  84 {
  85         return writel(data, plat->ddr_sch + reg);
  86 }
  87
  88 int match_ddr_conf(u32 ddr_conf)
  89 {
  90         int i;
  91
  92         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  93                 if (ddr_conf == ddr_config[i])
  94                         return i;
  95         }
  96         return 0;
  97 }
  98
  99 static int emif_clear(struct altera_sdram_platdata *plat)
 100 {
 101         hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
 102
 103         return wait_for_bit_le32((const void *)(plat->hmc +
 104                                  RSTHANDSHAKESTAT),
 105                                  DDR_HMC_RSTHANDSHAKE_MASK,
 106                                  false, 1000, false);
 107 }
 108
 109 static int emif_reset(struct altera_sdram_platdata *plat)
 110 {
 111         u32 c2s, s2c, ret;
 112
 113         c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
 114         s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
 115
 116         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 117               c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
 118               hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
 119               hmc_readl(plat, DRAMSTS));
 120
 121         if (s2c && emif_clear(plat)) {
 122                 printf("DDR: emif_clear() failed\n");
 123                 return -1;
 124         }
 125
 126         debug("DDR: Triggerring emif reset\n");
 127         hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 128
 129         /* if seq2core[3] = 0, we are good */
 130         ret = wait_for_bit_le32((const void *)(plat->hmc +
 131                                  RSTHANDSHAKESTAT),
 132                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
 133                                  false, 1000, false);
 134         if (ret) {
 135                 printf("DDR: failed to get ack from EMIF\n");
 136                 return ret;
 137         }
 138
 139         ret = emif_clear(plat);
 140         if (ret) {
 141                 printf("DDR: emif_clear() failed\n");
 142                 return ret;
 143         }
 144
 145         debug("DDR: %s triggered successly\n", __func__);
 146         return 0;
 147 }
 148
 149 static int poll_hmc_clock_status(void)
 150 {
 151         return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
 152                                  SYSMGR_SOC64_HMC_CLK),
 153                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 154 }
 155
 156 static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
 157 {
 158         phys_size_t i;
 159
 160         if (addr % CONFIG_SYS_CACHELINE_SIZE) {
 161                 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
 162                        addr);
 163                 hang();
 164         }
 165
 166         if (size % CONFIG_SYS_CACHELINE_SIZE) {
 167                 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
 168                        size);
 169                 hang();
 170         }
 171
 172         /* Use DC ZVA instruction to clear memory to zeros by a cache line */
 173         for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
 174                 asm volatile("dc zva, %0"
 175                      :
 176                      : "r"(addr)
 177                      : "memory");
 178                 addr += CONFIG_SYS_CACHELINE_SIZE;
 179         }
 180 }
 181
 182 static void sdram_init_ecc_bits(bd_t *bd)
 183 {
 184         phys_size_t size, size_init;
 185         phys_addr_t start_addr;
 186         int bank = 0;
 187         unsigned int start = get_timer(0);
 188
 189         icache_enable();
 190
 191         start_addr = bd->bi_dram[0].start;
 192         size = bd->bi_dram[0].size;
 193
 194         /* Initialize small block for page table */
 195         memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
 196         gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
 197         gd->arch.tlb_size = PGTABLE_SIZE;
 198         start_addr += PGTABLE_SIZE + PGTABLE_OFF;
 199         size -= (PGTABLE_OFF + PGTABLE_SIZE);
 200         dcache_enable();
 201
 202         while (1) {
 203                 while (size) {
 204                         size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
 205                         sdram_clear_mem(start_addr, size_init);
 206                         size -= size_init;
 207                         start_addr += size_init;
 208                         WATCHDOG_RESET();
 209                 }
 210
 211                 bank++;
 212                 if (bank >= CONFIG_NR_DRAM_BANKS)
 213                         break;
 214
 215                 start_addr = bd->bi_dram[bank].start;
 216                 size = bd->bi_dram[bank].size;
 217         }
 218
 219         dcache_disable();
 220         icache_disable();
 221
 222         printf("SDRAM-ECC: Initialized success with %d ms\n",
 223                (unsigned int)get_timer(start));
 224 }
 225
 226 static void sdram_size_check(bd_t *bd)
 227 {
 228         phys_size_t total_ram_check = 0;
 229         phys_size_t ram_check = 0;
 230         phys_addr_t start = 0;
 231         int bank;
 232
 233         /* Sanity check ensure correct SDRAM size specified */
 234         debug("DDR: Running SDRAM size sanity check\n");
 235
 236         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 237                 start = bd->bi_dram[bank].start;
 238                 while (ram_check < bd->bi_dram[bank].size) {
 239                         ram_check += get_ram_size((void *)(start + ram_check),
 240                                                  (phys_size_t)SZ_1G);
 241                 }
 242                 total_ram_check += ram_check;
 243                 ram_check = 0;
 244         }
 245
 246         /* If the ram_size is 2GB smaller, we can assume the IO space is
 247          * not mapped in.  gd->ram_size is the actual size of the dram
 248          * not the accessible size.
 249          */
 250         if (total_ram_check != gd->ram_size) {
 251                 puts("DDR: SDRAM size check failed!\n");
 252                 hang();
 253         }
 254
 255         debug("DDR: SDRAM size check passed!\n");
 256 }
 257
 258 /**
 259  * sdram_calculate_size() - Calculate SDRAM size
 260  *
 261  * Calculate SDRAM device size based on SDRAM controller parameters.
 262  * Size is specified in bytes.
 263  */
 264 static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
 265 {
 266         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 267
 268         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 269                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 270                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 271                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 272                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 273
 274         size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
 275                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 276
 277         return size;
 278 }
 279
 280 /**
 281  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 282  *
 283  * Initialize the SDRAM MMR.
 284  */
 285 static int sdram_mmr_init_full(struct udevice *dev)
 286 {
 287         struct altera_sdram_platdata *plat = dev->platdata;
 288         struct altera_sdram_priv *priv = dev_get_priv(dev);
 289         u32 update_value, io48_value, ddrioctl;
 290         u32 i;
 291         int ret;
 292         phys_size_t hw_size;
 293         bd_t bd = {0};
 294
 295         /* Enable access to DDR from CPU master */
 296         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
 297                      CCU_ADBASE_DI_MASK);
 298         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
 299                      CCU_ADBASE_DI_MASK);
 300         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
 301                      CCU_ADBASE_DI_MASK);
 302         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
 303                      CCU_ADBASE_DI_MASK);
 304         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
 305                      CCU_ADBASE_DI_MASK);
 306         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
 307                      CCU_ADBASE_DI_MASK);
 308         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
 309                      CCU_ADBASE_DI_MASK);
 310
 311         /* Enable access to DDR from IO master */
 312         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
 313                      CCU_ADBASE_DI_MASK);
 314         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
 315                      CCU_ADBASE_DI_MASK);
 316         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 317                      CCU_ADBASE_DI_MASK);
 318         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 319                      CCU_ADBASE_DI_MASK);
 320         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 321                      CCU_ADBASE_DI_MASK);
 322         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 323                      CCU_ADBASE_DI_MASK);
 324
 325         /* this enables nonsecure access to DDR */
 326         /* mpuregion0addr_limit */
 327         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 328         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 329
 330         /* nonmpuregion0addr_limit */
 331         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 332                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 333         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 334
 335         /* Enable mpuregion0enable and nonmpuregion0enable */
 336         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 337                               FW_MPU_DDR_SCR_EN_SET);
 338
 339         /* Ensure HMC clock is running */
 340         if (poll_hmc_clock_status()) {
 341                 puts("DDR: Error as HMC clock not running\n");
 342                 return -1;
 343         }
 344
 345         /* Try 3 times to do a calibration */
 346         for (i = 0; i < 3; i++) {
 347                 ret = wait_for_bit_le32((const void *)(plat->hmc +
 348                                         DDRCALSTAT),
 349                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 350                                         false);
 351                 if (!ret)
 352                         break;
 353
 354                 emif_reset(plat);
 355         }
 356
 357         if (ret) {
 358                 puts("DDR: Error as SDRAM calibration failed\n");
 359                 return -1;
 360         }
 361         debug("DDR: Calibration success\n");
 362
 363         u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
 364         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 365         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 366         u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
 367         u32 caltim0 = hmc_readl(plat, CALTIMING0);
 368         u32 caltim1 = hmc_readl(plat, CALTIMING1);
 369         u32 caltim2 = hmc_readl(plat, CALTIMING2);
 370         u32 caltim3 = hmc_readl(plat, CALTIMING3);
 371         u32 caltim4 = hmc_readl(plat, CALTIMING4);
 372         u32 caltim9 = hmc_readl(plat, CALTIMING9);
 373
 374         /*
 375          * Configure the DDR IO size [0xFFCFB008]
 376          * niosreserve0: Used to indicate DDR width &
 377          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 378          *      bit[8]   = 1 if user-mode OCT is present
 379          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 380          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 381          * niosreserve1: IP ADCDS version encoded as 16 bit value
 382          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 383          *                          3=EAP, 4-6 are reserved)
 384          *      bit[5:3] = Service Pack # (e.g. 1)
 385          *      bit[9:6] = Minor Release #
 386          *      bit[14:10] = Major Release #
 387          */
 388         update_value = hmc_readl(plat, NIOSRESERVED0);
 389         hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
 390         ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
 391
 392         /* enable HPS interface to HMC */
 393         hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 394
 395         /* Set the DDR Configuration */
 396         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 397                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 398                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 399                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 400                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 401
 402         update_value = match_ddr_conf(io48_value);
 403         if (update_value)
 404                 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
 405
 406         /* Configure HMC dramaddrw */
 407         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
 408
 409         /*
 410          * Configure DDR timing
 411          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 412          *  WRTOMISS = WL + tWR + tRP + tRCD and
 413          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 414          *  First part of equation is in memory clock units so divide by 2
 415          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 416          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 417          */
 418         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 419
 420         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 421                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 422                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 423                        (burst_len >> 2);
 424         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 425                        (burst_len >> 1)) >> 1) -
 426                       /* Up to here was in memory cycles so divide by 2 */
 427                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 428                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 429                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 430
 431         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 432                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 433                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 434                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 435                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 436                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 437                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 438                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 439                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 440                         (((ddrioctl == 1) ? 1 : 0) <<
 441                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 442                         DDR_SCH_DDRTIMING);
 443
 444         /* Configure DDR mode [precharge = 0] */
 445         ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
 446                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 447                         DDR_SCH_DDRMODE);
 448
 449         /* Configure the read latency */
 450         ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 451                         DDR_READ_LATENCY_DELAY,
 452                         DDR_SCH_READ_LATENCY);
 453
 454         /*
 455          * Configuring timing values concerning activate commands
 456          * [FAWBANK alway 1 because always 4 bank DDR]
 457          */
 458         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 459                          DDR_SCH_ACTIVATE_RRD_OFF) |
 460                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 461                          DDR_SCH_ACTIVATE_FAW_OFF) |
 462                         (DDR_ACTIVATE_FAWBANK <<
 463                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 464                         DDR_SCH_ACTIVATE);
 465
 466         /*
 467          * Configuring timing values concerning device to device data bus
 468          * ownership change
 469          */
 470         ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 471                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 472                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 473                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 474                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 475                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 476                         DDR_SCH_DEVTODEV);
 477
 478         /* assigning the SDRAM size */
 479         unsigned long long size = sdram_calculate_size(plat);
 480         /* If the size is invalid, use default Config size */
 481         if (size <= 0)
 482                 hw_size = PHYS_SDRAM_1_SIZE;
 483         else
 484                 hw_size = size;
 485
 486         /* Get bank configuration from devicetree */
 487         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 488                                      (phys_size_t *)&gd->ram_size, &bd);
 489         if (ret) {
 490                 puts("DDR: Failed to decode memory node\n");
 491                 return -1;
 492         }
 493
 494         if (gd->ram_size != hw_size)
 495                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 496
 497         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 498
 499         /* Enable or disable the SDRAM ECC */
 500         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 501                 setbits_le32(plat->hmc + ECCCTRL1,
 502                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 503                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 504                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 505                 clrbits_le32(plat->hmc + ECCCTRL1,
 506                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 507                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 508                 setbits_le32(plat->hmc + ECCCTRL2,
 509                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 510                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 511                 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 512
 513                 /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
 514                 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 515
 516                 /* Initialize memory content if not from warm reset */
 517                 if (!cpu_has_been_warmreset())
 518                         sdram_init_ecc_bits(&bd);
 519         } else {
 520                 clrbits_le32(plat->hmc + ECCCTRL1,
 521                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 522                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 523                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 524                 clrbits_le32(plat->hmc + ECCCTRL2,
 525                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 526                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 527         }
 528
 529         sdram_size_check(&bd);
 530
 531         priv->info.base = bd.bi_dram[0].start;
 532         priv->info.size = gd->ram_size;
 533
 534         debug("DDR: HMC init success\n");
 535         return 0;
 536 }
 537
 538 static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
 539 {
 540         struct altera_sdram_platdata *plat = dev->platdata;
 541         fdt_addr_t addr;
 542
 543         addr = dev_read_addr_index(dev, 0);
 544         if (addr == FDT_ADDR_T_NONE)
 545                 return -EINVAL;
 546         plat->ddr_sch = (void __iomem *)addr;
 547
 548         addr = dev_read_addr_index(dev, 1);
 549         if (addr == FDT_ADDR_T_NONE)
 550                 return -EINVAL;
 551         plat->iomhc = (void __iomem *)addr;
 552
 553         addr = dev_read_addr_index(dev, 2);
 554         if (addr == FDT_ADDR_T_NONE)
 555                 return -EINVAL;
 556         plat->hmc = (void __iomem *)addr;
 557
 558         return 0;
 559 }
 560
 561 static int altera_sdram_probe(struct udevice *dev)
 562 {
 563         int ret;
 564         struct altera_sdram_priv *priv = dev_get_priv(dev);
 565
 566         ret = reset_get_bulk(dev, &priv->resets);
 567         if (ret) {
 568                 dev_err(dev, "Can't get reset: %d\n", ret);
 569                 return -ENODEV;
 570         }
 571         reset_deassert_bulk(&priv->resets);
 572
 573         if (sdram_mmr_init_full(dev) != 0) {
 574                 puts("SDRAM init failed.\n");
 575                 goto failed;
 576         }
 577
 578         return 0;
 579
 580 failed:
 581         reset_release_bulk(&priv->resets);
 582         return -ENODEV;
 583 }
 584
 585 static int altera_sdram_get_info(struct udevice *dev,
 586                                  struct ram_info *info)
 587 {
 588         struct altera_sdram_priv *priv = dev_get_priv(dev);
 589
 590         info->base = priv->info.base;
 591         info->size = priv->info.size;
 592
 593         return 0;
 594 }
 595
 596 static struct ram_ops altera_sdram_ops = {
 597         .get_info = altera_sdram_get_info,
 598 };
 599
 600 static const struct udevice_id altera_sdram_ids[] = {
 601         { .compatible = "altr,sdr-ctl-s10" },
 602         { /* sentinel */ }
 603 };
 604
 605 U_BOOT_DRIVER(altera_sdram) = {
 606         .name = "altr_sdr_ctl",
 607         .id = UCLASS_RAM,
 608         .of_match = altera_sdram_ids,
 609         .ops = &altera_sdram_ops,
 610         .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
 611         .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
 612         .probe = altera_sdram_probe,
 613         .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
 614 };