drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <ram.h>
  14 #include <reset.h>
  15 #include "sdram_s10.h"
  16 #include <wait_bit.h>
  17 #include <asm/arch/firewall_s10.h>
  18 #include <asm/arch/system_manager.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22
  23 struct altera_sdram_priv {
  24         struct ram_info info;
  25         struct reset_ctl_bulk resets;
  26 };
  27
  28 struct altera_sdram_platdata {
  29         void __iomem *hmc;
  30         void __iomem *ddr_sch;
  31         void __iomem *iomhc;
  32 };
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 static const struct socfpga_system_manager *sysmgr_regs =
  37                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  38
  39 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  40
  41 #define PGTABLE_OFF     0x4000
  42
  43 /* The followring are the supported configurations */
  44 u32 ddr_config[] = {
  45         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  46         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  47         DDR_CONFIG(0, 3, 10, 12),
  48         DDR_CONFIG(0, 3,  9, 13),
  49         DDR_CONFIG(0, 3, 10, 13),
  50         DDR_CONFIG(0, 3,  9, 14),
  51         DDR_CONFIG(0, 3, 10, 14),
  52         DDR_CONFIG(0, 3, 10, 15),
  53         DDR_CONFIG(0, 3, 11, 14),
  54         DDR_CONFIG(0, 3, 11, 15),
  55         DDR_CONFIG(0, 3, 10, 16),
  56         DDR_CONFIG(0, 3, 11, 16),
  57         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  58         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  59         DDR_CONFIG(1, 3, 10, 14),
  60         DDR_CONFIG(1, 4, 10, 14),
  61         DDR_CONFIG(1, 3, 10, 15),
  62         DDR_CONFIG(1, 4, 10, 15),
  63         DDR_CONFIG(1, 3, 10, 16),
  64         DDR_CONFIG(1, 4, 10, 16),
  65         DDR_CONFIG(1, 3, 10, 17),
  66         DDR_CONFIG(1, 4, 10, 17),
  67 };
  68
  69 static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg)
  70 {
  71         return readl(plat->iomhc + reg);
  72 }
  73
  74 static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg)
  75 {
  76         return readl(plat->hmc + reg);
  77 }
  78
  79 static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
  80                           u32 data, u32 reg)
  81 {
  82         return writel(data, plat->hmc + reg);
  83 }
  84
  85 static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
  86                           u32 reg)
  87 {
  88         return writel(data, plat->ddr_sch + reg);
  89 }
  90
  91 int match_ddr_conf(u32 ddr_conf)
  92 {
  93         int i;
  94
  95         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  96                 if (ddr_conf == ddr_config[i])
  97                         return i;
  98         }
  99         return 0;
 100 }
 101
 102 static int emif_clear(struct altera_sdram_platdata *plat)
 103 {
 104         hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);
 105
 106         return wait_for_bit_le32((const void *)(plat->hmc +
 107                                  RSTHANDSHAKESTAT),
 108                                  DDR_HMC_RSTHANDSHAKE_MASK,
 109                                  false, 1000, false);
 110 }
 111
 112 static int emif_reset(struct altera_sdram_platdata *plat)
 113 {
 114         u32 c2s, s2c, ret;
 115
 116         c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;
 117         s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;
 118
 119         debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 120               c2s, s2c, hmc_readl(plat, NIOSRESERVED0),
 121               hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),
 122               hmc_readl(plat, DRAMSTS));
 123
 124         if (s2c && emif_clear(plat)) {
 125                 printf("DDR: emif_clear() failed\n");
 126                 return -1;
 127         }
 128
 129         debug("DDR: Triggerring emif reset\n");
 130         hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);
 131
 132         /* if seq2core[3] = 0, we are good */
 133         ret = wait_for_bit_le32((const void *)(plat->hmc +
 134                                  RSTHANDSHAKESTAT),
 135                                  DDR_HMC_SEQ2CORE_INT_RESP_MASK,
 136                                  false, 1000, false);
 137         if (ret) {
 138                 printf("DDR: failed to get ack from EMIF\n");
 139                 return ret;
 140         }
 141
 142         ret = emif_clear(plat);
 143         if (ret) {
 144                 printf("DDR: emif_clear() failed\n");
 145                 return ret;
 146         }
 147
 148         debug("DDR: %s triggered successly\n", __func__);
 149         return 0;
 150 }
 151
 152 static int poll_hmc_clock_status(void)
 153 {
 154         return wait_for_bit_le32(&sysmgr_regs->hmc_clk,
 155                                  SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);
 156 }
 157
 158 static void sdram_clear_mem(phys_addr_t addr, phys_size_t size)
 159 {
 160         phys_size_t i;
 161
 162         if (addr % CONFIG_SYS_CACHELINE_SIZE) {
 163                 printf("DDR: address 0x%llx is not cacheline size aligned.\n",
 164                        addr);
 165                 hang();
 166         }
 167
 168         if (size % CONFIG_SYS_CACHELINE_SIZE) {
 169                 printf("DDR: size 0x%llx is not multiple of cacheline size\n",
 170                        size);
 171                 hang();
 172         }
 173
 174         /* Use DC ZVA instruction to clear memory to zeros by a cache line */
 175         for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {
 176                 asm volatile("dc zva, %0"
 177                      :
 178                      : "r"(addr)
 179                      : "memory");
 180                 addr += CONFIG_SYS_CACHELINE_SIZE;
 181         }
 182 }
 183
 184 static void sdram_init_ecc_bits(bd_t *bd)
 185 {
 186         phys_size_t size, size_init;
 187         phys_addr_t start_addr;
 188         int bank = 0;
 189         unsigned int start = get_timer(0);
 190
 191         icache_enable();
 192
 193         start_addr = bd->bi_dram[0].start;
 194         size = bd->bi_dram[0].size;
 195
 196         /* Initialize small block for page table */
 197         memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);
 198         gd->arch.tlb_addr = start_addr + PGTABLE_OFF;
 199         gd->arch.tlb_size = PGTABLE_SIZE;
 200         start_addr += PGTABLE_SIZE + PGTABLE_OFF;
 201         size -= (PGTABLE_OFF + PGTABLE_SIZE);
 202         dcache_enable();
 203
 204         while (1) {
 205                 while (size) {
 206                         size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);
 207                         sdram_clear_mem(start_addr, size_init);
 208                         size -= size_init;
 209                         start_addr += size_init;
 210                         WATCHDOG_RESET();
 211                 }
 212
 213                 bank++;
 214                 if (bank >= CONFIG_NR_DRAM_BANKS)
 215                         break;
 216
 217                 start_addr = bd->bi_dram[bank].start;
 218                 size = bd->bi_dram[bank].size;
 219         }
 220
 221         dcache_disable();
 222         icache_disable();
 223
 224         printf("SDRAM-ECC: Initialized success with %d ms\n",
 225                (unsigned int)get_timer(start));
 226 }
 227
 228 static void sdram_size_check(bd_t *bd)
 229 {
 230         phys_size_t total_ram_check = 0;
 231         phys_size_t ram_check = 0;
 232         phys_addr_t start = 0;
 233         int bank;
 234
 235         /* Sanity check ensure correct SDRAM size specified */
 236         debug("DDR: Running SDRAM size sanity check\n");
 237
 238         for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
 239                 start = bd->bi_dram[bank].start;
 240                 while (ram_check < bd->bi_dram[bank].size) {
 241                         ram_check += get_ram_size((void *)(start + ram_check),
 242                                                  (phys_size_t)SZ_1G);
 243                 }
 244                 total_ram_check += ram_check;
 245                 ram_check = 0;
 246         }
 247
 248         /* If the ram_size is 2GB smaller, we can assume the IO space is
 249          * not mapped in.  gd->ram_size is the actual size of the dram
 250          * not the accessible size.
 251          */
 252         if (total_ram_check != gd->ram_size) {
 253                 puts("DDR: SDRAM size check failed!\n");
 254                 hang();
 255         }
 256
 257         debug("DDR: SDRAM size check passed!\n");
 258 }
 259
 260 /**
 261  * sdram_calculate_size() - Calculate SDRAM size
 262  *
 263  * Calculate SDRAM device size based on SDRAM controller parameters.
 264  * Size is specified in bytes.
 265  */
 266 static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat)
 267 {
 268         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 269
 270         phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
 271                          DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
 272                          DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 273                          DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
 274                          DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));
 275
 276         size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &
 277                         DDR_HMC_DDRIOCTRL_IOSIZE_MSK));
 278
 279         return size;
 280 }
 281
 282 /**
 283  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 284  *
 285  * Initialize the SDRAM MMR.
 286  */
 287 static int sdram_mmr_init_full(struct udevice *dev)
 288 {
 289         struct altera_sdram_platdata *plat = dev->platdata;
 290         struct altera_sdram_priv *priv = dev_get_priv(dev);
 291         u32 update_value, io48_value, ddrioctl;
 292         u32 i;
 293         int ret;
 294         phys_size_t hw_size;
 295         bd_t bd = {0};
 296
 297         /* Enable access to DDR from CPU master */
 298         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
 299                      CCU_ADBASE_DI_MASK);
 300         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
 301                      CCU_ADBASE_DI_MASK);
 302         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
 303                      CCU_ADBASE_DI_MASK);
 304         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
 305                      CCU_ADBASE_DI_MASK);
 306         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
 307                      CCU_ADBASE_DI_MASK);
 308         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
 309                      CCU_ADBASE_DI_MASK);
 310         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
 311                      CCU_ADBASE_DI_MASK);
 312
 313         /* Enable access to DDR from IO master */
 314         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
 315                      CCU_ADBASE_DI_MASK);
 316         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
 317                      CCU_ADBASE_DI_MASK);
 318         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 319                      CCU_ADBASE_DI_MASK);
 320         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 321                      CCU_ADBASE_DI_MASK);
 322         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 323                      CCU_ADBASE_DI_MASK);
 324         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 325                      CCU_ADBASE_DI_MASK);
 326
 327         /* this enables nonsecure access to DDR */
 328         /* mpuregion0addr_limit */
 329         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 330         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 331
 332         /* nonmpuregion0addr_limit */
 333         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 334                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 335         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 336
 337         /* Enable mpuregion0enable and nonmpuregion0enable */
 338         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 339                               FW_MPU_DDR_SCR_EN_SET);
 340
 341         /* Ensure HMC clock is running */
 342         if (poll_hmc_clock_status()) {
 343                 puts("DDR: Error as HMC clock not running\n");
 344                 return -1;
 345         }
 346
 347         /* Try 3 times to do a calibration */
 348         for (i = 0; i < 3; i++) {
 349                 ret = wait_for_bit_le32((const void *)(plat->hmc +
 350                                         DDRCALSTAT),
 351                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 352                                         false);
 353                 if (!ret)
 354                         break;
 355
 356                 emif_reset(plat);
 357         }
 358
 359         if (ret) {
 360                 puts("DDR: Error as SDRAM calibration failed\n");
 361                 return -1;
 362         }
 363         debug("DDR: Calibration success\n");
 364
 365         u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
 366         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 367         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 368         u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
 369         u32 caltim0 = hmc_readl(plat, CALTIMING0);
 370         u32 caltim1 = hmc_readl(plat, CALTIMING1);
 371         u32 caltim2 = hmc_readl(plat, CALTIMING2);
 372         u32 caltim3 = hmc_readl(plat, CALTIMING3);
 373         u32 caltim4 = hmc_readl(plat, CALTIMING4);
 374         u32 caltim9 = hmc_readl(plat, CALTIMING9);
 375
 376         /*
 377          * Configure the DDR IO size [0xFFCFB008]
 378          * niosreserve0: Used to indicate DDR width &
 379          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 380          *      bit[8]   = 1 if user-mode OCT is present
 381          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 382          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 383          * niosreserve1: IP ADCDS version encoded as 16 bit value
 384          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 385          *                          3=EAP, 4-6 are reserved)
 386          *      bit[5:3] = Service Pack # (e.g. 1)
 387          *      bit[9:6] = Minor Release #
 388          *      bit[14:10] = Major Release #
 389          */
 390         update_value = hmc_readl(plat, NIOSRESERVED0);
 391         hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
 392         ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
 393
 394         /* enable HPS interface to HMC */
 395         hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 396
 397         /* Set the DDR Configuration */
 398         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 399                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 400                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 401                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 402                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 403
 404         update_value = match_ddr_conf(io48_value);
 405         if (update_value)
 406                 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
 407
 408         /* Configure HMC dramaddrw */
 409         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
 410
 411         /*
 412          * Configure DDR timing
 413          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 414          *  WRTOMISS = WL + tWR + tRP + tRCD and
 415          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 416          *  First part of equation is in memory clock units so divide by 2
 417          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 418          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 419          */
 420         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 421
 422         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 423                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 424                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 425                        (burst_len >> 2);
 426         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 427                        (burst_len >> 1)) >> 1) -
 428                       /* Up to here was in memory cycles so divide by 2 */
 429                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 430                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 431                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 432
 433         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 434                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 435                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 436                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 437                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 438                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 439                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 440                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 441                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 442                         (((ddrioctl == 1) ? 1 : 0) <<
 443                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 444                         DDR_SCH_DDRTIMING);
 445
 446         /* Configure DDR mode [precharge = 0] */
 447         ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
 448                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 449                         DDR_SCH_DDRMODE);
 450
 451         /* Configure the read latency */
 452         ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 453                         DDR_READ_LATENCY_DELAY,
 454                         DDR_SCH_READ_LATENCY);
 455
 456         /*
 457          * Configuring timing values concerning activate commands
 458          * [FAWBANK alway 1 because always 4 bank DDR]
 459          */
 460         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 461                          DDR_SCH_ACTIVATE_RRD_OFF) |
 462                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 463                          DDR_SCH_ACTIVATE_FAW_OFF) |
 464                         (DDR_ACTIVATE_FAWBANK <<
 465                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 466                         DDR_SCH_ACTIVATE);
 467
 468         /*
 469          * Configuring timing values concerning device to device data bus
 470          * ownership change
 471          */
 472         ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 473                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 474                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 475                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 476                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 477                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 478                         DDR_SCH_DEVTODEV);
 479
 480         /* assigning the SDRAM size */
 481         unsigned long long size = sdram_calculate_size(plat);
 482         /* If the size is invalid, use default Config size */
 483         if (size <= 0)
 484                 hw_size = PHYS_SDRAM_1_SIZE;
 485         else
 486                 hw_size = size;
 487
 488         /* Get bank configuration from devicetree */
 489         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 490                                      (phys_size_t *)&gd->ram_size, &bd);
 491         if (ret) {
 492                 puts("DDR: Failed to decode memory node\n");
 493                 return -1;
 494         }
 495
 496         if (gd->ram_size != hw_size)
 497                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 498
 499         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 500
 501         /* Enable or disable the SDRAM ECC */
 502         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 503                 setbits_le32(plat->hmc + ECCCTRL1,
 504                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 505                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 506                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 507                 clrbits_le32(plat->hmc + ECCCTRL1,
 508                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 509                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 510                 setbits_le32(plat->hmc + ECCCTRL2,
 511                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 512                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 513                 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 514
 515                 /* Enable non-secure writes to HMC Adapter for SDRAM ECC */
 516                 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 517
 518                 /* Initialize memory content if not from warm reset */
 519                 if (!cpu_has_been_warmreset())
 520                         sdram_init_ecc_bits(&bd);
 521         } else {
 522                 clrbits_le32(plat->hmc + ECCCTRL1,
 523                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 524                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 525                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 526                 clrbits_le32(plat->hmc + ECCCTRL2,
 527                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 528                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 529         }
 530
 531         sdram_size_check(&bd);
 532
 533         priv->info.base = bd.bi_dram[0].start;
 534         priv->info.size = gd->ram_size;
 535
 536         debug("DDR: HMC init success\n");
 537         return 0;
 538 }
 539
 540 static int altera_sdram_ofdata_to_platdata(struct udevice *dev)
 541 {
 542         struct altera_sdram_platdata *plat = dev->platdata;
 543         fdt_addr_t addr;
 544
 545         addr = dev_read_addr_index(dev, 0);
 546         if (addr == FDT_ADDR_T_NONE)
 547                 return -EINVAL;
 548         plat->ddr_sch = (void __iomem *)addr;
 549
 550         addr = dev_read_addr_index(dev, 1);
 551         if (addr == FDT_ADDR_T_NONE)
 552                 return -EINVAL;
 553         plat->iomhc = (void __iomem *)addr;
 554
 555         addr = dev_read_addr_index(dev, 2);
 556         if (addr == FDT_ADDR_T_NONE)
 557                 return -EINVAL;
 558         plat->hmc = (void __iomem *)addr;
 559
 560         return 0;
 561 }
 562
 563 static int altera_sdram_probe(struct udevice *dev)
 564 {
 565         int ret;
 566         struct altera_sdram_priv *priv = dev_get_priv(dev);
 567
 568         ret = reset_get_bulk(dev, &priv->resets);
 569         if (ret) {
 570                 dev_err(dev, "Can't get reset: %d\n", ret);
 571                 return -ENODEV;
 572         }
 573         reset_deassert_bulk(&priv->resets);
 574
 575         if (sdram_mmr_init_full(dev) != 0) {
 576                 puts("SDRAM init failed.\n");
 577                 goto failed;
 578         }
 579
 580         return 0;
 581
 582 failed:
 583         reset_release_bulk(&priv->resets);
 584         return -ENODEV;
 585 }
 586
 587 static int altera_sdram_get_info(struct udevice *dev,
 588                                  struct ram_info *info)
 589 {
 590         struct altera_sdram_priv *priv = dev_get_priv(dev);
 591
 592         info->base = priv->info.base;
 593         info->size = priv->info.size;
 594
 595         return 0;
 596 }
 597
 598 static struct ram_ops altera_sdram_ops = {
 599         .get_info = altera_sdram_get_info,
 600 };
 601
 602 static const struct udevice_id altera_sdram_ids[] = {
 603         { .compatible = "altr,sdr-ctl-s10" },
 604         { /* sentinel */ }
 605 };
 606
 607 U_BOOT_DRIVER(altera_sdram) = {
 608         .name = "altr_sdr_ctl",
 609         .id = UCLASS_RAM,
 610         .of_match = altera_sdram_ids,
 611         .ops = &altera_sdram_ops,
 612         .ofdata_to_platdata = altera_sdram_ofdata_to_platdata,
 613         .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),
 614         .probe = altera_sdram_probe,
 615         .priv_auto_alloc_size = sizeof(struct altera_sdram_priv),
 616 };