drivers/ddr/altera/sdram_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <cpu_func.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <div64.h>
  12 #include <fdtdec.h>
  13 #include <init.h>
  14 #include <ram.h>
  15 #include <reset.h>
  16 #include "sdram_s10.h"
  17 #include <wait_bit.h>
  18 #include <asm/arch/firewall.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/io.h>
  21 #include <linux/sizes.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 #define DDR_CONFIG(A, B, C, R)  (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  26
  27 /* The followring are the supported configurations */
  28 u32 ddr_config[] = {
  29         /* DDR_CONFIG(Address order,Bank,Column,Row) */
  30         /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
  31         DDR_CONFIG(0, 3, 10, 12),
  32         DDR_CONFIG(0, 3,  9, 13),
  33         DDR_CONFIG(0, 3, 10, 13),
  34         DDR_CONFIG(0, 3,  9, 14),
  35         DDR_CONFIG(0, 3, 10, 14),
  36         DDR_CONFIG(0, 3, 10, 15),
  37         DDR_CONFIG(0, 3, 11, 14),
  38         DDR_CONFIG(0, 3, 11, 15),
  39         DDR_CONFIG(0, 3, 10, 16),
  40         DDR_CONFIG(0, 3, 11, 16),
  41         DDR_CONFIG(0, 3, 12, 15),       /* 0xa */
  42         /* List for DDR4 only (pinout order > chip, bank, row, column) */
  43         DDR_CONFIG(1, 3, 10, 14),
  44         DDR_CONFIG(1, 4, 10, 14),
  45         DDR_CONFIG(1, 3, 10, 15),
  46         DDR_CONFIG(1, 4, 10, 15),
  47         DDR_CONFIG(1, 3, 10, 16),
  48         DDR_CONFIG(1, 4, 10, 16),
  49         DDR_CONFIG(1, 3, 10, 17),
  50         DDR_CONFIG(1, 4, 10, 17),
  51 };
  52
  53 int match_ddr_conf(u32 ddr_conf)
  54 {
  55         int i;
  56
  57         for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
  58                 if (ddr_conf == ddr_config[i])
  59                         return i;
  60         }
  61         return 0;
  62 }
  63
  64 /**
  65  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
  66  *
  67  * Initialize the SDRAM MMR.
  68  */
  69 int sdram_mmr_init_full(struct udevice *dev)
  70 {
  71         struct altera_sdram_platdata *plat = dev->platdata;
  72         struct altera_sdram_priv *priv = dev_get_priv(dev);
  73         u32 update_value, io48_value, ddrioctl;
  74         u32 i;
  75         int ret;
  76         phys_size_t hw_size;
  77         bd_t bd = {0};
  78
  79         /* Enable access to DDR from CPU master */
  80         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
  81                      CCU_ADBASE_DI_MASK);
  82         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
  83                      CCU_ADBASE_DI_MASK);
  84         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
  85                      CCU_ADBASE_DI_MASK);
  86         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
  87                      CCU_ADBASE_DI_MASK);
  88         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
  89                      CCU_ADBASE_DI_MASK);
  90         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
  91                      CCU_ADBASE_DI_MASK);
  92         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
  93                      CCU_ADBASE_DI_MASK);
  94
  95         /* Enable access to DDR from IO master */
  96         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
  97                      CCU_ADBASE_DI_MASK);
  98         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
  99                      CCU_ADBASE_DI_MASK);
 100         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
 101                      CCU_ADBASE_DI_MASK);
 102         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
 103                      CCU_ADBASE_DI_MASK);
 104         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
 105                      CCU_ADBASE_DI_MASK);
 106         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
 107                      CCU_ADBASE_DI_MASK);
 108
 109         /* Enable access to DDR from TCU */
 110         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
 111                      CCU_ADBASE_DI_MASK);
 112         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
 113                      CCU_ADBASE_DI_MASK);
 114         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
 115                      CCU_ADBASE_DI_MASK);
 116         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
 117                      CCU_ADBASE_DI_MASK);
 118         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
 119                      CCU_ADBASE_DI_MASK);
 120         clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
 121                      CCU_ADBASE_DI_MASK);
 122
 123         /* this enables nonsecure access to DDR */
 124         /* mpuregion0addr_limit */
 125         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
 126         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
 127
 128         /* nonmpuregion0addr_limit */
 129         FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
 130                               FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
 131         FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
 132
 133         /* Enable mpuregion0enable and nonmpuregion0enable */
 134         FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
 135                               FW_MPU_DDR_SCR_EN_SET);
 136
 137         /* Ensure HMC clock is running */
 138         if (poll_hmc_clock_status()) {
 139                 puts("DDR: Error as HMC clock not running\n");
 140                 return -1;
 141         }
 142
 143         /* Try 3 times to do a calibration */
 144         for (i = 0; i < 3; i++) {
 145                 ret = wait_for_bit_le32((const void *)(plat->hmc +
 146                                         DDRCALSTAT),
 147                                         DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
 148                                         false);
 149                 if (!ret)
 150                         break;
 151
 152                 emif_reset(plat);
 153         }
 154
 155         if (ret) {
 156                 puts("DDR: Error as SDRAM calibration failed\n");
 157                 return -1;
 158         }
 159         debug("DDR: Calibration success\n");
 160
 161         u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
 162         u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
 163         u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
 164         u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
 165         u32 caltim0 = hmc_readl(plat, CALTIMING0);
 166         u32 caltim1 = hmc_readl(plat, CALTIMING1);
 167         u32 caltim2 = hmc_readl(plat, CALTIMING2);
 168         u32 caltim3 = hmc_readl(plat, CALTIMING3);
 169         u32 caltim4 = hmc_readl(plat, CALTIMING4);
 170         u32 caltim9 = hmc_readl(plat, CALTIMING9);
 171
 172         /*
 173          * Configure the DDR IO size [0xFFCFB008]
 174          * niosreserve0: Used to indicate DDR width &
 175          *      bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
 176          *      bit[8]   = 1 if user-mode OCT is present
 177          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 178          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 179          * niosreserve1: IP ADCDS version encoded as 16 bit value
 180          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 181          *                          3=EAP, 4-6 are reserved)
 182          *      bit[5:3] = Service Pack # (e.g. 1)
 183          *      bit[9:6] = Minor Release #
 184          *      bit[14:10] = Major Release #
 185          */
 186         update_value = hmc_readl(plat, NIOSRESERVED0);
 187         hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
 188         ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
 189
 190         /* enable HPS interface to HMC */
 191         hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
 192
 193         /* Set the DDR Configuration */
 194         io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
 195                                 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
 196                                  DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
 197                                 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
 198                                 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
 199
 200         update_value = match_ddr_conf(io48_value);
 201         if (update_value)
 202                 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
 203
 204         /* Configure HMC dramaddrw */
 205         hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
 206
 207         /*
 208          * Configure DDR timing
 209          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 210          *  WRTOMISS = WL + tWR + tRP + tRCD and
 211          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 212          *  First part of equation is in memory clock units so divide by 2
 213          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 214          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 215          */
 216         u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
 217
 218         update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
 219                        CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
 220                        CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
 221                        (burst_len >> 2);
 222         io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
 223                        (burst_len >> 1)) >> 1) -
 224                       /* Up to here was in memory cycles so divide by 2 */
 225                       CALTIMING1_CFG_RD_TO_WR(caltim1) +
 226                       CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
 227                       CALTIMING4_CFG_PCH_TO_VALID(caltim4));
 228
 229         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
 230                          DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
 231                         (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
 232                         (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
 233                         ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
 234                         (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
 235                          DDR_SCH_DDRTIMING_RDTOWR_OFF) |
 236                         (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
 237                          DDR_SCH_DDRTIMING_WRTORD_OFF) |
 238                         (((ddrioctl == 1) ? 1 : 0) <<
 239                          DDR_SCH_DDRTIMING_BWRATIO_OFF)),
 240                         DDR_SCH_DDRTIMING);
 241
 242         /* Configure DDR mode [precharge = 0] */
 243         ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
 244                          DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
 245                         DDR_SCH_DDRMODE);
 246
 247         /* Configure the read latency */
 248         ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
 249                         DDR_READ_LATENCY_DELAY,
 250                         DDR_SCH_READ_LATENCY);
 251
 252         /*
 253          * Configuring timing values concerning activate commands
 254          * [FAWBANK alway 1 because always 4 bank DDR]
 255          */
 256         ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
 257                          DDR_SCH_ACTIVATE_RRD_OFF) |
 258                         (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
 259                          DDR_SCH_ACTIVATE_FAW_OFF) |
 260                         (DDR_ACTIVATE_FAWBANK <<
 261                          DDR_SCH_ACTIVATE_FAWBANK_OFF)),
 262                         DDR_SCH_ACTIVATE);
 263
 264         /*
 265          * Configuring timing values concerning device to device data bus
 266          * ownership change
 267          */
 268         ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
 269                          DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
 270                         (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
 271                          DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
 272                         (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
 273                          DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
 274                         DDR_SCH_DEVTODEV);
 275
 276         /* assigning the SDRAM size */
 277         unsigned long long size = sdram_calculate_size(plat);
 278         /* If the size is invalid, use default Config size */
 279         if (size <= 0)
 280                 hw_size = PHYS_SDRAM_1_SIZE;
 281         else
 282                 hw_size = size;
 283
 284         /* Get bank configuration from devicetree */
 285         ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
 286                                      (phys_size_t *)&gd->ram_size, &bd);
 287         if (ret) {
 288                 puts("DDR: Failed to decode memory node\n");
 289                 return -1;
 290         }
 291
 292         if (gd->ram_size != hw_size)
 293                 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
 294
 295         printf("DDR: %lld MiB\n", gd->ram_size >> 20);
 296
 297         /* Enable or disable the SDRAM ECC */
 298         if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
 299                 setbits_le32(plat->hmc + ECCCTRL1,
 300                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 301                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 302                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 303                 clrbits_le32(plat->hmc + ECCCTRL1,
 304                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 305                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
 306                 setbits_le32(plat->hmc + ECCCTRL2,
 307                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 308                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 309                 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
 310
 311                 /* Initialize memory content if not from warm reset */
 312                 if (!cpu_has_been_warmreset())
 313                         sdram_init_ecc_bits(&bd);
 314         } else {
 315                 clrbits_le32(plat->hmc + ECCCTRL1,
 316                              (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
 317                               DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
 318                               DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
 319                 clrbits_le32(plat->hmc + ECCCTRL2,
 320                              (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
 321                               DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
 322         }
 323
 324         /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
 325         writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
 326
 327         sdram_size_check(&bd);
 328
 329         priv->info.base = bd.bi_dram[0].start;
 330         priv->info.size = gd->ram_size;
 331
 332         debug("DDR: HMC init success\n");
 333         return 0;
 334 }
 335