1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
17 #include "sdram_s10.h"
19 #include <asm/arch/firewall.h>
20 #include <asm/arch/reset_manager.h>
22 #include <linux/sizes.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
28 /* The followring are the supported configurations */
30 /* DDR_CONFIG(Address order,Bank,Column,Row) */
31 /* List for DDR3 or LPDDR3 (pinout order > chip, row, bank, column) */
32 DDR_CONFIG(0, 3, 10, 12),
33 DDR_CONFIG(0, 3, 9, 13),
34 DDR_CONFIG(0, 3, 10, 13),
35 DDR_CONFIG(0, 3, 9, 14),
36 DDR_CONFIG(0, 3, 10, 14),
37 DDR_CONFIG(0, 3, 10, 15),
38 DDR_CONFIG(0, 3, 11, 14),
39 DDR_CONFIG(0, 3, 11, 15),
40 DDR_CONFIG(0, 3, 10, 16),
41 DDR_CONFIG(0, 3, 11, 16),
42 DDR_CONFIG(0, 3, 12, 15), /* 0xa */
43 /* List for DDR4 only (pinout order > chip, bank, row, column) */
44 DDR_CONFIG(1, 3, 10, 14),
45 DDR_CONFIG(1, 4, 10, 14),
46 DDR_CONFIG(1, 3, 10, 15),
47 DDR_CONFIG(1, 4, 10, 15),
48 DDR_CONFIG(1, 3, 10, 16),
49 DDR_CONFIG(1, 4, 10, 16),
50 DDR_CONFIG(1, 3, 10, 17),
51 DDR_CONFIG(1, 4, 10, 17),
54 int match_ddr_conf(u32 ddr_conf)
58 for (i = 0; i < ARRAY_SIZE(ddr_config); i++) {
59 if (ddr_conf == ddr_config[i])
66 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
68 * Initialize the SDRAM MMR.
70 int sdram_mmr_init_full(struct udevice *dev)
72 struct altera_sdram_platdata *plat = dev->platdata;
73 struct altera_sdram_priv *priv = dev_get_priv(dev);
74 u32 update_value, io48_value, ddrioctl;
80 /* Enable access to DDR from CPU master */
81 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_DDRREG),
83 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE0),
85 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1A),
87 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1B),
89 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1C),
91 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1D),
93 clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADBASE_MEMSPACE1E),
96 /* Enable access to DDR from IO master */
97 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE0),
99 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1A),
101 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1B),
103 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1C),
105 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1D),
107 clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADBASE_MEMSPACE1E),
110 /* Enable access to DDR from TCU */
111 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE0),
113 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1A),
115 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1B),
117 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1C),
119 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1D),
121 clrbits_le32(CCU_REG_ADDR(CCU_TCU_MPRT_ADBASE_MEMSPACE1E),
124 /* this enables nonsecure access to DDR */
125 /* mpuregion0addr_limit */
126 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);
127 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);
129 /* nonmpuregion0addr_limit */
130 FW_MPU_DDR_SCR_WRITEL(0xFFFF0000,
131 FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);
132 FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT);
134 /* Enable mpuregion0enable and nonmpuregion0enable */
135 FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,
136 FW_MPU_DDR_SCR_EN_SET);
138 /* Ensure HMC clock is running */
139 if (poll_hmc_clock_status()) {
140 puts("DDR: Error as HMC clock not running\n");
144 /* Try 3 times to do a calibration */
145 for (i = 0; i < 3; i++) {
146 ret = wait_for_bit_le32((const void *)(plat->hmc +
148 DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,
157 puts("DDR: Error as SDRAM calibration failed\n");
160 debug("DDR: Calibration success\n");
162 u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0);
163 u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);
164 u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
165 u32 dramtim0 = hmc_readl(plat, DRAMTIMING0);
166 u32 caltim0 = hmc_readl(plat, CALTIMING0);
167 u32 caltim1 = hmc_readl(plat, CALTIMING1);
168 u32 caltim2 = hmc_readl(plat, CALTIMING2);
169 u32 caltim3 = hmc_readl(plat, CALTIMING3);
170 u32 caltim4 = hmc_readl(plat, CALTIMING4);
171 u32 caltim9 = hmc_readl(plat, CALTIMING9);
174 * Configure the DDR IO size [0xFFCFB008]
175 * niosreserve0: Used to indicate DDR width &
176 * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)
177 * bit[8] = 1 if user-mode OCT is present
178 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
179 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
180 * niosreserve1: IP ADCDS version encoded as 16 bit value
181 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
182 * 3=EAP, 4-6 are reserved)
183 * bit[5:3] = Service Pack # (e.g. 1)
184 * bit[9:6] = Minor Release #
185 * bit[14:10] = Major Release #
187 update_value = hmc_readl(plat, NIOSRESERVED0);
188 hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL);
189 ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL);
191 /* enable HPS interface to HMC */
192 hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL);
194 /* Set the DDR Configuration */
195 io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1),
196 (DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
197 DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw)),
198 DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw),
199 DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw));
201 update_value = match_ddr_conf(io48_value);
203 ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF);
205 /* Configure HMC dramaddrw */
206 hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);
209 * Configure DDR timing
210 * RDTOMISS = tRTP + tRP + tRCD - BL/2
211 * WRTOMISS = WL + tWR + tRP + tRCD and
212 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
213 * First part of equation is in memory clock units so divide by 2
214 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
215 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
217 u32 burst_len = CTRLCFG0_CFG_CTRL_BURST_LEN(ctrlcfg0);
219 update_value = CALTIMING2_CFG_RD_TO_WR_PCH(caltim2) +
220 CALTIMING4_CFG_PCH_TO_VALID(caltim4) +
221 CALTIMING0_CFG_ACT_TO_RDWR(caltim0) -
223 io48_value = (((DRAMTIMING0_CFG_TCL(dramtim0) + 2 + DDR_TWR +
224 (burst_len >> 1)) >> 1) -
225 /* Up to here was in memory cycles so divide by 2 */
226 CALTIMING1_CFG_RD_TO_WR(caltim1) +
227 CALTIMING0_CFG_ACT_TO_RDWR(caltim0) +
228 CALTIMING4_CFG_PCH_TO_VALID(caltim4));
230 ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) <<
231 DDR_SCH_DDRTIMING_ACTTOACT_OFF) |
232 (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) |
233 (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) |
234 ((burst_len >> 2) << DDR_SCH_DDRTIMING_BURSTLEN_OFF) |
235 (CALTIMING1_CFG_RD_TO_WR(caltim1) <<
236 DDR_SCH_DDRTIMING_RDTOWR_OFF) |
237 (CALTIMING3_CFG_WR_TO_RD(caltim3) <<
238 DDR_SCH_DDRTIMING_WRTORD_OFF) |
239 (((ddrioctl == 1) ? 1 : 0) <<
240 DDR_SCH_DDRTIMING_BWRATIO_OFF)),
243 /* Configure DDR mode [precharge = 0] */
244 ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) <<
245 DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF),
248 /* Configure the read latency */
249 ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) +
250 DDR_READ_LATENCY_DELAY,
251 DDR_SCH_READ_LATENCY);
254 * Configuring timing values concerning activate commands
255 * [FAWBANK alway 1 because always 4 bank DDR]
257 ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) <<
258 DDR_SCH_ACTIVATE_RRD_OFF) |
259 (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) <<
260 DDR_SCH_ACTIVATE_FAW_OFF) |
261 (DDR_ACTIVATE_FAWBANK <<
262 DDR_SCH_ACTIVATE_FAWBANK_OFF)),
266 * Configuring timing values concerning device to device data bus
269 ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) <<
270 DDR_SCH_DEVTODEV_BUSRDTORD_OFF) |
271 (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) <<
272 DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) |
273 (CALTIMING3_CFG_WR_TO_RD_DC(caltim3) <<
274 DDR_SCH_DEVTODEV_BUSWRTORD_OFF)),
277 /* assigning the SDRAM size */
278 unsigned long long size = sdram_calculate_size(plat);
279 /* If the size is invalid, use default Config size */
281 hw_size = PHYS_SDRAM_1_SIZE;
285 /* Get bank configuration from devicetree */
286 ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
287 (phys_size_t *)&gd->ram_size, &bd);
289 puts("DDR: Failed to decode memory node\n");
293 if (gd->ram_size != hw_size)
294 printf("DDR: Warning: DRAM size from device tree mismatch with hardware.\n");
296 printf("DDR: %lld MiB\n", gd->ram_size >> 20);
298 /* Enable or disable the SDRAM ECC */
299 if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {
300 setbits_le32(plat->hmc + ECCCTRL1,
301 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
302 DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
303 DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
304 clrbits_le32(plat->hmc + ECCCTRL1,
305 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
306 DDR_HMC_ECCCTL_CNT_RST_SET_MSK));
307 setbits_le32(plat->hmc + ECCCTRL2,
308 (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
309 DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
310 hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS);
312 /* Initialize memory content if not from warm reset */
313 if (!cpu_has_been_warmreset())
314 sdram_init_ecc_bits(&bd);
316 clrbits_le32(plat->hmc + ECCCTRL1,
317 (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |
318 DDR_HMC_ECCCTL_CNT_RST_SET_MSK |
319 DDR_HMC_ECCCTL_ECC_EN_SET_MSK));
320 clrbits_le32(plat->hmc + ECCCTRL2,
321 (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |
322 DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));
325 /* Enable non-secure reads/writes to HMC Adapter for SDRAM ECC */
326 writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);
328 sdram_size_check(&bd);
330 priv->info.base = bd.bi_dram[0].start;
331 priv->info.size = gd->ram_size;
333 debug("DDR: HMC init success\n");