1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright Altera Corporation (C) 2014-2015
12 #include <asm/arch/fpga_manager.h>
13 #include <asm/arch/reset_manager.h>
14 #include <asm/arch/sdram.h>
15 #include <asm/arch/system_manager.h>
18 #include "sequencer.h"
20 #ifdef CONFIG_SPL_BUILD
22 struct altera_gen5_sdram_priv {
26 struct altera_gen5_sdram_platdata {
27 struct socfpga_sdr *sdr;
30 struct sdram_prot_rule {
31 u32 sdram_start; /* SDRAM start address */
32 u32 sdram_end; /* SDRAM end address */
33 u32 rule; /* SDRAM protection rule number: 0-19 */
34 int valid; /* Rule valid or not? 1 - valid, 0 not*/
43 static struct socfpga_system_manager *sysmgr_regs =
44 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
46 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl);
49 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
50 * @cfg: SDRAM controller configuration data
52 * SDRAM Failure happens when accessing non-existent memory. Artificially
53 * increase the number of rows so that the memory controller thinks it has
54 * 4GB of RAM. This function returns such amount of rows.
56 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
58 /* Define constant for 4G memory - used for SDRAM errata workaround */
59 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
60 const unsigned long long memsize = MEMSIZE_4G;
61 const unsigned int cs =
62 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
63 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
64 const unsigned int rows =
65 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
66 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
67 const unsigned int banks =
68 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
69 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
70 const unsigned int cols =
71 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
72 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
73 const unsigned int width = 8;
75 unsigned long long newrows;
76 int bits, inewrowslog2;
78 debug("workaround rows - memsize %lld\n", memsize);
79 debug("workaround rows - cs %d\n", cs);
80 debug("workaround rows - width %d\n", width);
81 debug("workaround rows - rows %d\n", rows);
82 debug("workaround rows - banks %d\n", banks);
83 debug("workaround rows - cols %d\n", cols);
85 newrows = lldiv(memsize, cs * (width / 8));
86 debug("rows workaround - term1 %lld\n", newrows);
88 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
89 debug("rows workaround - term2 %lld\n", newrows);
92 * Compute the hamming weight - same as number of bits set.
93 * Need to see if result is ordinal power of 2 before
94 * attempting log2 of result.
96 bits = generic_hweight32(newrows);
98 debug("rows workaround - bits %d\n", bits);
101 printf("SDRAM workaround failed, bits set %d\n", bits);
105 if (newrows > UINT_MAX) {
106 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
110 inewrowslog2 = __ilog2(newrows);
112 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
114 if (inewrowslog2 == -1) {
115 printf("SDRAM workaround failed, newrows %lld\n", newrows);
122 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
123 static void sdram_set_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
124 struct sdram_prot_rule *prule)
128 int ruleno = prule->rule;
130 /* Select the rule */
131 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
133 /* Obtain the address bits */
134 lo_addr_bits = prule->sdram_start >> 20ULL;
135 hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
137 debug("sdram set rule start %x, %d\n", lo_addr_bits,
139 debug("sdram set rule end %x, %d\n", hi_addr_bits,
142 /* Set rule addresses */
143 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
145 /* Set rule protection ids */
146 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
147 &sdr_ctrl->prot_rule_id);
149 /* Set the rule data */
150 writel(prule->security | (prule->valid << 2) |
151 (prule->portmask << 3) | (prule->result << 13),
152 &sdr_ctrl->prot_rule_data);
155 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
157 /* Set rule number to 0 by default */
158 writel(0, &sdr_ctrl->prot_rule_rdwr);
161 static void sdram_get_rule(struct socfpga_sdr_ctrl *sdr_ctrl,
162 struct sdram_prot_rule *prule)
167 int ruleno = prule->rule;
170 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
171 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
173 /* Get the addresses */
174 addr = readl(&sdr_ctrl->prot_rule_addr);
175 prule->sdram_start = (addr & 0xFFF) << 20;
176 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
178 /* Get the configured protection IDs */
179 id = readl(&sdr_ctrl->prot_rule_id);
180 prule->lo_prot_id = id & 0xFFF;
181 prule->hi_prot_id = (id >> 12) & 0xFFF;
183 /* Get protection data */
184 data = readl(&sdr_ctrl->prot_rule_data);
186 prule->security = data & 0x3;
187 prule->valid = (data >> 2) & 0x1;
188 prule->portmask = (data >> 3) & 0x3FF;
189 prule->result = (data >> 13) & 0x1;
193 sdram_set_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl,
194 const u32 sdram_start, const u32 sdram_end)
196 struct sdram_prot_rule rule;
199 /* Start with accepting all SDRAM transaction */
200 writel(0x0, &sdr_ctrl->protport_default);
202 /* Clear all protection rules for warm boot case */
203 memset(&rule, 0, sizeof(rule));
205 for (rules = 0; rules < 20; rules++) {
207 sdram_set_rule(sdr_ctrl, &rule);
210 /* new rule: accept SDRAM */
211 rule.sdram_start = sdram_start;
212 rule.sdram_end = sdram_end;
213 rule.lo_prot_id = 0x0;
214 rule.hi_prot_id = 0xFFF;
215 rule.portmask = 0x3FF;
222 sdram_set_rule(sdr_ctrl, &rule);
224 /* default rule: reject everything */
225 writel(0x3ff, &sdr_ctrl->protport_default);
228 static void sdram_dump_protection_config(struct socfpga_sdr_ctrl *sdr_ctrl)
230 struct sdram_prot_rule rule;
233 debug("SDRAM Prot rule, default %x\n",
234 readl(&sdr_ctrl->protport_default));
236 for (rules = 0; rules < 20; rules++) {
238 sdram_get_rule(sdr_ctrl, &rule);
239 debug("Rule %d, rules ...\n", rules);
240 debug(" sdram start %x\n", rule.sdram_start);
241 debug(" sdram end %x\n", rule.sdram_end);
242 debug(" low prot id %d, hi prot id %d\n",
245 debug(" portmask %x\n", rule.portmask);
246 debug(" security %d\n", rule.security);
247 debug(" result %d\n", rule.result);
248 debug(" valid %d\n", rule.valid);
253 * sdram_write_verify() - write to register and verify the write.
254 * @addr: Register address
255 * @val: Value to be written and verified
257 * This function writes to a register, reads back the value and compares
258 * the result with the written value to check if the data match.
260 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
264 debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
267 debug(" Read and verify...");
270 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
280 * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
281 * @cfg: SDRAM controller configuration data
283 * Return the value of DRAM CTRLCFG register.
285 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
288 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
289 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
291 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
292 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
294 u32 ctrl_cfg = cfg->ctrl_cfg;
297 * SDRAM Failure When Accessing Non-Existent Memory
298 * Set the addrorder field of the SDRAM control register
299 * based on the CSBITs setting.
303 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
305 } else if (csbits == 2) {
307 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
311 ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
312 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
318 * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
319 * @cfg: SDRAM controller configuration data
321 * Return the value of DRAM ADDRW register.
323 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
326 * SDRAM Failure When Accessing Non-Existent Memory
327 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
328 * log2(number of chip select bits). Since there's only
329 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
330 * which is the same as "chip selects" - 1.
332 const int rows = get_errata_rows(cfg);
333 u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
335 return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
339 * sdr_load_regs() - Load SDRAM controller registers
340 * @cfg: SDRAM controller configuration data
342 * This function loads the register values into the SDRAM controller block.
344 static void sdr_load_regs(struct socfpga_sdr_ctrl *sdr_ctrl,
345 const struct socfpga_sdram_config *cfg)
347 const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
348 const u32 dram_addrw = sdr_get_addr_rw(cfg);
350 debug("\nConfiguring CTRLCFG\n");
351 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
353 debug("Configuring DRAMTIMING1\n");
354 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
356 debug("Configuring DRAMTIMING2\n");
357 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
359 debug("Configuring DRAMTIMING3\n");
360 writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
362 debug("Configuring DRAMTIMING4\n");
363 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
365 debug("Configuring LOWPWRTIMING\n");
366 writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
368 debug("Configuring DRAMADDRW\n");
369 writel(dram_addrw, &sdr_ctrl->dram_addrw);
371 debug("Configuring DRAMIFWIDTH\n");
372 writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
374 debug("Configuring DRAMDEVWIDTH\n");
375 writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
377 debug("Configuring LOWPWREQ\n");
378 writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
380 debug("Configuring DRAMINTR\n");
381 writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
383 debug("Configuring STATICCFG\n");
384 writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
386 debug("Configuring CTRLWIDTH\n");
387 writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
389 debug("Configuring PORTCFG\n");
390 writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
392 debug("Configuring FIFOCFG\n");
393 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
395 debug("Configuring MPPRIORITY\n");
396 writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
398 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
399 writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
400 writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
401 writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
402 writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
404 debug("Configuring MPPACING_MPPACING_0\n");
405 writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
406 writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
407 writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
408 writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
410 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
411 writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
412 writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
413 writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
415 debug("Configuring PHYCTRL_PHYCTRL_0\n");
416 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
418 debug("Configuring CPORTWIDTH\n");
419 writel(cfg->cport_width, &sdr_ctrl->cport_width);
421 debug("Configuring CPORTWMAP\n");
422 writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
424 debug("Configuring CPORTRMAP\n");
425 writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
427 debug("Configuring RFIFOCMAP\n");
428 writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
430 debug("Configuring WFIFOCMAP\n");
431 writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
433 debug("Configuring CPORTRDWR\n");
434 writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
436 debug("Configuring DRAMODT\n");
437 writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
439 debug("Configuring EXTRATIME1\n");
440 writel(cfg->extratime1, &sdr_ctrl->extratime1);
444 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
445 * @sdr_phy_reg: Value of the PHY control register 0
447 * Initialize the SDRAM MMR.
449 int sdram_mmr_init_full(struct socfpga_sdr_ctrl *sdr_ctrl,
450 unsigned int sdr_phy_reg)
452 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
453 const unsigned int rows =
454 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
455 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
458 writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
460 sdr_load_regs(sdr_ctrl, cfg);
462 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
463 writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
465 /* only enable if the FPGA is programmed */
466 if (fpgamgr_test_fpga_ready()) {
467 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
473 /* Restore the SDR PHY Register if valid */
474 if (sdr_phy_reg != 0xffffffff)
475 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
477 /* Final step - apply configuration changes */
478 debug("Configuring STATICCFG\n");
479 clrsetbits_le32(&sdr_ctrl->static_cfg,
480 SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
481 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
483 sdram_set_protection_config(sdr_ctrl, 0,
484 sdram_calculate_size(sdr_ctrl) - 1);
486 sdram_dump_protection_config(sdr_ctrl);
492 * sdram_calculate_size() - Calculate SDRAM size
494 * Calculate SDRAM device size based on SDRAM controller parameters.
495 * Size is specified in bytes.
497 static unsigned long sdram_calculate_size(struct socfpga_sdr_ctrl *sdr_ctrl)
500 unsigned long row, bank, col, cs, width;
501 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
502 const unsigned int csbits =
503 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
504 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
505 const unsigned int rowbits =
506 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
507 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
509 temp = readl(&sdr_ctrl->dram_addrw);
510 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
511 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
514 * SDRAM Failure When Accessing Non-Existent Memory
515 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
516 * since the FB specifies we modify ROWBITs to work around SDRAM
519 row = readl(&sysmgr_regs->iswgrp_handoff[4]);
523 * If the stored handoff value for rows is greater than
524 * the field width in the sdr.dramaddrw register then
525 * something is very wrong. Revert to using the the #define
526 * value handed off by the SOCEDS tool chain instead of
527 * using a broken value.
532 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
533 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
536 * SDRAM Failure When Accessing Non-Existent Memory
537 * Use CSBITs from Quartus/QSys to calculate SDRAM size
538 * since the FB specifies we modify CSBITs to work around SDRAM
543 width = readl(&sdr_ctrl->dram_if_width);
545 /* ECC would not be calculated as its not addressible */
546 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
548 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
551 /* calculate the SDRAM size base on this info */
552 temp = 1 << (row + bank + col);
553 temp = temp * cs * (width / 8);
555 debug("%s returns %ld\n", __func__, temp);
560 static int altera_gen5_sdram_ofdata_to_platdata(struct udevice *dev)
562 struct altera_gen5_sdram_platdata *plat = dev->platdata;
564 plat->sdr = (struct socfpga_sdr *)devfdt_get_addr_index(dev, 0);
571 static int altera_gen5_sdram_probe(struct udevice *dev)
574 unsigned long sdram_size;
575 struct altera_gen5_sdram_platdata *plat = dev->platdata;
576 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
577 struct socfpga_sdr_ctrl *sdr_ctrl = &plat->sdr->sdr_ctrl;
578 struct reset_ctl_bulk resets;
580 ret = reset_get_bulk(dev, &resets);
582 dev_err(dev, "Can't get reset: %d\n", ret);
585 reset_deassert_bulk(&resets);
587 if (sdram_mmr_init_full(sdr_ctrl, 0xffffffff) != 0) {
588 puts("SDRAM init failed.\n");
592 debug("SDRAM: Calibrating PHY\n");
593 /* SDRAM calibration */
594 if (sdram_calibration_full(plat->sdr) == 0) {
595 puts("SDRAM calibration failed.\n");
599 sdram_size = sdram_calculate_size(sdr_ctrl);
600 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
602 /* Sanity check ensure correct SDRAM size specified */
603 if (get_ram_size(0, sdram_size) != sdram_size) {
604 puts("SDRAM size check failed!\n");
609 priv->info.size = sdram_size;
614 reset_release_bulk(&resets);
618 static int altera_gen5_sdram_get_info(struct udevice *dev,
619 struct ram_info *info)
621 struct altera_gen5_sdram_priv *priv = dev_get_priv(dev);
623 info->base = priv->info.base;
624 info->size = priv->info.size;
629 static struct ram_ops altera_gen5_sdram_ops = {
630 .get_info = altera_gen5_sdram_get_info,
633 static const struct udevice_id altera_gen5_sdram_ids[] = {
634 { .compatible = "altr,sdr-ctl" },
638 U_BOOT_DRIVER(altera_gen5_sdram) = {
639 .name = "altr_sdr_ctl",
641 .of_match = altera_gen5_sdram_ids,
642 .ops = &altera_gen5_sdram_ops,
643 .ofdata_to_platdata = altera_gen5_sdram_ofdata_to_platdata,
644 .platdata_auto_alloc_size = sizeof(struct altera_gen5_sdram_platdata),
645 .probe = altera_gen5_sdram_probe,
646 .priv_auto_alloc_size = sizeof(struct altera_gen5_sdram_priv),
649 #endif /* CONFIG_SPL_BUILD */