drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu_func.h>
   8 #include <errno.h>
   9 #include <fdtdec.h>
  10 #include <init.h>
  11 #include <log.h>
  12 #include <malloc.h>
  13 #include <wait_bit.h>
  14 #include <watchdog.h>
  15 #include <asm/cache.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/fpga_manager.h>
  18 #include <asm/arch/misc.h>
  19 #include <asm/arch/reset_manager.h>
  20 #include <asm/arch/sdram.h>
  21 #include <linux/bitops.h>
  22 #include <linux/delay.h>
  23 #include <linux/kernel.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 static void sdram_mmr_init(void);
  28 static u64 sdram_size_calc(void);
  29
  30 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  31 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  32
  33 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  34         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  35 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  36 #define DDR_REG_SEQ2CORE        0xFFD0507C
  37 #define DDR_REG_CORE2SEQ        0xFFD05078
  38 #define DDR_READ_LATENCY_DELAY  40
  39 #define DDR_SIZE_2GB_HEX        0x80000000
  40
  41 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  42 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  43 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  44 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  45
  46 #define SEQ2CORE_MASK           0xF
  47 #define CORE2SEQ_INT_REQ        0xF
  48 #define SEQ2CORE_INT_RESP_BIT   3
  49
  50 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  51                 (void *)SOCFPGA_SDR_ADDRESS;
  52 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  53                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  54 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  55                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  56                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  57 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  58                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  59 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  60                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  61
  62 /* The following are the supported configurations */
  63 static u32 ddr_config[] = {
  64         /* Chip - Row - Bank - Column Style */
  65         /* All Types */
  66         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  67         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  68         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  69         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  70         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  71         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  72         /* LPDDR x16 */
  73         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  74         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  75         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  76         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  77         /* DDR4 Only */
  78         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  79         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  80         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  81         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  82         /* Chip - Bank - Row - Column Style */
  83         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  84         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  85         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  86         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  87         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  88         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  89         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  90         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  91         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  92         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  93         /* DDR4 Only */
  94         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  95         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  96         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  97         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  98 };
  99
 100 static int match_ddr_conf(u32 ddr_conf)
 101 {
 102         int i;
 103
 104         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
 105                 if (ddr_conf == ddr_config[i])
 106                         return i;
 107         }
 108         return 0;
 109 }
 110
 111 static int emif_clear(void)
 112 {
 113         writel(0, DDR_REG_CORE2SEQ);
 114
 115         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 116                                 SEQ2CORE_MASK, 0, 1000, 0);
 117 }
 118
 119 static int emif_reset(void)
 120 {
 121         u32 c2s, s2c;
 122         int ret;
 123
 124         c2s = readl(DDR_REG_CORE2SEQ);
 125         s2c = readl(DDR_REG_SEQ2CORE);
 126
 127         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 128              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 129              readl(IO48_MMR_NIOS2_RESERVE1),
 130              readl(IO48_MMR_NIOS2_RESERVE2),
 131              readl(IO48_MMR_DRAMSTS));
 132
 133         if (s2c & SEQ2CORE_MASK) {
 134                 ret = emif_clear();
 135                 if (ret) {
 136                         debug("failed emif_clear()\n");
 137                         return -EPERM;
 138                 }
 139         }
 140
 141         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 142
 143         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 144                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 145         if (ret) {
 146                 debug("emif_reset failed to see interrupt acknowledge\n");
 147                 emif_clear();
 148                 return ret;
 149         }
 150
 151         mdelay(1);
 152
 153         ret = emif_clear();
 154         if (ret) {
 155                 debug("emif_clear() failed\n");
 156                 return -EPERM;
 157         }
 158         debug("emif_reset interrupt cleared\n");
 159
 160         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 161              readl(IO48_MMR_NIOS2_RESERVE0),
 162              readl(IO48_MMR_NIOS2_RESERVE1),
 163              readl(IO48_MMR_NIOS2_RESERVE2));
 164
 165         return 0;
 166 }
 167
 168 static int ddr_setup(void)
 169 {
 170         int i, ret;
 171
 172         /* Try 32 times to do a calibration */
 173         for (i = 0; i < 32; i++) {
 174                 mdelay(500);
 175                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 176                                         BIT(0), true, 500, false);
 177                 if (!ret)
 178                         return 0;
 179
 180                 ret = emif_reset();
 181                 if (ret)
 182                         puts("Error: Failed to reset EMIF\n");
 183         }
 184
 185         puts("Error: Could Not Calibrate SDRAM\n");
 186         return -EPERM;
 187 }
 188
 189 static int sdram_is_ecc_enabled(void)
 190 {
 191         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 192                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 193 }
 194
 195 /* Initialize SDRAM ECC bits to avoid false DBE */
 196 static void sdram_init_ecc_bits(u32 size)
 197 {
 198         icache_enable();
 199
 200         memset(0, 0, 0x8000);
 201         gd->arch.tlb_addr = 0x4000;
 202         gd->arch.tlb_size = PGTABLE_SIZE;
 203
 204         dcache_enable();
 205
 206         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 207         memset((void *)0x8000, 0, size - 0x8000);
 208         flush_dcache_all();
 209         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 210         dcache_disable();
 211 }
 212
 213 /* Function to startup the SDRAM*/
 214 static int sdram_startup(void)
 215 {
 216         /* Release NOC ddr scheduler from reset */
 217         socfpga_reset_deassert_noc_ddr_scheduler();
 218
 219         /* Bringup the DDR (calibration and configuration) */
 220         return ddr_setup();
 221 }
 222
 223 static u64 sdram_size_calc(void)
 224 {
 225         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 226
 227         u64 size = BIT(((dramaddrw &
 228                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 229                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 230                 ((dramaddrw &
 231                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 232                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 233                 ((dramaddrw &
 234                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 235                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 236                 ((dramaddrw &
 237                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 238                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 239                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 240
 241         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 242                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 243
 244         debug("SDRAM size=%llu\n", size);
 245
 246         return size;
 247 }
 248
 249 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 250 static void sdram_mmr_init(void)
 251 {
 252         u32 update_value, io48_value;
 253         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 254         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 255         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 256         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 257         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 258         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 259         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 260         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 261         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 262         u32 ddrioctl;
 263
 264         /*
 265          * Configure the DDR IO size [0xFFCFB008]
 266          * niosreserve0: Used to indicate DDR width &
 267          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 268          *      bit[8]   = 1 if user-mode OCT is present
 269          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 270          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 271          * niosreserve1: IP ADCDS version encoded as 16 bit value
 272          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 273          *                          3=EAP, 4-6 are reserved)
 274          *      bit[5:3] = Service Pack # (e.g. 1)
 275          *      bit[9:6] = Minor Release #
 276          *      bit[14:10] = Major Release #
 277          */
 278         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 279                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 280                 writel(((update_value & 0xFF) >> 5),
 281                        &socfpga_ecc_hmc_base->ddrioctrl);
 282         }
 283
 284         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 285
 286         /* Set the DDR Configuration [0xFFD12400] */
 287         io48_value = ARRIA_DDR_CONFIG(
 288                         ((ctrlcfg1 &
 289                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 290                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 291                         ((dramaddrw &
 292                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 293                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 294                         ((dramaddrw &
 295                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 296                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 297                         (dramaddrw &
 298                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 299                         ((dramaddrw &
 300                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 301                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 302
 303         update_value = match_ddr_conf(io48_value);
 304         if (update_value)
 305                 writel(update_value,
 306                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 307
 308         /*
 309          * Configure DDR timing [0xFFD1240C]
 310          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 311          *  WRTOMISS = WL + tWR + tRP + tRCD and
 312          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 313          *  First part of equation is in memory clock units so divide by 2
 314          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 315          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 316          */
 317         u32 ctrlcfg0_cfg_ctrl_burst_len =
 318                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 319                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 320
 321         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 322                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 323
 324         u32 caltim0_cfg_act_to_act =
 325                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 326                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 327
 328         u32 caltim0_cfg_act_to_act_db =
 329                 (caltim0 &
 330                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 331                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 332
 333         u32 caltim1_cfg_rd_to_wr =
 334                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 335                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 336
 337         u32 caltim1_cfg_rd_to_rd_dc =
 338                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 339                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 340
 341         u32 caltim1_cfg_rd_to_wr_dc =
 342                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 343                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 344
 345         u32 caltim2_cfg_rd_to_pch =
 346                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 347                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 348
 349         u32 caltim3_cfg_wr_to_rd =
 350                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 351                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 352
 353         u32 caltim3_cfg_wr_to_rd_dc =
 354                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 355                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 356
 357         u32 caltim4_cfg_pch_to_valid =
 358                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 359                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 360
 361         u32 caltim9_cfg_4_act_to_act = caltim9 &
 362                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 363
 364         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 365                         caltim0_cfg_act_to_rdwr -
 366                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 367
 368         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 369                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 370                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 371                       /* Up to here was in memory cycles so divide by 2 */
 372                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 373                       caltim4_cfg_pch_to_valid);
 374
 375         writel(((caltim0_cfg_act_to_act <<
 376                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 377                 (update_value <<
 378                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 379                 (io48_value <<
 380                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 381                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 382                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 383                 (caltim1_cfg_rd_to_wr <<
 384                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 385                 (caltim3_cfg_wr_to_rd <<
 386                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 387                 (((ddrioctl == 1) ? 1 : 0) <<
 388                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 389                 &socfpga_noc_ddr_scheduler_base->
 390                         ddr_t_main_scheduler_ddrtiming);
 391
 392         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 393         writel(((ddrioctl ? 0 : 1) <<
 394                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 395                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 396
 397         /* Configure the read latency [0xFFD12414] */
 398         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 399                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 400                 DDR_READ_LATENCY_DELAY,
 401                 &socfpga_noc_ddr_scheduler_base->
 402                         ddr_t_main_scheduler_readlatency);
 403
 404         /*
 405          * Configuring timing values concerning activate commands
 406          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 407          */
 408         writel(((caltim0_cfg_act_to_act_db <<
 409                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 410                 (caltim9_cfg_4_act_to_act <<
 411                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 412                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 413                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 414                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 415
 416         /*
 417          * Configuring timing values concerning device to device data bus
 418          * ownership change [0xFFD1243C]
 419          */
 420         writel(((caltim1_cfg_rd_to_rd_dc <<
 421                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 422                 (caltim1_cfg_rd_to_wr_dc <<
 423                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 424                 (caltim3_cfg_wr_to_rd_dc <<
 425                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 426                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 427
 428         /* Enable or disable the SDRAM ECC */
 429         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 430                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 431                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 432                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 433                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 434                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 435                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 436                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 437                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 438                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 439                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 440         } else {
 441                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 442                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 443                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 444                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 445                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 446                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 447                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 448         }
 449 }
 450
 451 struct firewall_entry {
 452         const char *prop_name;
 453         const u32 cfg_addr;
 454         const u32 en_addr;
 455         const u32 en_bit;
 456 };
 457 #define FW_MPU_FPGA_ADDRESS \
 458         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 459         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 460
 461 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 462                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 463                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 464
 465 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 466                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 467                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 468
 469 const struct firewall_entry firewall_table[] = {
 470         {
 471                 "mpu0",
 472                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 473                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 474                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 475         },
 476         {
 477                 "mpu1",
 478                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 479                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 480                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 481                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 482         },
 483         {
 484                 "mpu2",
 485                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 486                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 487                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 488         },
 489         {
 490                 "mpu3",
 491                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 492                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 493                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 494         },
 495         {
 496                 "l3-0",
 497                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 498                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 499                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 500         },
 501         {
 502                 "l3-1",
 503                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 504                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 505                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 506         },
 507         {
 508                 "l3-2",
 509                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 510                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 511                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 512         },
 513         {
 514                 "l3-3",
 515                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 516                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 517                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 518         },
 519         {
 520                 "l3-4",
 521                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 522                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 523                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 524         },
 525         {
 526                 "l3-5",
 527                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 528                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 529                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 530         },
 531         {
 532                 "l3-6",
 533                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 534                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 535                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 536         },
 537         {
 538                 "l3-7",
 539                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 540                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 541                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 542         },
 543         {
 544                 "fpga2sdram0-0",
 545                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 546                 (fpga2sdram0region0addr),
 547                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 548                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 549         },
 550         {
 551                 "fpga2sdram0-1",
 552                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 553                 (fpga2sdram0region1addr),
 554                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 555                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 556         },
 557         {
 558                 "fpga2sdram0-2",
 559                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 560                 (fpga2sdram0region2addr),
 561                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 562                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 563         },
 564         {
 565                 "fpga2sdram0-3",
 566                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 567                 (fpga2sdram0region3addr),
 568                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 569                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 570         },
 571         {
 572                 "fpga2sdram1-0",
 573                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 574                 (fpga2sdram1region0addr),
 575                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 576                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 577         },
 578         {
 579                 "fpga2sdram1-1",
 580                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 581                 (fpga2sdram1region1addr),
 582                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 583                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 584         },
 585         {
 586                 "fpga2sdram1-2",
 587                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 588                 (fpga2sdram1region2addr),
 589                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 590                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 591         },
 592         {
 593                 "fpga2sdram1-3",
 594                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 595                 (fpga2sdram1region3addr),
 596                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 597                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 598         },
 599         {
 600                 "fpga2sdram2-0",
 601                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 602                 (fpga2sdram2region0addr),
 603                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 604                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 605         },
 606         {
 607                 "fpga2sdram2-1",
 608                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 609                 (fpga2sdram2region1addr),
 610                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 611                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 612         },
 613         {
 614                 "fpga2sdram2-2",
 615                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 616                 (fpga2sdram2region2addr),
 617                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 618                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 619         },
 620         {
 621                 "fpga2sdram2-3",
 622                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 623                 (fpga2sdram2region3addr),
 624                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 625                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 626         },
 627
 628 };
 629
 630 static int of_sdram_firewall_setup(const void *blob)
 631 {
 632         int child, i, node, ret;
 633         u32 start_end[2];
 634         char name[32];
 635
 636         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 637         if (node < 0)
 638                 return -ENXIO;
 639
 640         child = fdt_first_subnode(blob, node);
 641         if (child < 0)
 642                 return -ENXIO;
 643
 644         /* set to default state */
 645         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 646         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 647
 648
 649         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 650                 sprintf(name, "%s", firewall_table[i].prop_name);
 651                 ret = fdtdec_get_int_array(blob, child, name,
 652                                            start_end, 2);
 653                 if (ret) {
 654                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 655                         ret = fdtdec_get_int_array(blob, child, name,
 656                                                    start_end, 2);
 657                         if (ret)
 658                                 continue;
 659                 }
 660
 661                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 662                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 663                        firewall_table[i].cfg_addr);
 664                 setbits_le32(firewall_table[i].en_addr,
 665                              firewall_table[i].en_bit);
 666         }
 667
 668         return 0;
 669 }
 670
 671 int ddr_calibration_sequence(void)
 672 {
 673         WATCHDOG_RESET();
 674
 675         /* Check to see if SDRAM cal was success */
 676         if (sdram_startup()) {
 677                 puts("DDRCAL: Failed\n");
 678                 return -EPERM;
 679         }
 680
 681         puts("DDRCAL: Success\n");
 682
 683         WATCHDOG_RESET();
 684
 685         /* initialize the MMR register */
 686         sdram_mmr_init();
 687
 688         /* assigning the SDRAM size */
 689         u64 size = sdram_size_calc();
 690
 691         /*
 692          * If size is less than zero, this is invalid/weird value from
 693          * calculation, use default Config size.
 694          * Up to 2GB is supported, 2GB would be used if more than that.
 695          */
 696         if (size <= 0)
 697                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 698         else if (DDR_SIZE_2GB_HEX <= size)
 699                 gd->ram_size = DDR_SIZE_2GB_HEX;
 700         else
 701                 gd->ram_size = (u32)size;
 702
 703         /* setup the dram info within bd */
 704         dram_init_banksize();
 705
 706         if (of_sdram_firewall_setup(gd->fdt_blob))
 707                 puts("FW: Error Configuring Firewall\n");
 708
 709         if (sdram_is_ecc_enabled())
 710                 sdram_init_ecc_bits(gd->ram_size);
 711
 712         return 0;
 713 }