1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2017 Intel Corporation <www.intel.com>
13 #include <asm/arch/fpga_manager.h>
14 #include <asm/arch/misc.h>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/sdram.h>
17 #include <linux/kernel.h>
19 DECLARE_GLOBAL_DATA_PTR;
21 static void sdram_mmr_init(void);
22 static u64 sdram_size_calc(void);
24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
25 #define ARRIA10_SDR_ACTIVATE_FAWBANK (0x1)
27 #define ARRIA_DDR_CONFIG(A, B, C, R) \
28 (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
29 #define DDR_CONFIG_ELEMENTS ARRAY_SIZE(ddr_config)
30 #define DDR_REG_SEQ2CORE 0xFFD0507C
31 #define DDR_REG_CORE2SEQ 0xFFD05078
32 #define DDR_READ_LATENCY_DELAY 40
33 #define DDR_SIZE_2GB_HEX 0x80000000
35 #define IO48_MMR_DRAMSTS 0xFFCFA0EC
36 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
37 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
38 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
40 #define SEQ2CORE_MASK 0xF
41 #define CORE2SEQ_INT_REQ 0xF
42 #define SEQ2CORE_INT_RESP_BIT 3
44 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
45 (void *)SOCFPGA_SDR_ADDRESS;
46 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
47 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
48 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
49 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
50 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
51 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
52 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
53 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
54 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
56 /* The following are the supported configurations */
57 static u32 ddr_config[] = {
58 /* Chip - Row - Bank - Column Style */
60 ARRIA_DDR_CONFIG(0, 3, 10, 12),
61 ARRIA_DDR_CONFIG(0, 3, 10, 13),
62 ARRIA_DDR_CONFIG(0, 3, 10, 14),
63 ARRIA_DDR_CONFIG(0, 3, 10, 15),
64 ARRIA_DDR_CONFIG(0, 3, 10, 16),
65 ARRIA_DDR_CONFIG(0, 3, 10, 17),
67 ARRIA_DDR_CONFIG(0, 3, 11, 14),
68 ARRIA_DDR_CONFIG(0, 3, 11, 15),
69 ARRIA_DDR_CONFIG(0, 3, 11, 16),
70 ARRIA_DDR_CONFIG(0, 3, 12, 15),
72 ARRIA_DDR_CONFIG(0, 4, 10, 14),
73 ARRIA_DDR_CONFIG(0, 4, 10, 15),
74 ARRIA_DDR_CONFIG(0, 4, 10, 16),
75 ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
76 /* Chip - Bank - Row - Column Style */
77 ARRIA_DDR_CONFIG(1, 3, 10, 12),
78 ARRIA_DDR_CONFIG(1, 3, 10, 13),
79 ARRIA_DDR_CONFIG(1, 3, 10, 14),
80 ARRIA_DDR_CONFIG(1, 3, 10, 15),
81 ARRIA_DDR_CONFIG(1, 3, 10, 16),
82 ARRIA_DDR_CONFIG(1, 3, 10, 17),
83 ARRIA_DDR_CONFIG(1, 3, 11, 14),
84 ARRIA_DDR_CONFIG(1, 3, 11, 15),
85 ARRIA_DDR_CONFIG(1, 3, 11, 16),
86 ARRIA_DDR_CONFIG(1, 3, 12, 15),
88 ARRIA_DDR_CONFIG(1, 4, 10, 14),
89 ARRIA_DDR_CONFIG(1, 4, 10, 15),
90 ARRIA_DDR_CONFIG(1, 4, 10, 16),
91 ARRIA_DDR_CONFIG(1, 4, 10, 17),
94 static int match_ddr_conf(u32 ddr_conf)
98 for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
99 if (ddr_conf == ddr_config[i])
105 /* Check whether SDRAM is successfully Calibrated */
106 static int is_sdram_cal_success(void)
108 return readl(&socfpga_ecc_hmc_base->ddrcalstat);
111 static int emif_clear(void)
113 writel(0, DDR_REG_CORE2SEQ);
115 return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
116 SEQ2CORE_MASK, 0, 1000, 0);
119 static int emif_reset(void)
124 c2s = readl(DDR_REG_CORE2SEQ);
125 s2c = readl(DDR_REG_SEQ2CORE);
127 debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
128 c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
129 readl(IO48_MMR_NIOS2_RESERVE1),
130 readl(IO48_MMR_NIOS2_RESERVE2),
131 readl(IO48_MMR_DRAMSTS));
133 if (s2c & SEQ2CORE_MASK) {
136 debug("failed emif_clear()\n");
141 writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
143 ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
144 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
146 debug("emif_reset failed to see interrupt acknowledge\n");
155 debug("emif_clear() failed\n");
158 debug("emif_reset interrupt cleared\n");
160 debug("nr0=%08x nr1=%08x nr2=%08x\n",
161 readl(IO48_MMR_NIOS2_RESERVE0),
162 readl(IO48_MMR_NIOS2_RESERVE1),
163 readl(IO48_MMR_NIOS2_RESERVE2));
168 static int ddr_setup(void)
170 int i, j, ddr_setup_complete = 0;
172 /* Try 3 times to do a calibration */
173 for (i = 0; (i < 3) && !ddr_setup_complete; i++) {
176 /* A delay to wait for calibration bit to set */
177 for (j = 0; (j < 10) && !ddr_setup_complete; j++) {
179 ddr_setup_complete = is_sdram_cal_success();
182 if (!ddr_setup_complete)
184 puts("Error: Failed to reset EMIF\n");
187 /* After 3 times trying calibration */
188 if (!ddr_setup_complete) {
189 puts("Error: Could Not Calibrate SDRAM\n");
196 static int sdram_is_ecc_enabled(void)
198 return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
199 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
202 /* Initialize SDRAM ECC bits to avoid false DBE */
203 static void sdram_init_ecc_bits(u32 size)
207 memset(0, 0, 0x8000);
208 gd->arch.tlb_addr = 0x4000;
209 gd->arch.tlb_size = PGTABLE_SIZE;
213 printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
214 memset((void *)0x8000, 0, size - 0x8000);
216 printf("DDRCAL: Scrubbing ECC RAM done.\n");
220 /* Function to startup the SDRAM*/
221 static int sdram_startup(void)
223 /* Release NOC ddr scheduler from reset */
224 socfpga_reset_deassert_noc_ddr_scheduler();
226 /* Bringup the DDR (calibration and configuration) */
230 static u64 sdram_size_calc(void)
232 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
234 u64 size = BIT(((dramaddrw &
235 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
236 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
238 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
239 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
241 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
242 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
244 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
245 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
246 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
248 size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
249 ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
251 debug("SDRAM size=%llu\n", size);
256 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
257 static void sdram_mmr_init(void)
259 u32 update_value, io48_value;
260 u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
261 u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
262 u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
263 u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
264 u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
265 u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
266 u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
267 u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
268 u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
272 * Configure the DDR IO size [0xFFCFB008]
273 * niosreserve0: Used to indicate DDR width &
274 * bit[7:0] = Number of data bits (0x20 for 32bit)
275 * bit[8] = 1 if user-mode OCT is present
276 * bit[9] = 1 if warm reset compiled into EMIF Cal Code
277 * bit[10] = 1 if warm reset is on during generation in EMIF Cal
278 * niosreserve1: IP ADCDS version encoded as 16 bit value
279 * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
280 * 3=EAP, 4-6 are reserved)
281 * bit[5:3] = Service Pack # (e.g. 1)
282 * bit[9:6] = Minor Release #
283 * bit[14:10] = Major Release #
285 if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
286 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
287 writel(((update_value & 0xFF) >> 5),
288 &socfpga_ecc_hmc_base->ddrioctrl);
291 ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
293 /* Set the DDR Configuration [0xFFD12400] */
294 io48_value = ARRIA_DDR_CONFIG(
296 IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
297 IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
299 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
300 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
302 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
303 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
305 IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
307 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
308 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
310 update_value = match_ddr_conf(io48_value);
313 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
316 * Configure DDR timing [0xFFD1240C]
317 * RDTOMISS = tRTP + tRP + tRCD - BL/2
318 * WRTOMISS = WL + tWR + tRP + tRCD and
319 * WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns so...
320 * First part of equation is in memory clock units so divide by 2
321 * for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
322 * WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
324 u32 ctrlcfg0_cfg_ctrl_burst_len =
325 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
326 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
328 u32 caltim0_cfg_act_to_rdwr = caltim0 &
329 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
331 u32 caltim0_cfg_act_to_act =
332 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
333 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
335 u32 caltim0_cfg_act_to_act_db =
337 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
338 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
340 u32 caltim1_cfg_rd_to_wr =
341 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
342 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
344 u32 caltim1_cfg_rd_to_rd_dc =
345 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
346 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
348 u32 caltim1_cfg_rd_to_wr_dc =
349 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
350 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
352 u32 caltim2_cfg_rd_to_pch =
353 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
354 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
356 u32 caltim3_cfg_wr_to_rd =
357 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
358 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
360 u32 caltim3_cfg_wr_to_rd_dc =
361 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
362 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
364 u32 caltim4_cfg_pch_to_valid =
365 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
366 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
368 u32 caltim9_cfg_4_act_to_act = caltim9 &
369 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
371 update_value = (caltim2_cfg_rd_to_pch + caltim4_cfg_pch_to_valid +
372 caltim0_cfg_act_to_rdwr -
373 (ctrlcfg0_cfg_ctrl_burst_len >> 2));
375 io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
376 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
377 (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
378 /* Up to here was in memory cycles so divide by 2 */
379 caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
380 caltim4_cfg_pch_to_valid);
382 writel(((caltim0_cfg_act_to_act <<
383 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
385 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
387 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
388 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
389 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
390 (caltim1_cfg_rd_to_wr <<
391 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
392 (caltim3_cfg_wr_to_rd <<
393 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
394 (((ddrioctl == 1) ? 1 : 0) <<
395 ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
396 &socfpga_noc_ddr_scheduler_base->
397 ddr_t_main_scheduler_ddrtiming);
399 /* Configure DDR mode [0xFFD12410] [precharge = 0] */
400 writel(((ddrioctl ? 0 : 1) <<
401 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
402 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
404 /* Configure the read latency [0xFFD12414] */
405 writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
406 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
407 DDR_READ_LATENCY_DELAY,
408 &socfpga_noc_ddr_scheduler_base->
409 ddr_t_main_scheduler_readlatency);
412 * Configuring timing values concerning activate commands
413 * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
415 writel(((caltim0_cfg_act_to_act_db <<
416 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
417 (caltim9_cfg_4_act_to_act <<
418 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
419 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
420 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
421 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
424 * Configuring timing values concerning device to device data bus
425 * ownership change [0xFFD1243C]
427 writel(((caltim1_cfg_rd_to_rd_dc <<
428 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
429 (caltim1_cfg_rd_to_wr_dc <<
430 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
431 (caltim3_cfg_wr_to_rd_dc <<
432 ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
433 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
435 /* Enable or disable the SDRAM ECC */
436 if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
437 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
438 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
439 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
440 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
441 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
442 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
443 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
444 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
445 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
446 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
448 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
449 (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
450 ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
451 ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
452 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
453 (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
454 ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
458 struct firewall_entry {
459 const char *prop_name;
464 #define FW_MPU_FPGA_ADDRESS \
465 ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
466 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
468 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
469 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
470 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
472 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
473 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
474 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
476 const struct firewall_entry firewall_table[] = {
479 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
480 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
481 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
485 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
486 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
487 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
488 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
492 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
493 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
494 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
498 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
499 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
500 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
504 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
505 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
506 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
510 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
511 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
512 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
516 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
517 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
518 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
522 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
523 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
524 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
528 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
529 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
530 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
534 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
535 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
536 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
540 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
541 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
542 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
546 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
547 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
548 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
552 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
553 (fpga2sdram0region0addr),
554 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
555 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
559 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
560 (fpga2sdram0region1addr),
561 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
562 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
566 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
567 (fpga2sdram0region2addr),
568 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
569 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
573 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
574 (fpga2sdram0region3addr),
575 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
576 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
580 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
581 (fpga2sdram1region0addr),
582 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
583 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
587 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
588 (fpga2sdram1region1addr),
589 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
590 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
594 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
595 (fpga2sdram1region2addr),
596 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
597 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
601 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
602 (fpga2sdram1region3addr),
603 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
604 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
608 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
609 (fpga2sdram2region0addr),
610 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
611 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
615 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
616 (fpga2sdram2region1addr),
617 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
618 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
622 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
623 (fpga2sdram2region2addr),
624 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
625 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
629 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
630 (fpga2sdram2region3addr),
631 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
632 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
637 static int of_sdram_firewall_setup(const void *blob)
639 int child, i, node, ret;
643 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
647 child = fdt_first_subnode(blob, node);
651 /* set to default state */
652 writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
653 writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
656 for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
657 sprintf(name, "%s", firewall_table[i].prop_name);
658 ret = fdtdec_get_int_array(blob, child, name,
661 sprintf(name, "altr,%s", firewall_table[i].prop_name);
662 ret = fdtdec_get_int_array(blob, child, name,
668 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
669 (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
670 firewall_table[i].cfg_addr);
671 setbits_le32(firewall_table[i].en_addr,
672 firewall_table[i].en_bit);
678 int ddr_calibration_sequence(void)
682 /* Check to see if SDRAM cal was success */
683 if (sdram_startup()) {
684 puts("DDRCAL: Failed\n");
688 puts("DDRCAL: Success\n");
692 /* initialize the MMR register */
695 /* assigning the SDRAM size */
696 u64 size = sdram_size_calc();
699 * If size is less than zero, this is invalid/weird value from
700 * calculation, use default Config size.
701 * Up to 2GB is supported, 2GB would be used if more than that.
704 gd->ram_size = PHYS_SDRAM_1_SIZE;
705 else if (DDR_SIZE_2GB_HEX <= size)
706 gd->ram_size = DDR_SIZE_2GB_HEX;
708 gd->ram_size = (u32)size;
710 /* setup the dram info within bd */
711 dram_init_banksize();
713 if (of_sdram_firewall_setup(gd->fdt_blob))
714 puts("FW: Error Configuring Firewall\n");
716 if (sdram_is_ecc_enabled())
717 sdram_init_ecc_bits(gd->ram_size);