drivers/ddr/altera/sdram_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2017 Intel Corporation <www.intel.com>
   4  */
   5
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <fdtdec.h>
   9 #include <malloc.h>
  10 #include <wait_bit.h>
  11 #include <watchdog.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/fpga_manager.h>
  14 #include <asm/arch/misc.h>
  15 #include <asm/arch/reset_manager.h>
  16 #include <asm/arch/sdram.h>
  17 #include <linux/kernel.h>
  18
  19 DECLARE_GLOBAL_DATA_PTR;
  20
  21 static void sdram_mmr_init(void);
  22 static u64 sdram_size_calc(void);
  23
  24 /* FAWBANK - Number of Bank of a given device involved in the FAW period. */
  25 #define ARRIA10_SDR_ACTIVATE_FAWBANK    (0x1)
  26
  27 #define ARRIA_DDR_CONFIG(A, B, C, R) \
  28         (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
  29 #define DDR_CONFIG_ELEMENTS     ARRAY_SIZE(ddr_config)
  30 #define DDR_REG_SEQ2CORE        0xFFD0507C
  31 #define DDR_REG_CORE2SEQ        0xFFD05078
  32 #define DDR_READ_LATENCY_DELAY  40
  33 #define DDR_SIZE_2GB_HEX        0x80000000
  34
  35 #define IO48_MMR_DRAMSTS        0xFFCFA0EC
  36 #define IO48_MMR_NIOS2_RESERVE0 0xFFCFA110
  37 #define IO48_MMR_NIOS2_RESERVE1 0xFFCFA114
  38 #define IO48_MMR_NIOS2_RESERVE2 0xFFCFA118
  39
  40 #define SEQ2CORE_MASK           0xF
  41 #define CORE2SEQ_INT_REQ        0xF
  42 #define SEQ2CORE_INT_RESP_BIT   3
  43
  44 static const struct socfpga_ecc_hmc *socfpga_ecc_hmc_base =
  45                 (void *)SOCFPGA_SDR_ADDRESS;
  46 static const struct socfpga_noc_ddr_scheduler *socfpga_noc_ddr_scheduler_base =
  47                 (void *)SOCFPGA_SDR_SCHEDULER_ADDRESS;
  48 static const struct socfpga_noc_fw_ddr_mpu_fpga2sdram
  49                 *socfpga_noc_fw_ddr_mpu_fpga2sdram_base =
  50                 (void *)SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS;
  51 static const struct socfpga_noc_fw_ddr_l3 *socfpga_noc_fw_ddr_l3_base =
  52                 (void *)SOCFPGA_SDR_FIREWALL_L3_ADDRESS;
  53 static const struct socfpga_io48_mmr *socfpga_io48_mmr_base =
  54                 (void *)SOCFPGA_HMC_MMR_IO48_ADDRESS;
  55
  56 /* The following are the supported configurations */
  57 static u32 ddr_config[] = {
  58         /* Chip - Row - Bank - Column Style */
  59         /* All Types */
  60         ARRIA_DDR_CONFIG(0, 3, 10, 12),
  61         ARRIA_DDR_CONFIG(0, 3, 10, 13),
  62         ARRIA_DDR_CONFIG(0, 3, 10, 14),
  63         ARRIA_DDR_CONFIG(0, 3, 10, 15),
  64         ARRIA_DDR_CONFIG(0, 3, 10, 16),
  65         ARRIA_DDR_CONFIG(0, 3, 10, 17),
  66         /* LPDDR x16 */
  67         ARRIA_DDR_CONFIG(0, 3, 11, 14),
  68         ARRIA_DDR_CONFIG(0, 3, 11, 15),
  69         ARRIA_DDR_CONFIG(0, 3, 11, 16),
  70         ARRIA_DDR_CONFIG(0, 3, 12, 15),
  71         /* DDR4 Only */
  72         ARRIA_DDR_CONFIG(0, 4, 10, 14),
  73         ARRIA_DDR_CONFIG(0, 4, 10, 15),
  74         ARRIA_DDR_CONFIG(0, 4, 10, 16),
  75         ARRIA_DDR_CONFIG(0, 4, 10, 17), /* 14 */
  76         /* Chip - Bank - Row - Column Style */
  77         ARRIA_DDR_CONFIG(1, 3, 10, 12),
  78         ARRIA_DDR_CONFIG(1, 3, 10, 13),
  79         ARRIA_DDR_CONFIG(1, 3, 10, 14),
  80         ARRIA_DDR_CONFIG(1, 3, 10, 15),
  81         ARRIA_DDR_CONFIG(1, 3, 10, 16),
  82         ARRIA_DDR_CONFIG(1, 3, 10, 17),
  83         ARRIA_DDR_CONFIG(1, 3, 11, 14),
  84         ARRIA_DDR_CONFIG(1, 3, 11, 15),
  85         ARRIA_DDR_CONFIG(1, 3, 11, 16),
  86         ARRIA_DDR_CONFIG(1, 3, 12, 15),
  87         /* DDR4 Only */
  88         ARRIA_DDR_CONFIG(1, 4, 10, 14),
  89         ARRIA_DDR_CONFIG(1, 4, 10, 15),
  90         ARRIA_DDR_CONFIG(1, 4, 10, 16),
  91         ARRIA_DDR_CONFIG(1, 4, 10, 17),
  92 };
  93
  94 static int match_ddr_conf(u32 ddr_conf)
  95 {
  96         int i;
  97
  98         for (i = 0; i < DDR_CONFIG_ELEMENTS; i++) {
  99                 if (ddr_conf == ddr_config[i])
 100                         return i;
 101         }
 102         return 0;
 103 }
 104
 105 static int emif_clear(void)
 106 {
 107         writel(0, DDR_REG_CORE2SEQ);
 108
 109         return wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 110                                 SEQ2CORE_MASK, 0, 1000, 0);
 111 }
 112
 113 static int emif_reset(void)
 114 {
 115         u32 c2s, s2c;
 116         int ret;
 117
 118         c2s = readl(DDR_REG_CORE2SEQ);
 119         s2c = readl(DDR_REG_SEQ2CORE);
 120
 121         debug("c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",
 122              c2s, s2c, readl(IO48_MMR_NIOS2_RESERVE0),
 123              readl(IO48_MMR_NIOS2_RESERVE1),
 124              readl(IO48_MMR_NIOS2_RESERVE2),
 125              readl(IO48_MMR_DRAMSTS));
 126
 127         if (s2c & SEQ2CORE_MASK) {
 128                 ret = emif_clear();
 129                 if (ret) {
 130                         debug("failed emif_clear()\n");
 131                         return -EPERM;
 132                 }
 133         }
 134
 135         writel(CORE2SEQ_INT_REQ, DDR_REG_CORE2SEQ);
 136
 137         ret = wait_for_bit_le32((u32 *)DDR_REG_SEQ2CORE,
 138                                 SEQ2CORE_INT_RESP_BIT, false, 1000, false);
 139         if (ret) {
 140                 debug("emif_reset failed to see interrupt acknowledge\n");
 141                 emif_clear();
 142                 return ret;
 143         }
 144
 145         mdelay(1);
 146
 147         ret = emif_clear();
 148         if (ret) {
 149                 debug("emif_clear() failed\n");
 150                 return -EPERM;
 151         }
 152         debug("emif_reset interrupt cleared\n");
 153
 154         debug("nr0=%08x nr1=%08x nr2=%08x\n",
 155              readl(IO48_MMR_NIOS2_RESERVE0),
 156              readl(IO48_MMR_NIOS2_RESERVE1),
 157              readl(IO48_MMR_NIOS2_RESERVE2));
 158
 159         return 0;
 160 }
 161
 162 static int ddr_setup(void)
 163 {
 164         int i, ret;
 165
 166         /* Try 32 times to do a calibration */
 167         for (i = 0; i < 32; i++) {
 168                 mdelay(500);
 169                 ret = wait_for_bit_le32(&socfpga_ecc_hmc_base->ddrcalstat,
 170                                         BIT(0), true, 500, false);
 171                 if (!ret)
 172                         return 0;
 173
 174                 ret = emif_reset();
 175                 if (ret)
 176                         puts("Error: Failed to reset EMIF\n");
 177         }
 178
 179         puts("Error: Could Not Calibrate SDRAM\n");
 180         return -EPERM;
 181 }
 182
 183 static int sdram_is_ecc_enabled(void)
 184 {
 185         return !!(readl(&socfpga_ecc_hmc_base->eccctrl) &
 186                   ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK);
 187 }
 188
 189 /* Initialize SDRAM ECC bits to avoid false DBE */
 190 static void sdram_init_ecc_bits(u32 size)
 191 {
 192         icache_enable();
 193
 194         memset(0, 0, 0x8000);
 195         gd->arch.tlb_addr = 0x4000;
 196         gd->arch.tlb_size = PGTABLE_SIZE;
 197
 198         dcache_enable();
 199
 200         printf("DDRCAL: Scrubbing ECC RAM (%i MiB).\n", size >> 20);
 201         memset((void *)0x8000, 0, size - 0x8000);
 202         flush_dcache_all();
 203         printf("DDRCAL: Scrubbing ECC RAM done.\n");
 204         dcache_disable();
 205 }
 206
 207 /* Function to startup the SDRAM*/
 208 static int sdram_startup(void)
 209 {
 210         /* Release NOC ddr scheduler from reset */
 211         socfpga_reset_deassert_noc_ddr_scheduler();
 212
 213         /* Bringup the DDR (calibration and configuration) */
 214         return ddr_setup();
 215 }
 216
 217 static u64 sdram_size_calc(void)
 218 {
 219         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 220
 221         u64 size = BIT(((dramaddrw &
 222                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MASK) >>
 223                 IO48_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SHIFT) +
 224                 ((dramaddrw &
 225                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 226                 IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT) +
 227                 ((dramaddrw &
 228                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 229                 IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 230                 ((dramaddrw &
 231                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 232                 IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT) +
 233                 (dramaddrw & IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK));
 234
 235         size *= (2 << (readl(&socfpga_ecc_hmc_base->ddrioctrl) &
 236                        ALT_ECC_HMC_OCP_DDRIOCTRL_IO_SIZE_MSK));
 237
 238         debug("SDRAM size=%llu\n", size);
 239
 240         return size;
 241 }
 242
 243 /* Function to initialize SDRAM MMR and NOC DDR scheduler*/
 244 static void sdram_mmr_init(void)
 245 {
 246         u32 update_value, io48_value;
 247         u32 ctrlcfg0 = readl(&socfpga_io48_mmr_base->ctrlcfg0);
 248         u32 ctrlcfg1 = readl(&socfpga_io48_mmr_base->ctrlcfg1);
 249         u32 dramaddrw = readl(&socfpga_io48_mmr_base->dramaddrw);
 250         u32 caltim0 = readl(&socfpga_io48_mmr_base->caltiming0);
 251         u32 caltim1 = readl(&socfpga_io48_mmr_base->caltiming1);
 252         u32 caltim2 = readl(&socfpga_io48_mmr_base->caltiming2);
 253         u32 caltim3 = readl(&socfpga_io48_mmr_base->caltiming3);
 254         u32 caltim4 = readl(&socfpga_io48_mmr_base->caltiming4);
 255         u32 caltim9 = readl(&socfpga_io48_mmr_base->caltiming9);
 256         u32 ddrioctl;
 257
 258         /*
 259          * Configure the DDR IO size [0xFFCFB008]
 260          * niosreserve0: Used to indicate DDR width &
 261          *      bit[7:0] = Number of data bits (0x20 for 32bit)
 262          *      bit[8]   = 1 if user-mode OCT is present
 263          *      bit[9]   = 1 if warm reset compiled into EMIF Cal Code
 264          *      bit[10]  = 1 if warm reset is on during generation in EMIF Cal
 265          * niosreserve1: IP ADCDS version encoded as 16 bit value
 266          *      bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,
 267          *                          3=EAP, 4-6 are reserved)
 268          *      bit[5:3] = Service Pack # (e.g. 1)
 269          *      bit[9:6] = Minor Release #
 270          *      bit[14:10] = Major Release #
 271          */
 272         if ((readl(&socfpga_io48_mmr_base->niosreserve1) >> 6) & 0x1FF) {
 273                 update_value = readl(&socfpga_io48_mmr_base->niosreserve0);
 274                 writel(((update_value & 0xFF) >> 5),
 275                        &socfpga_ecc_hmc_base->ddrioctrl);
 276         }
 277
 278         ddrioctl = readl(&socfpga_ecc_hmc_base->ddrioctrl);
 279
 280         /* Set the DDR Configuration [0xFFD12400] */
 281         io48_value = ARRIA_DDR_CONFIG(
 282                         ((ctrlcfg1 &
 283                         IO48_MMR_CTRLCFG1_ADDR_ORDER_MASK) >>
 284                         IO48_MMR_CTRLCFG1_ADDR_ORDER_SHIFT),
 285                         ((dramaddrw &
 286                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MASK) >>
 287                         IO48_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SHIFT) +
 288                         ((dramaddrw &
 289                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MASK) >>
 290                         IO48_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SHIFT),
 291                         (dramaddrw &
 292                         IO48_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MASK),
 293                         ((dramaddrw &
 294                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MASK) >>
 295                         IO48_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SHIFT));
 296
 297         update_value = match_ddr_conf(io48_value);
 298         if (update_value)
 299                 writel(update_value,
 300                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrconf);
 301
 302         /*
 303          * Configure DDR timing [0xFFD1240C]
 304          *  RDTOMISS = tRTP + tRP + tRCD - BL/2
 305          *  WRTOMISS = WL + tWR + tRP + tRCD and
 306          *    WL = RL + BL/2 + 2 - rd-to-wr ; tWR = 15ns  so...
 307          *  First part of equation is in memory clock units so divide by 2
 308          *  for HMC clock units. 1066MHz is close to 1ns so use 15 directly.
 309          *  WRTOMISS = ((RL + BL/2 + 2 + tWR) >> 1)- rd-to-wr + tRP + tRCD
 310          */
 311         u32 ctrlcfg0_cfg_ctrl_burst_len =
 312                 (ctrlcfg0 & IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_MASK) >>
 313                 IO48_MMR_CTRLCFG0_CTRL_BURST_LENGTH_SHIFT;
 314
 315         u32 caltim0_cfg_act_to_rdwr = caltim0 &
 316                 IO48_MMR_CALTIMING0_CFG_ACT_TO_RDWR_MASK;
 317
 318         u32 caltim0_cfg_act_to_act =
 319                 (caltim0 & IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_MASK) >>
 320                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_SHIFT;
 321
 322         u32 caltim0_cfg_act_to_act_db =
 323                 (caltim0 &
 324                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_MASK) >>
 325                 IO48_MMR_CALTIMING0_CFG_ACT_TO_ACT_DIFF_BANK_SHIFT;
 326
 327         u32 caltim1_cfg_rd_to_wr =
 328                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_MASK) >>
 329                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_SHIFT;
 330
 331         u32 caltim1_cfg_rd_to_rd_dc =
 332                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_MASK) >>
 333                 IO48_MMR_CALTIMING1_CFG_RD_TO_RD_DC_SHIFT;
 334
 335         u32 caltim1_cfg_rd_to_wr_dc =
 336                 (caltim1 & IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_MASK) >>
 337                 IO48_MMR_CALTIMING1_CFG_RD_TO_WR_DIFF_CHIP_SHIFT;
 338
 339         u32 caltim2_cfg_rd_to_pch =
 340                 (caltim2 & IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_MASK) >>
 341                 IO48_MMR_CALTIMING2_CFG_RD_TO_PCH_SHIFT;
 342
 343         u32 caltim3_cfg_wr_to_rd =
 344                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_MASK) >>
 345                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_SHIFT;
 346
 347         u32 caltim3_cfg_wr_to_rd_dc =
 348                 (caltim3 & IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_MASK) >>
 349                 IO48_MMR_CALTIMING3_CFG_WR_TO_RD_DIFF_CHIP_SHIFT;
 350
 351         u32 caltim4_cfg_pch_to_valid =
 352                 (caltim4 & IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_MASK) >>
 353                 IO48_MMR_CALTIMING4_CFG_PCH_TO_VALID_SHIFT;
 354
 355         u32 caltim9_cfg_4_act_to_act = caltim9 &
 356                 IO48_MMR_CALTIMING9_CFG_WR_4_ACT_TO_ACT_MASK;
 357
 358         update_value = (caltim2_cfg_rd_to_pch +  caltim4_cfg_pch_to_valid +
 359                         caltim0_cfg_act_to_rdwr -
 360                         (ctrlcfg0_cfg_ctrl_burst_len >> 2));
 361
 362         io48_value = ((((readl(&socfpga_io48_mmr_base->dramtiming0) &
 363                       ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) + 2 + 15 +
 364                       (ctrlcfg0_cfg_ctrl_burst_len >> 1)) >> 1) -
 365                       /* Up to here was in memory cycles so divide by 2 */
 366                       caltim1_cfg_rd_to_wr + caltim0_cfg_act_to_rdwr +
 367                       caltim4_cfg_pch_to_valid);
 368
 369         writel(((caltim0_cfg_act_to_act <<
 370                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB) |
 371                 (update_value <<
 372                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB) |
 373                 (io48_value <<
 374                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB) |
 375                 ((ctrlcfg0_cfg_ctrl_burst_len >> 2) <<
 376                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB) |
 377                 (caltim1_cfg_rd_to_wr <<
 378                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB) |
 379                 (caltim3_cfg_wr_to_rd <<
 380                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB) |
 381                 (((ddrioctl == 1) ? 1 : 0) <<
 382                         ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB)),
 383                 &socfpga_noc_ddr_scheduler_base->
 384                         ddr_t_main_scheduler_ddrtiming);
 385
 386         /* Configure DDR mode [0xFFD12410] [precharge = 0] */
 387         writel(((ddrioctl ? 0 : 1) <<
 388                 ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB),
 389                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_ddrmode);
 390
 391         /* Configure the read latency [0xFFD12414] */
 392         writel(((readl(&socfpga_io48_mmr_base->dramtiming0) &
 393                 ALT_IO48_DRAMTIME_MEM_READ_LATENCY_MASK) >> 1) +
 394                 DDR_READ_LATENCY_DELAY,
 395                 &socfpga_noc_ddr_scheduler_base->
 396                         ddr_t_main_scheduler_readlatency);
 397
 398         /*
 399          * Configuring timing values concerning activate commands
 400          * [0xFFD12438] [FAWBANK alway 1 because always 4 bank DDR]
 401          */
 402         writel(((caltim0_cfg_act_to_act_db <<
 403                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB) |
 404                 (caltim9_cfg_4_act_to_act <<
 405                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB) |
 406                 (ARRIA10_SDR_ACTIVATE_FAWBANK <<
 407                         ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB)),
 408                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_activate);
 409
 410         /*
 411          * Configuring timing values concerning device to device data bus
 412          * ownership change [0xFFD1243C]
 413          */
 414         writel(((caltim1_cfg_rd_to_rd_dc <<
 415                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB) |
 416                 (caltim1_cfg_rd_to_wr_dc <<
 417                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB) |
 418                 (caltim3_cfg_wr_to_rd_dc <<
 419                         ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB)),
 420                 &socfpga_noc_ddr_scheduler_base->ddr_t_main_scheduler_devtodev);
 421
 422         /* Enable or disable the SDRAM ECC */
 423         if (ctrlcfg1 & IO48_MMR_CTRLCFG1_CTRL_ENABLE_ECC) {
 424                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 425                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 426                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 427                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 428                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 429                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 430                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK));
 431                 setbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 432                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 433                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 434         } else {
 435                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl,
 436                              (ALT_ECC_HMC_OCP_ECCCTL_AWB_CNT_RST_SET_MSK |
 437                               ALT_ECC_HMC_OCP_ECCCTL_CNT_RST_SET_MSK |
 438                               ALT_ECC_HMC_OCP_ECCCTL_ECC_EN_SET_MSK));
 439                 clrbits_le32(&socfpga_ecc_hmc_base->eccctrl2,
 440                              (ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK |
 441                               ALT_ECC_HMC_OCP_ECCCTL2_AWB_EN_SET_MSK));
 442         }
 443 }
 444
 445 struct firewall_entry {
 446         const char *prop_name;
 447         const u32 cfg_addr;
 448         const u32 en_addr;
 449         const u32 en_bit;
 450 };
 451 #define FW_MPU_FPGA_ADDRESS \
 452         ((const struct socfpga_noc_fw_ddr_mpu_fpga2sdram *)\
 453         SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS)
 454
 455 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(ADDR) \
 456                 (SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS + \
 457                 offsetof(struct socfpga_noc_fw_ddr_mpu_fpga2sdram, ADDR))
 458
 459 #define SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(ADDR) \
 460                 (SOCFPGA_SDR_FIREWALL_L3_ADDRESS + \
 461                 offsetof(struct socfpga_noc_fw_ddr_l3, ADDR))
 462
 463 const struct firewall_entry firewall_table[] = {
 464         {
 465                 "mpu0",
 466                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion0addr),
 467                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 468                 ALT_NOC_FW_DDR_SCR_EN_MPUREG0EN_SET_MSK
 469         },
 470         {
 471                 "mpu1",
 472                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS +
 473                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion1addr),
 474                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 475                 ALT_NOC_FW_DDR_SCR_EN_MPUREG1EN_SET_MSK
 476         },
 477         {
 478                 "mpu2",
 479                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion2addr),
 480                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 481                 ALT_NOC_FW_DDR_SCR_EN_MPUREG2EN_SET_MSK
 482         },
 483         {
 484                 "mpu3",
 485                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(mpuregion3addr),
 486                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 487                 ALT_NOC_FW_DDR_SCR_EN_MPUREG3EN_SET_MSK
 488         },
 489         {
 490                 "l3-0",
 491                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion0addr),
 492                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 493                 ALT_NOC_FW_DDR_SCR_EN_HPSREG0EN_SET_MSK
 494         },
 495         {
 496                 "l3-1",
 497                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion1addr),
 498                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 499                 ALT_NOC_FW_DDR_SCR_EN_HPSREG1EN_SET_MSK
 500         },
 501         {
 502                 "l3-2",
 503                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion2addr),
 504                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 505                 ALT_NOC_FW_DDR_SCR_EN_HPSREG2EN_SET_MSK
 506         },
 507         {
 508                 "l3-3",
 509                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion3addr),
 510                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 511                 ALT_NOC_FW_DDR_SCR_EN_HPSREG3EN_SET_MSK
 512         },
 513         {
 514                 "l3-4",
 515                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion4addr),
 516                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 517                 ALT_NOC_FW_DDR_SCR_EN_HPSREG4EN_SET_MSK
 518         },
 519         {
 520                 "l3-5",
 521                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion5addr),
 522                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 523                 ALT_NOC_FW_DDR_SCR_EN_HPSREG5EN_SET_MSK
 524         },
 525         {
 526                 "l3-6",
 527                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion6addr),
 528                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 529                 ALT_NOC_FW_DDR_SCR_EN_HPSREG6EN_SET_MSK
 530         },
 531         {
 532                 "l3-7",
 533                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(hpsregion7addr),
 534                 SOCFPGA_SDR_FIREWALL_L3_ADDRESS_OFFSET(enable),
 535                 ALT_NOC_FW_DDR_SCR_EN_HPSREG7EN_SET_MSK
 536         },
 537         {
 538                 "fpga2sdram0-0",
 539                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 540                 (fpga2sdram0region0addr),
 541                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 542                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK
 543         },
 544         {
 545                 "fpga2sdram0-1",
 546                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 547                 (fpga2sdram0region1addr),
 548                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 549                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK
 550         },
 551         {
 552                 "fpga2sdram0-2",
 553                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 554                 (fpga2sdram0region2addr),
 555                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 556                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK
 557         },
 558         {
 559                 "fpga2sdram0-3",
 560                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 561                 (fpga2sdram0region3addr),
 562                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 563                 ALT_NOC_FW_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK
 564         },
 565         {
 566                 "fpga2sdram1-0",
 567                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 568                 (fpga2sdram1region0addr),
 569                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 570                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK
 571         },
 572         {
 573                 "fpga2sdram1-1",
 574                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 575                 (fpga2sdram1region1addr),
 576                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 577                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK
 578         },
 579         {
 580                 "fpga2sdram1-2",
 581                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 582                 (fpga2sdram1region2addr),
 583                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 584                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK
 585         },
 586         {
 587                 "fpga2sdram1-3",
 588                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 589                 (fpga2sdram1region3addr),
 590                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 591                 ALT_NOC_FW_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK
 592         },
 593         {
 594                 "fpga2sdram2-0",
 595                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 596                 (fpga2sdram2region0addr),
 597                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 598                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK
 599         },
 600         {
 601                 "fpga2sdram2-1",
 602                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 603                 (fpga2sdram2region1addr),
 604                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 605                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK
 606         },
 607         {
 608                 "fpga2sdram2-2",
 609                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 610                 (fpga2sdram2region2addr),
 611                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 612                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK
 613         },
 614         {
 615                 "fpga2sdram2-3",
 616                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET
 617                 (fpga2sdram2region3addr),
 618                 SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS_OFFSET(enable),
 619                 ALT_NOC_FW_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK
 620         },
 621
 622 };
 623
 624 static int of_sdram_firewall_setup(const void *blob)
 625 {
 626         int child, i, node, ret;
 627         u32 start_end[2];
 628         char name[32];
 629
 630         node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_NOC);
 631         if (node < 0)
 632                 return -ENXIO;
 633
 634         child = fdt_first_subnode(blob, node);
 635         if (child < 0)
 636                 return -ENXIO;
 637
 638         /* set to default state */
 639         writel(0, &socfpga_noc_fw_ddr_mpu_fpga2sdram_base->enable);
 640         writel(0, &socfpga_noc_fw_ddr_l3_base->enable);
 641
 642
 643         for (i = 0; i < ARRAY_SIZE(firewall_table); i++) {
 644                 sprintf(name, "%s", firewall_table[i].prop_name);
 645                 ret = fdtdec_get_int_array(blob, child, name,
 646                                            start_end, 2);
 647                 if (ret) {
 648                         sprintf(name, "altr,%s", firewall_table[i].prop_name);
 649                         ret = fdtdec_get_int_array(blob, child, name,
 650                                                    start_end, 2);
 651                         if (ret)
 652                                 continue;
 653                 }
 654
 655                 writel((start_end[0] & ALT_NOC_FW_DDR_ADDR_MASK) |
 656                        (start_end[1] << ALT_NOC_FW_DDR_END_ADDR_LSB),
 657                        firewall_table[i].cfg_addr);
 658                 setbits_le32(firewall_table[i].en_addr,
 659                              firewall_table[i].en_bit);
 660         }
 661
 662         return 0;
 663 }
 664
 665 int ddr_calibration_sequence(void)
 666 {
 667         WATCHDOG_RESET();
 668
 669         /* Check to see if SDRAM cal was success */
 670         if (sdram_startup()) {
 671                 puts("DDRCAL: Failed\n");
 672                 return -EPERM;
 673         }
 674
 675         puts("DDRCAL: Success\n");
 676
 677         WATCHDOG_RESET();
 678
 679         /* initialize the MMR register */
 680         sdram_mmr_init();
 681
 682         /* assigning the SDRAM size */
 683         u64 size = sdram_size_calc();
 684
 685         /*
 686          * If size is less than zero, this is invalid/weird value from
 687          * calculation, use default Config size.
 688          * Up to 2GB is supported, 2GB would be used if more than that.
 689          */
 690         if (size <= 0)
 691                 gd->ram_size = PHYS_SDRAM_1_SIZE;
 692         else if (DDR_SIZE_2GB_HEX <= size)
 693                 gd->ram_size = DDR_SIZE_2GB_HEX;
 694         else
 695                 gd->ram_size = (u32)size;
 696
 697         /* setup the dram info within bd */
 698         dram_init_banksize();
 699
 700         if (of_sdram_firewall_setup(gd->fdt_blob))
 701                 puts("FW: Error Configuring Firewall\n");
 702
 703         if (sdram_is_ecc_enabled())
 704                 sdram_init_ecc_bits(gd->ram_size);
 705
 706         return 0;
 707 }