2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/fpga_manager.h>
10 #include <asm/arch/sdram.h>
11 #include <asm/arch/system_manager.h>
15 * FIXME: This path is temporary until the SDRAM driver gets
16 * a proper thorough cleanup.
18 #include "../../../board/altera/socfpga/qts/sdram_config.h"
20 /* define constant for 4G memory - used for SDRAM errata workaround */
21 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
23 DECLARE_GLOBAL_DATA_PTR;
25 static struct socfpga_system_manager *sysmgr_regs =
26 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
27 static struct socfpga_sdr_ctrl *sdr_ctrl =
28 (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
30 static int compute_errata_rows(unsigned long long memsize, int cs, int width,
31 int rows, int banks, int cols)
33 unsigned long long newrows;
37 debug("workaround rows - memsize %lld\n", memsize);
38 debug("workaround rows - cs %d\n", cs);
39 debug("workaround rows - width %d\n", width);
40 debug("workaround rows - rows %d\n", rows);
41 debug("workaround rows - banks %d\n", banks);
42 debug("workaround rows - cols %d\n", cols);
44 newrows = lldiv(memsize, (cs * (width / 8)));
45 debug("rows workaround - term1 %lld\n", newrows);
47 newrows = lldiv(newrows, ((1 << banks) * (1 << cols)));
48 debug("rows workaround - term2 %lld\n", newrows);
50 /* Compute the hamming weight - same as number of bits set.
51 * Need to see if result is ordinal power of 2 before
52 * attempting log2 of result.
54 bits = hweight32(newrows);
56 debug("rows workaround - bits %d\n", bits);
59 printf("SDRAM workaround failed, bits set %d\n", bits);
63 if (newrows > UINT_MAX) {
64 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
68 inewrowslog2 = __ilog2((unsigned int)newrows);
70 debug("rows workaround - ilog2 %d, %d\n", inewrowslog2,
73 if (inewrowslog2 == -1) {
74 printf("SDRAM workaround failed, newrows %d\n", (int)newrows);
81 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
82 static void sdram_set_rule(struct sdram_prot_rule *prule)
84 uint32_t lo_addr_bits;
85 uint32_t hi_addr_bits;
86 int ruleno = prule->rule;
89 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
91 /* Obtain the address bits */
92 lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
93 hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
95 debug("sdram set rule start %x, %lld\n", lo_addr_bits,
97 debug("sdram set rule end %x, %lld\n", hi_addr_bits,
100 /* Set rule addresses */
101 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
103 /* Set rule protection ids */
104 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
105 &sdr_ctrl->prot_rule_id);
107 /* Set the rule data */
108 writel(prule->security | (prule->valid << 2) |
109 (prule->portmask << 3) | (prule->result << 13),
110 &sdr_ctrl->prot_rule_data);
113 writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
115 /* Set rule number to 0 by default */
116 writel(0, &sdr_ctrl->prot_rule_rdwr);
119 static void sdram_get_rule(struct sdram_prot_rule *prule)
124 int ruleno = prule->rule;
127 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
128 writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
130 /* Get the addresses */
131 addr = readl(&sdr_ctrl->prot_rule_addr);
132 prule->sdram_start = (addr & 0xFFF) << 20;
133 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
135 /* Get the configured protection IDs */
136 id = readl(&sdr_ctrl->prot_rule_id);
137 prule->lo_prot_id = id & 0xFFF;
138 prule->hi_prot_id = (id >> 12) & 0xFFF;
140 /* Get protection data */
141 data = readl(&sdr_ctrl->prot_rule_data);
143 prule->security = data & 0x3;
144 prule->valid = (data >> 2) & 0x1;
145 prule->portmask = (data >> 3) & 0x3FF;
146 prule->result = (data >> 13) & 0x1;
149 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
151 struct sdram_prot_rule rule;
154 /* Start with accepting all SDRAM transaction */
155 writel(0x0, &sdr_ctrl->protport_default);
157 /* Clear all protection rules for warm boot case */
158 memset(&rule, 0, sizeof(struct sdram_prot_rule));
160 for (rules = 0; rules < 20; rules++) {
162 sdram_set_rule(&rule);
165 /* new rule: accept SDRAM */
166 rule.sdram_start = sdram_start;
167 rule.sdram_end = sdram_end;
168 rule.lo_prot_id = 0x0;
169 rule.hi_prot_id = 0xFFF;
170 rule.portmask = 0x3FF;
177 sdram_set_rule(&rule);
179 /* default rule: reject everything */
180 writel(0x3ff, &sdr_ctrl->protport_default);
183 static void sdram_dump_protection_config(void)
185 struct sdram_prot_rule rule;
188 debug("SDRAM Prot rule, default %x\n",
189 readl(&sdr_ctrl->protport_default));
191 for (rules = 0; rules < 20; rules++) {
192 sdram_get_rule(&rule);
193 debug("Rule %d, rules ...\n", rules);
194 debug(" sdram start %llx\n", rule.sdram_start);
195 debug(" sdram end %llx\n", rule.sdram_end);
196 debug(" low prot id %d, hi prot id %d\n",
199 debug(" portmask %x\n", rule.portmask);
200 debug(" security %d\n", rule.security);
201 debug(" result %d\n", rule.result);
202 debug(" valid %d\n", rule.valid);
206 /* Function to write to register and verify the write */
207 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
209 #ifndef SDRAM_MMR_SKIP_VERIFY
212 debug(" Write - Address ");
213 debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
214 /* Write to register */
215 writel(reg_value, addr);
216 #ifndef SDRAM_MMR_SKIP_VERIFY
217 debug(" Read and verify...");
218 /* Read back the wrote value */
219 reg_value1 = readl(addr);
220 /* Indicate failure if value not matched */
221 if (reg_value1 != reg_value) {
222 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
223 (u32)addr, reg_value, reg_value1);
227 #endif /* SDRAM_MMR_SKIP_VERIFY */
231 static void set_sdr_ctrlcfg(void)
235 debug("\nConfiguring CTRLCFG\n");
236 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
237 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
238 SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
239 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
240 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
241 SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
244 /* SDRAM Failure When Accessing Non-Existent Memory
245 * Set the addrorder field of the SDRAM control register
246 * based on the CSBITs setting.
248 switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
250 addrorder = 0; /* chip, row, bank, column */
251 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
252 debug("INFO: Changing address order to 0 (chip, row, \
256 addrorder = 2; /* row, chip, bank, column */
257 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
258 debug("INFO: Changing address order to 2 (row, chip, \
262 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
266 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
267 addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
269 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
270 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
271 SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
273 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
274 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
275 SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
277 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
278 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
279 SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
281 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
282 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
283 SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
285 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
286 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
287 SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
289 clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
290 CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
291 SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
294 static void set_sdr_dram_timing1(void)
296 debug("Configuring DRAMTIMING1\n");
297 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
298 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
299 SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
301 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
302 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
303 SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
305 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
306 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
307 SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
309 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
310 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
311 SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
313 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
314 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
315 SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
317 clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
318 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
319 SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
322 static void set_sdr_dram_timing2(void)
324 debug("Configuring DRAMTIMING2\n");
325 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
326 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
327 SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
329 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
330 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
331 SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
333 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
334 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
335 SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
337 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
338 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
339 SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
341 clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
342 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
343 SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
346 static void set_sdr_dram_timing3(void)
348 debug("Configuring DRAMTIMING3\n");
349 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
350 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
351 SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
353 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
354 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
355 SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
357 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
358 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
359 SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
361 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
362 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
363 SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
365 clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
366 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
367 SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
370 static void set_sdr_dram_timing4(void)
372 debug("Configuring DRAMTIMING4\n");
373 clrsetbits_le32(&sdr_ctrl->dram_timing4,
374 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
375 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
376 SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
378 clrsetbits_le32(&sdr_ctrl->dram_timing4,
379 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
380 CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
381 SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
384 static void set_sdr_dram_lowpwr_timing(void)
386 debug("Configuring LOWPWRTIMING\n");
387 clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
388 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
389 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
390 SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
392 clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
393 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
394 CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
395 SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
398 static void set_sdr_addr_rw(void)
400 int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
402 int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
403 int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
404 int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
405 unsigned long long workaround_memsize = MEMSIZE_4G;
407 debug("Configuring DRAMADDRW\n");
408 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
409 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
410 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
412 * SDRAM Failure When Accessing Non-Existent Memory
413 * Update Preloader to artificially increase the number of rows so
414 * that the memory thinks it has 4GB of RAM.
416 rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks,
419 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
420 rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
422 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
423 CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
424 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
425 /* SDRAM Failure When Accessing Non-Existent Memory
426 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
427 * log2(number of chip select bits). Since there's only
428 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
429 * which is the same as "chip selects" - 1.
431 clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
432 (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
433 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
436 static void set_sdr_static_cfg(void)
438 debug("Configuring STATICCFG\n");
439 clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
440 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
441 SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
443 clrsetbits_le32(&sdr_ctrl->static_cfg,
444 SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
445 CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
446 SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
449 static void set_sdr_fifo_cfg(void)
451 debug("Configuring FIFOCFG\n");
452 clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
453 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
454 SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
456 clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
457 CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
458 SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
461 static void set_sdr_mp_weight(void)
463 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
464 clrsetbits_le32(&sdr_ctrl->mp_weight0,
465 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
466 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
467 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
469 clrsetbits_le32(&sdr_ctrl->mp_weight1,
470 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
471 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
472 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
474 clrsetbits_le32(&sdr_ctrl->mp_weight1,
475 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
476 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
477 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
479 clrsetbits_le32(&sdr_ctrl->mp_weight2,
480 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
481 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
482 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
484 clrsetbits_le32(&sdr_ctrl->mp_weight3,
485 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
486 CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
487 SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
490 static void set_sdr_mp_pacing(void)
492 debug("Configuring MPPACING_MPPACING_0\n");
493 clrsetbits_le32(&sdr_ctrl->mp_pacing0,
494 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
495 CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
496 SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
498 clrsetbits_le32(&sdr_ctrl->mp_pacing1,
499 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
500 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
501 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
503 clrsetbits_le32(&sdr_ctrl->mp_pacing1,
504 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
505 CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
506 SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
508 clrsetbits_le32(&sdr_ctrl->mp_pacing2,
509 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
510 CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
511 SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
513 clrsetbits_le32(&sdr_ctrl->mp_pacing3,
514 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
515 CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
516 SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
519 static void set_sdr_mp_threshold(void)
521 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
522 clrsetbits_le32(&sdr_ctrl->mp_threshold0,
523 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
524 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
525 SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
527 clrsetbits_le32(&sdr_ctrl->mp_threshold1,
528 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
529 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
530 SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
532 clrsetbits_le32(&sdr_ctrl->mp_threshold2,
533 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
534 CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
535 SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
539 /* Function to initialize SDRAM MMR */
540 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
542 unsigned long reg_value;
543 unsigned long status = 0;
545 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
546 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
547 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
548 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
549 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
551 writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
552 &sysmgr_regs->iswgrp_handoff[4]);
555 set_sdr_dram_timing1();
556 set_sdr_dram_timing2();
557 set_sdr_dram_timing3();
558 set_sdr_dram_timing4();
559 set_sdr_dram_lowpwr_timing();
562 debug("Configuring DRAMIFWIDTH\n");
563 clrsetbits_le32(&sdr_ctrl->dram_if_width,
564 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
565 CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
566 SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
568 debug("Configuring DRAMDEVWIDTH\n");
569 clrsetbits_le32(&sdr_ctrl->dram_dev_width,
570 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
571 CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
572 SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
574 debug("Configuring LOWPWREQ\n");
575 clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
576 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
577 CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
578 SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
580 debug("Configuring DRAMINTR\n");
581 clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
582 CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
583 SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
585 set_sdr_static_cfg();
587 debug("Configuring CTRLWIDTH\n");
588 clrsetbits_le32(&sdr_ctrl->ctrl_width,
589 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
590 CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
591 SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
593 debug("Configuring PORTCFG\n");
594 clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
595 CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
596 SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
600 debug("Configuring MPPRIORITY\n");
601 clrsetbits_le32(&sdr_ctrl->mp_priority,
602 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
603 CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
604 SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
608 set_sdr_mp_threshold();
610 debug("Configuring PHYCTRL_PHYCTRL_0\n");
611 setbits_le32(&sdr_ctrl->phy_ctrl0,
612 CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
614 debug("Configuring CPORTWIDTH\n");
615 clrsetbits_le32(&sdr_ctrl->cport_width,
616 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
617 CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
618 SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
619 debug(" Write - Address ");
620 debug("0x%08x Data 0x%08x\n",
621 (unsigned)(&sdr_ctrl->cport_width),
622 (unsigned)reg_value);
623 reg_value = readl(&sdr_ctrl->cport_width);
624 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
626 debug("Configuring CPORTWMAP\n");
627 clrsetbits_le32(&sdr_ctrl->cport_wmap,
628 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
629 CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
630 SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
631 debug(" Write - Address ");
632 debug("0x%08x Data 0x%08x\n",
633 (unsigned)(&sdr_ctrl->cport_wmap),
634 (unsigned)reg_value);
635 reg_value = readl(&sdr_ctrl->cport_wmap);
636 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
638 debug("Configuring CPORTRMAP\n");
639 clrsetbits_le32(&sdr_ctrl->cport_rmap,
640 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
641 CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
642 SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
643 debug(" Write - Address ");
644 debug("0x%08x Data 0x%08x\n",
645 (unsigned)(&sdr_ctrl->cport_rmap),
646 (unsigned)reg_value);
647 reg_value = readl(&sdr_ctrl->cport_rmap);
648 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
650 debug("Configuring RFIFOCMAP\n");
651 clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
652 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
653 CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
654 SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
655 debug(" Write - Address ");
656 debug("0x%08x Data 0x%08x\n",
657 (unsigned)(&sdr_ctrl->rfifo_cmap),
658 (unsigned)reg_value);
659 reg_value = readl(&sdr_ctrl->rfifo_cmap);
660 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
662 debug("Configuring WFIFOCMAP\n");
663 reg_value = readl(&sdr_ctrl->wfifo_cmap);
664 clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
665 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
666 CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
667 SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
668 debug(" Write - Address ");
669 debug("0x%08x Data 0x%08x\n",
670 (unsigned)(&sdr_ctrl->wfifo_cmap),
671 (unsigned)reg_value);
672 reg_value = readl(&sdr_ctrl->wfifo_cmap);
673 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
675 debug("Configuring CPORTRDWR\n");
676 clrsetbits_le32(&sdr_ctrl->cport_rdwr,
677 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
678 CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
679 SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
680 debug(" Write - Address ");
681 debug("0x%08x Data 0x%08x\n",
682 (unsigned)(&sdr_ctrl->cport_rdwr),
683 (unsigned)reg_value);
684 reg_value = readl(&sdr_ctrl->cport_rdwr);
685 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
687 debug("Configuring DRAMODT\n");
688 clrsetbits_le32(&sdr_ctrl->dram_odt,
689 SDR_CTRLGRP_DRAMODT_READ_MASK,
690 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
691 SDR_CTRLGRP_DRAMODT_READ_LSB);
693 clrsetbits_le32(&sdr_ctrl->dram_odt,
694 SDR_CTRLGRP_DRAMODT_WRITE_MASK,
695 CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
696 SDR_CTRLGRP_DRAMODT_WRITE_LSB);
698 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
699 writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
700 &sysmgr_regs->iswgrp_handoff[3]);
702 /* only enable if the FPGA is programmed */
703 if (fpgamgr_test_fpga_ready()) {
704 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
705 CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
711 /* Restore the SDR PHY Register if valid */
712 if (sdr_phy_reg != 0xffffffff)
713 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
715 /***** Final step - apply configuration changes *****/
716 debug("Configuring STATICCFG_\n");
717 clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
718 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
719 debug(" Write - Address ");
720 debug("0x%08x Data 0x%08x\n",
721 (unsigned)(&sdr_ctrl->static_cfg),
722 (unsigned)reg_value);
723 reg_value = readl(&sdr_ctrl->static_cfg);
724 debug(" Read value without verify 0x%08x\n", (unsigned)reg_value);
726 sdram_set_protection_config(0, sdram_calculate_size());
728 sdram_dump_protection_config();
734 * To calculate SDRAM device size based on SDRAM controller parameters.
735 * Size is specified in bytes.
738 * This function is compiled and linked into the preloader and
739 * Uboot (there may be others). So if this function changes, the Preloader
740 * and UBoot must be updated simultaneously.
742 unsigned long sdram_calculate_size(void)
745 unsigned long row, bank, col, cs, width;
747 temp = readl(&sdr_ctrl->dram_addrw);
748 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
749 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
751 /* SDRAM Failure When Accessing Non-Existent Memory
752 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
753 * since the FB specifies we modify ROWBITs to work around SDRAM
756 * If the stored handoff value for rows is 0, it probably means
757 * the preloader is older than UBoot. Use the
758 * #define from the SOCEDS Tools per Crucible review
759 * uboot-socfpga-204. Note that this is not a supported
760 * configuration and is not tested. The customer
761 * should be using preloader and uboot built from the
764 row = readl(&sysmgr_regs->iswgrp_handoff[4]);
766 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
767 /* If the stored handoff value for rows is greater than
768 * the field width in the sdr.dramaddrw register then
769 * something is very wrong. Revert to using the the #define
770 * value handed off by the SOCEDS tool chain instead of
771 * using a broken value.
774 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
776 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
777 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
779 /* SDRAM Failure When Accessing Non-Existent Memory
780 * Use CSBITs from Quartus/QSys to calculate SDRAM size
781 * since the FB specifies we modify CSBITs to work around SDRAM
784 cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
785 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
788 cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
790 width = readl(&sdr_ctrl->dram_if_width);
791 /* ECC would not be calculated as its not addressible */
792 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
794 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
797 /* calculate the SDRAM size base on this info */
798 temp = 1 << (row + bank + col);
799 temp = temp * cs * (width / 8);
801 debug("sdram_calculate_memory returns %ld\n", temp);