drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 struct sdram_prot_rule {
  16         u32     sdram_start;    /* SDRAM start address */
  17         u32     sdram_end;      /* SDRAM end address */
  18         u32     rule;           /* SDRAM protection rule number: 0-19 */
  19         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  20
  21         u32     security;
  22         u32     portmask;
  23         u32     result;
  24         u32     lo_prot_id;
  25         u32     hi_prot_id;
  26 };
  27
  28 static struct socfpga_system_manager *sysmgr_regs =
  29         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  30 static struct socfpga_sdr_ctrl *sdr_ctrl =
  31         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  32
  33 /**
  34  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  35  * @cfg:        SDRAM controller configuration data
  36  *
  37  * SDRAM Failure happens when accessing non-existent memory. Artificially
  38  * increase the number of rows so that the memory controller thinks it has
  39  * 4GB of RAM. This function returns such amount of rows.
  40  */
  41 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  42 {
  43         /* Define constant for 4G memory - used for SDRAM errata workaround */
  44 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  45         const unsigned long long memsize = MEMSIZE_4G;
  46         const unsigned int cs =
  47                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  48                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  49         const unsigned int rows =
  50                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  51                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  52         const unsigned int banks =
  53                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  54                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  55         const unsigned int cols =
  56                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  57                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  58         const unsigned int width = 8;
  59
  60         unsigned long long newrows;
  61         int bits, inewrowslog2;
  62
  63         debug("workaround rows - memsize %lld\n", memsize);
  64         debug("workaround rows - cs        %d\n", cs);
  65         debug("workaround rows - width     %d\n", width);
  66         debug("workaround rows - rows      %d\n", rows);
  67         debug("workaround rows - banks     %d\n", banks);
  68         debug("workaround rows - cols      %d\n", cols);
  69
  70         newrows = lldiv(memsize, cs * (width / 8));
  71         debug("rows workaround - term1 %lld\n", newrows);
  72
  73         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  74         debug("rows workaround - term2 %lld\n", newrows);
  75
  76         /*
  77          * Compute the hamming weight - same as number of bits set.
  78          * Need to see if result is ordinal power of 2 before
  79          * attempting log2 of result.
  80          */
  81         bits = generic_hweight32(newrows);
  82
  83         debug("rows workaround - bits %d\n", bits);
  84
  85         if (bits != 1) {
  86                 printf("SDRAM workaround failed, bits set %d\n", bits);
  87                 return rows;
  88         }
  89
  90         if (newrows > UINT_MAX) {
  91                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  92                 return rows;
  93         }
  94
  95         inewrowslog2 = __ilog2(newrows);
  96
  97         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
  98
  99         if (inewrowslog2 == -1) {
 100                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 101                 return rows;
 102         }
 103
 104         return inewrowslog2;
 105 }
 106
 107 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 108 static void sdram_set_rule(struct sdram_prot_rule *prule)
 109 {
 110         u32 lo_addr_bits;
 111         u32 hi_addr_bits;
 112         int ruleno = prule->rule;
 113
 114         /* Select the rule */
 115         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 116
 117         /* Obtain the address bits */
 118         lo_addr_bits = prule->sdram_start >> 20ULL;
 119         hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 120
 121         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 122               prule->sdram_start);
 123         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 124               prule->sdram_end);
 125
 126         /* Set rule addresses */
 127         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 128
 129         /* Set rule protection ids */
 130         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 131                &sdr_ctrl->prot_rule_id);
 132
 133         /* Set the rule data */
 134         writel(prule->security | (prule->valid << 2) |
 135                (prule->portmask << 3) | (prule->result << 13),
 136                &sdr_ctrl->prot_rule_data);
 137
 138         /* write the rule */
 139         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 140
 141         /* Set rule number to 0 by default */
 142         writel(0, &sdr_ctrl->prot_rule_rdwr);
 143 }
 144
 145 static void sdram_get_rule(struct sdram_prot_rule *prule)
 146 {
 147         u32 addr;
 148         u32 id;
 149         u32 data;
 150         int ruleno = prule->rule;
 151
 152         /* Read the rule */
 153         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 154         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 155
 156         /* Get the addresses */
 157         addr = readl(&sdr_ctrl->prot_rule_addr);
 158         prule->sdram_start = (addr & 0xFFF) << 20;
 159         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 160
 161         /* Get the configured protection IDs */
 162         id = readl(&sdr_ctrl->prot_rule_id);
 163         prule->lo_prot_id = id & 0xFFF;
 164         prule->hi_prot_id = (id >> 12) & 0xFFF;
 165
 166         /* Get protection data */
 167         data = readl(&sdr_ctrl->prot_rule_data);
 168
 169         prule->security = data & 0x3;
 170         prule->valid = (data >> 2) & 0x1;
 171         prule->portmask = (data >> 3) & 0x3FF;
 172         prule->result = (data >> 13) & 0x1;
 173 }
 174
 175 static void
 176 sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
 177 {
 178         struct sdram_prot_rule rule;
 179         int rules;
 180
 181         /* Start with accepting all SDRAM transaction */
 182         writel(0x0, &sdr_ctrl->protport_default);
 183
 184         /* Clear all protection rules for warm boot case */
 185         memset(&rule, 0, sizeof(rule));
 186
 187         for (rules = 0; rules < 20; rules++) {
 188                 rule.rule = rules;
 189                 sdram_set_rule(&rule);
 190         }
 191
 192         /* new rule: accept SDRAM */
 193         rule.sdram_start = sdram_start;
 194         rule.sdram_end = sdram_end;
 195         rule.lo_prot_id = 0x0;
 196         rule.hi_prot_id = 0xFFF;
 197         rule.portmask = 0x3FF;
 198         rule.security = 0x3;
 199         rule.result = 0;
 200         rule.valid = 1;
 201         rule.rule = 0;
 202
 203         /* set new rule */
 204         sdram_set_rule(&rule);
 205
 206         /* default rule: reject everything */
 207         writel(0x3ff, &sdr_ctrl->protport_default);
 208 }
 209
 210 static void sdram_dump_protection_config(void)
 211 {
 212         struct sdram_prot_rule rule;
 213         int rules;
 214
 215         debug("SDRAM Prot rule, default %x\n",
 216               readl(&sdr_ctrl->protport_default));
 217
 218         for (rules = 0; rules < 20; rules++) {
 219                 rule.rule = rules;
 220                 sdram_get_rule(&rule);
 221                 debug("Rule %d, rules ...\n", rules);
 222                 debug("    sdram start %x\n", rule.sdram_start);
 223                 debug("    sdram end   %x\n", rule.sdram_end);
 224                 debug("    low prot id %d, hi prot id %d\n",
 225                       rule.lo_prot_id,
 226                       rule.hi_prot_id);
 227                 debug("    portmask %x\n", rule.portmask);
 228                 debug("    security %d\n", rule.security);
 229                 debug("    result %d\n", rule.result);
 230                 debug("    valid %d\n", rule.valid);
 231         }
 232 }
 233
 234 /**
 235  * sdram_write_verify() - write to register and verify the write.
 236  * @addr:       Register address
 237  * @val:        Value to be written and verified
 238  *
 239  * This function writes to a register, reads back the value and compares
 240  * the result with the written value to check if the data match.
 241  */
 242 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 243 {
 244         u32 rval;
 245
 246         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 247         writel(val, addr);
 248
 249         debug("   Read and verify...");
 250         rval = readl(addr);
 251         if (rval != val) {
 252                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 253                       addr, val, rval);
 254                 return -EINVAL;
 255         }
 256
 257         debug("correct!\n");
 258         return 0;
 259 }
 260
 261 /**
 262  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 263  * @cfg:        SDRAM controller configuration data
 264  *
 265  * Return the value of DRAM CTRLCFG register.
 266  */
 267 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 268 {
 269         const u32 csbits =
 270                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 271                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 272         u32 addrorder =
 273                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 274                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 275
 276         u32 ctrl_cfg = cfg->ctrl_cfg;
 277
 278         /*
 279          * SDRAM Failure When Accessing Non-Existent Memory
 280          * Set the addrorder field of the SDRAM control register
 281          * based on the CSBITs setting.
 282          */
 283         if (csbits == 1) {
 284                 if (addrorder != 0)
 285                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 286                 addrorder = 0;
 287         } else if (csbits == 2) {
 288                 if (addrorder != 2)
 289                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 290                 addrorder = 2;
 291         }
 292
 293         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 294         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 295
 296         return ctrl_cfg;
 297 }
 298
 299 /**
 300  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 301  * @cfg:        SDRAM controller configuration data
 302  *
 303  * Return the value of DRAM ADDRW register.
 304  */
 305 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 306 {
 307         /*
 308          * SDRAM Failure When Accessing Non-Existent Memory
 309          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 310          * log2(number of chip select bits). Since there's only
 311          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 312          * which is the same as "chip selects" - 1.
 313          */
 314         const int rows = get_errata_rows(cfg);
 315         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 316
 317         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 318 }
 319
 320 /**
 321  * sdr_load_regs() - Load SDRAM controller registers
 322  * @cfg:        SDRAM controller configuration data
 323  *
 324  * This function loads the register values into the SDRAM controller block.
 325  */
 326 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 327 {
 328         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 329         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 330
 331         debug("\nConfiguring CTRLCFG\n");
 332         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 333
 334         debug("Configuring DRAMTIMING1\n");
 335         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 336
 337         debug("Configuring DRAMTIMING2\n");
 338         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 339
 340         debug("Configuring DRAMTIMING3\n");
 341         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 342
 343         debug("Configuring DRAMTIMING4\n");
 344         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 345
 346         debug("Configuring LOWPWRTIMING\n");
 347         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 348
 349         debug("Configuring DRAMADDRW\n");
 350         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 351
 352         debug("Configuring DRAMIFWIDTH\n");
 353         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 354
 355         debug("Configuring DRAMDEVWIDTH\n");
 356         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 357
 358         debug("Configuring LOWPWREQ\n");
 359         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 360
 361         debug("Configuring DRAMINTR\n");
 362         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 363
 364         debug("Configuring STATICCFG\n");
 365         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 366
 367         debug("Configuring CTRLWIDTH\n");
 368         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 369
 370         debug("Configuring PORTCFG\n");
 371         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 372
 373         debug("Configuring FIFOCFG\n");
 374         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 375
 376         debug("Configuring MPPRIORITY\n");
 377         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 378
 379         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 380         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 381         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 382         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 383         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 384
 385         debug("Configuring MPPACING_MPPACING_0\n");
 386         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 387         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 388         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 389         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 390
 391         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 392         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 393         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 394         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 395
 396         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 397         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 398
 399         debug("Configuring CPORTWIDTH\n");
 400         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 401
 402         debug("Configuring CPORTWMAP\n");
 403         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 404
 405         debug("Configuring CPORTRMAP\n");
 406         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 407
 408         debug("Configuring RFIFOCMAP\n");
 409         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 410
 411         debug("Configuring WFIFOCMAP\n");
 412         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 413
 414         debug("Configuring CPORTRDWR\n");
 415         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 416
 417         debug("Configuring DRAMODT\n");
 418         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 419
 420         debug("Configuring EXTRATIME1\n");
 421         writel(cfg->extratime1, &sdr_ctrl->extratime1);
 422 }
 423
 424 /**
 425  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 426  * @sdr_phy_reg:        Value of the PHY control register 0
 427  *
 428  * Initialize the SDRAM MMR.
 429  */
 430 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 431 {
 432         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 433         const unsigned int rows =
 434                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 435                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 436         int ret;
 437
 438         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 439
 440         sdr_load_regs(cfg);
 441
 442         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 443         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 444
 445         /* only enable if the FPGA is programmed */
 446         if (fpgamgr_test_fpga_ready()) {
 447                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 448                                          cfg->fpgaport_rst);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         /* Restore the SDR PHY Register if valid */
 454         if (sdr_phy_reg != 0xffffffff)
 455                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 456
 457         /* Final step - apply configuration changes */
 458         debug("Configuring STATICCFG\n");
 459         clrsetbits_le32(&sdr_ctrl->static_cfg,
 460                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 461                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 462
 463         sdram_set_protection_config(0, sdram_calculate_size() - 1);
 464
 465         sdram_dump_protection_config();
 466
 467         return 0;
 468 }
 469
 470 /**
 471  * sdram_calculate_size() - Calculate SDRAM size
 472  *
 473  * Calculate SDRAM device size based on SDRAM controller parameters.
 474  * Size is specified in bytes.
 475  */
 476 unsigned long sdram_calculate_size(void)
 477 {
 478         unsigned long temp;
 479         unsigned long row, bank, col, cs, width;
 480         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 481         const unsigned int csbits =
 482                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 483                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 484         const unsigned int rowbits =
 485                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 486                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 487
 488         temp = readl(&sdr_ctrl->dram_addrw);
 489         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 490                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 491
 492         /*
 493          * SDRAM Failure When Accessing Non-Existent Memory
 494          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 495          * since the FB specifies we modify ROWBITs to work around SDRAM
 496          * controller issue.
 497          */
 498         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 499         if (row == 0)
 500                 row = rowbits;
 501         /*
 502          * If the stored handoff value for rows is greater than
 503          * the field width in the sdr.dramaddrw register then
 504          * something is very wrong. Revert to using the the #define
 505          * value handed off by the SOCEDS tool chain instead of
 506          * using a broken value.
 507          */
 508         if (row > 31)
 509                 row = rowbits;
 510
 511         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 512                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 513
 514         /*
 515          * SDRAM Failure When Accessing Non-Existent Memory
 516          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 517          * since the FB specifies we modify CSBITs to work around SDRAM
 518          * controller issue.
 519          */
 520         cs = csbits;
 521
 522         width = readl(&sdr_ctrl->dram_if_width);
 523
 524         /* ECC would not be calculated as its not addressible */
 525         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 526                 width = 32;
 527         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 528                 width = 16;
 529
 530         /* calculate the SDRAM size base on this info */
 531         temp = 1 << (row + bank + col);
 532         temp = temp * cs * (width  / 8);
 533
 534         debug("%s returns %ld\n", __func__, temp);
 535
 536         return temp;
 537 }