drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <div64.h>
   8 #include <watchdog.h>
   9 #include <asm/arch/fpga_manager.h>
  10 #include <asm/arch/sdram.h>
  11 #include <asm/arch/sdram_config.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 /* define constant for 4G memory - used for SDRAM errata workaround */
  16 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 static struct socfpga_system_manager *sysmgr_regs =
  21         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  22 static struct socfpga_sdr_ctrl *sdr_ctrl =
  23         (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
  24
  25 static int compute_errata_rows(unsigned long long memsize, int cs, int width,
  26                                int rows, int banks, int cols)
  27 {
  28         unsigned long long newrows;
  29         int inewrowslog2;
  30         int bits;
  31
  32         debug("workaround rows - memsize %lld\n", memsize);
  33         debug("workaround rows - cs        %d\n", cs);
  34         debug("workaround rows - width     %d\n", width);
  35         debug("workaround rows - rows      %d\n", rows);
  36         debug("workaround rows - banks     %d\n", banks);
  37         debug("workaround rows - cols      %d\n", cols);
  38
  39         newrows = lldiv(memsize, (cs * (width / 8)));
  40         debug("rows workaround - term1 %lld\n", newrows);
  41
  42         newrows = lldiv(newrows, ((1 << banks) * (1 << cols)));
  43         debug("rows workaround - term2 %lld\n", newrows);
  44
  45         /* Compute the hamming weight - same as number of bits set.
  46          * Need to see if result is ordinal power of 2 before
  47          * attempting log2 of result.
  48          */
  49         bits = hweight32(newrows);
  50
  51         debug("rows workaround - bits %d\n", bits);
  52
  53         if (bits != 1) {
  54                 printf("SDRAM workaround failed, bits set %d\n", bits);
  55                 return rows;
  56         }
  57
  58         if (newrows > UINT_MAX) {
  59                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  60                 return rows;
  61         }
  62
  63         inewrowslog2 = __ilog2((unsigned int)newrows);
  64
  65         debug("rows workaround - ilog2 %d, %d\n", inewrowslog2,
  66                (int)newrows);
  67
  68         if (inewrowslog2 == -1) {
  69                 printf("SDRAM workaround failed, newrows %d\n", (int)newrows);
  70                 return rows;
  71         }
  72
  73         return inewrowslog2;
  74 }
  75
  76 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
  77 static void sdram_set_rule(struct sdram_prot_rule *prule)
  78 {
  79         uint32_t lo_addr_bits;
  80         uint32_t hi_addr_bits;
  81         int ruleno = prule->rule;
  82
  83         /* Select the rule */
  84         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
  85
  86         /* Obtain the address bits */
  87         lo_addr_bits = (uint32_t)(((prule->sdram_start) >> 20ULL) & 0xFFF);
  88         hi_addr_bits = (uint32_t)((((prule->sdram_end-1) >> 20ULL)) & 0xFFF);
  89
  90         debug("sdram set rule start %x, %lld\n", lo_addr_bits,
  91               prule->sdram_start);
  92         debug("sdram set rule end   %x, %lld\n", hi_addr_bits,
  93               prule->sdram_end);
  94
  95         /* Set rule addresses */
  96         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
  97
  98         /* Set rule protection ids */
  99         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 100                &sdr_ctrl->prot_rule_id);
 101
 102         /* Set the rule data */
 103         writel(prule->security | (prule->valid << 2) |
 104                (prule->portmask << 3) | (prule->result << 13),
 105                &sdr_ctrl->prot_rule_data);
 106
 107         /* write the rule */
 108         writel(ruleno | (1L << 5), &sdr_ctrl->prot_rule_rdwr);
 109
 110         /* Set rule number to 0 by default */
 111         writel(0, &sdr_ctrl->prot_rule_rdwr);
 112 }
 113
 114 static void sdram_get_rule(struct sdram_prot_rule *prule)
 115 {
 116         uint32_t addr;
 117         uint32_t id;
 118         uint32_t data;
 119         int ruleno = prule->rule;
 120
 121         /* Read the rule */
 122         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 123         writel(ruleno | (1L << 6), &sdr_ctrl->prot_rule_rdwr);
 124
 125         /* Get the addresses */
 126         addr = readl(&sdr_ctrl->prot_rule_addr);
 127         prule->sdram_start = (addr & 0xFFF) << 20;
 128         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 129
 130         /* Get the configured protection IDs */
 131         id = readl(&sdr_ctrl->prot_rule_id);
 132         prule->lo_prot_id = id & 0xFFF;
 133         prule->hi_prot_id = (id >> 12) & 0xFFF;
 134
 135         /* Get protection data */
 136         data = readl(&sdr_ctrl->prot_rule_data);
 137
 138         prule->security = data & 0x3;
 139         prule->valid = (data >> 2) & 0x1;
 140         prule->portmask = (data >> 3) & 0x3FF;
 141         prule->result = (data >> 13) & 0x1;
 142 }
 143
 144 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
 145 {
 146         struct sdram_prot_rule rule;
 147         int rules;
 148
 149         /* Start with accepting all SDRAM transaction */
 150         writel(0x0, &sdr_ctrl->protport_default);
 151
 152         /* Clear all protection rules for warm boot case */
 153         memset(&rule, 0, sizeof(struct sdram_prot_rule));
 154
 155         for (rules = 0; rules < 20; rules++) {
 156                 rule.rule = rules;
 157                 sdram_set_rule(&rule);
 158         }
 159
 160         /* new rule: accept SDRAM */
 161         rule.sdram_start = sdram_start;
 162         rule.sdram_end = sdram_end;
 163         rule.lo_prot_id = 0x0;
 164         rule.hi_prot_id = 0xFFF;
 165         rule.portmask = 0x3FF;
 166         rule.security = 0x3;
 167         rule.result = 0;
 168         rule.valid = 1;
 169         rule.rule = 0;
 170
 171         /* set new rule */
 172         sdram_set_rule(&rule);
 173
 174         /* default rule: reject everything */
 175         writel(0x3ff, &sdr_ctrl->protport_default);
 176 }
 177
 178 static void sdram_dump_protection_config(void)
 179 {
 180         struct sdram_prot_rule rule;
 181         int rules;
 182
 183         debug("SDRAM Prot rule, default %x\n",
 184               readl(&sdr_ctrl->protport_default));
 185
 186         for (rules = 0; rules < 20; rules++) {
 187                 sdram_get_rule(&rule);
 188                 debug("Rule %d, rules ...\n", rules);
 189                 debug("    sdram start %llx\n", rule.sdram_start);
 190                 debug("    sdram end   %llx\n", rule.sdram_end);
 191                 debug("    low prot id %d, hi prot id %d\n",
 192                       rule.lo_prot_id,
 193                       rule.hi_prot_id);
 194                 debug("    portmask %x\n", rule.portmask);
 195                 debug("    security %d\n", rule.security);
 196                 debug("    result %d\n", rule.result);
 197                 debug("    valid %d\n", rule.valid);
 198         }
 199 }
 200
 201 /* Function to write to register and verify the write */
 202 static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
 203 {
 204 #ifndef SDRAM_MMR_SKIP_VERIFY
 205         unsigned reg_value1;
 206 #endif
 207         debug("   Write - Address ");
 208         debug("0x%08x Data 0x%08x\n", (u32)addr, reg_value);
 209         /* Write to register */
 210         writel(reg_value, addr);
 211 #ifndef SDRAM_MMR_SKIP_VERIFY
 212         debug("   Read and verify...");
 213         /* Read back the wrote value */
 214         reg_value1 = readl(addr);
 215         /* Indicate failure if value not matched */
 216         if (reg_value1 != reg_value) {
 217                 debug("FAIL - Address 0x%08x Expected 0x%08x Data 0x%08x\n",
 218                       (u32)addr, reg_value, reg_value1);
 219                 return 1;
 220         }
 221         debug("correct!\n");
 222 #endif  /* SDRAM_MMR_SKIP_VERIFY */
 223         return 0;
 224 }
 225
 226 static void set_sdr_ctrlcfg(void)
 227 {
 228         int addrorder;
 229
 230         debug("\nConfiguring CTRLCFG\n");
 231         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
 232                    CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
 233                    SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
 234         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
 235                    CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
 236                    SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
 237
 238
 239         /* SDRAM Failure When Accessing Non-Existent Memory
 240          * Set the addrorder field of the SDRAM control register
 241          * based on the CSBITs setting.
 242          */
 243         switch (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) {
 244         case 1:
 245                 addrorder = 0; /* chip, row, bank, column */
 246                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
 247                         debug("INFO: Changing address order to 0 (chip, row, \
 248                               bank, column)\n");
 249                 break;
 250         case 2:
 251                 addrorder = 2; /* row, chip, bank, column */
 252                 if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
 253                         debug("INFO: Changing address order to 2 (row, chip, \
 254                               bank, column)\n");
 255                 break;
 256         default:
 257                 addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
 258                 break;
 259         }
 260
 261         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
 262                         addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
 263
 264         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
 265                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
 266                         SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
 267
 268         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
 269                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
 270                         SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
 271
 272         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
 273                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
 274                         SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
 275
 276         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
 277                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
 278                         SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
 279
 280         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
 281                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
 282                         SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
 283
 284         clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
 285                         CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
 286                         SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
 287 }
 288
 289 static void set_sdr_dram_timing1(void)
 290 {
 291         debug("Configuring DRAMTIMING1\n");
 292         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
 293                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
 294                         SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
 295
 296         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
 297                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
 298                         SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
 299
 300         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
 301                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
 302                         SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
 303
 304         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
 305                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
 306                         SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
 307
 308         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
 309                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
 310                         SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
 311
 312         clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
 313                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
 314                         SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
 315 }
 316
 317 static void set_sdr_dram_timing2(void)
 318 {
 319         debug("Configuring DRAMTIMING2\n");
 320         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
 321                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
 322                         SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
 323
 324         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
 325                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
 326                         SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
 327
 328         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
 329                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
 330                         SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
 331
 332         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
 333                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
 334                         SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
 335
 336         clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
 337                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
 338                         SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
 339 }
 340
 341 static void set_sdr_dram_timing3(void)
 342 {
 343         debug("Configuring DRAMTIMING3\n");
 344         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
 345                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
 346                         SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
 347
 348         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
 349                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
 350                         SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
 351
 352         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
 353                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
 354                         SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
 355
 356         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
 357                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
 358                         SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
 359
 360         clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
 361                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
 362                         SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
 363 }
 364
 365 static void set_sdr_dram_timing4(void)
 366 {
 367         debug("Configuring DRAMTIMING4\n");
 368         clrsetbits_le32(&sdr_ctrl->dram_timing4,
 369                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
 370                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
 371                         SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
 372
 373         clrsetbits_le32(&sdr_ctrl->dram_timing4,
 374                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
 375                         CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
 376                         SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
 377 }
 378
 379 static void set_sdr_dram_lowpwr_timing(void)
 380 {
 381         debug("Configuring LOWPWRTIMING\n");
 382         clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
 383                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
 384                         CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
 385                         SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
 386
 387         clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
 388                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
 389                         CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
 390                         SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
 391 }
 392
 393 static void set_sdr_addr_rw(void)
 394 {
 395         int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 396         int width = 8;
 397         int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 398         int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
 399         int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
 400         unsigned long long workaround_memsize = MEMSIZE_4G;
 401
 402         debug("Configuring DRAMADDRW\n");
 403         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
 404                         CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
 405                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
 406         /*
 407          * SDRAM Failure When Accessing Non-Existent Memory
 408          * Update Preloader to artificially increase the number of rows so
 409          * that the memory thinks it has 4GB of RAM.
 410          */
 411         rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks,
 412                                    cols);
 413
 414         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
 415                         rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 416
 417         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
 418                         CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
 419                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
 420         /* SDRAM Failure When Accessing Non-Existent Memory
 421          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 422          * log2(number of chip select bits). Since there's only
 423          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 424          * which is the same as "chip selects" - 1.
 425          */
 426         clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
 427                         (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
 428                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
 429 }
 430
 431 static void set_sdr_static_cfg(void)
 432 {
 433         debug("Configuring STATICCFG\n");
 434         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
 435                         CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
 436                         SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
 437
 438         clrsetbits_le32(&sdr_ctrl->static_cfg,
 439                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
 440                         CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
 441                         SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
 442 }
 443
 444 static void set_sdr_fifo_cfg(void)
 445 {
 446         debug("Configuring FIFOCFG\n");
 447         clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
 448                         CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
 449                         SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
 450
 451         clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
 452                         CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
 453                         SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
 454 }
 455
 456 static void set_sdr_mp_weight(void)
 457 {
 458         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 459         clrsetbits_le32(&sdr_ctrl->mp_weight0,
 460                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
 461                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
 462                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
 463
 464         clrsetbits_le32(&sdr_ctrl->mp_weight1,
 465                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
 466                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
 467                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
 468
 469         clrsetbits_le32(&sdr_ctrl->mp_weight1,
 470                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
 471                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
 472                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
 473
 474         clrsetbits_le32(&sdr_ctrl->mp_weight2,
 475                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
 476                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
 477                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
 478
 479         clrsetbits_le32(&sdr_ctrl->mp_weight3,
 480                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
 481                         CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
 482                         SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
 483 }
 484
 485 static void set_sdr_mp_pacing(void)
 486 {
 487         debug("Configuring MPPACING_MPPACING_0\n");
 488         clrsetbits_le32(&sdr_ctrl->mp_pacing0,
 489                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
 490                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
 491                         SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
 492
 493         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 494                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
 495                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
 496                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
 497
 498         clrsetbits_le32(&sdr_ctrl->mp_pacing1,
 499                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
 500                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
 501                         SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
 502
 503         clrsetbits_le32(&sdr_ctrl->mp_pacing2,
 504                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
 505                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
 506                         SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
 507
 508         clrsetbits_le32(&sdr_ctrl->mp_pacing3,
 509                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
 510                         CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
 511                         SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
 512 }
 513
 514 static void set_sdr_mp_threshold(void)
 515 {
 516         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 517         clrsetbits_le32(&sdr_ctrl->mp_threshold0,
 518                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
 519                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
 520                         SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
 521
 522         clrsetbits_le32(&sdr_ctrl->mp_threshold1,
 523                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
 524                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
 525                         SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
 526
 527         clrsetbits_le32(&sdr_ctrl->mp_threshold2,
 528                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
 529                         CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
 530                         SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
 531 }
 532
 533
 534 /* Function to initialize SDRAM MMR */
 535 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
 536 {
 537         unsigned long reg_value;
 538         unsigned long status = 0;
 539
 540 #if defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS) && \
 541 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS) && \
 542 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS) && \
 543 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS) && \
 544 defined(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS)
 545
 546         writel(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS,
 547                &sysmgr_regs->iswgrp_handoff[4]);
 548 #endif
 549         set_sdr_ctrlcfg();
 550         set_sdr_dram_timing1();
 551         set_sdr_dram_timing2();
 552         set_sdr_dram_timing3();
 553         set_sdr_dram_timing4();
 554         set_sdr_dram_lowpwr_timing();
 555         set_sdr_addr_rw();
 556
 557         debug("Configuring DRAMIFWIDTH\n");
 558         clrsetbits_le32(&sdr_ctrl->dram_if_width,
 559                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK,
 560                         CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH <<
 561                         SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB);
 562
 563         debug("Configuring DRAMDEVWIDTH\n");
 564         clrsetbits_le32(&sdr_ctrl->dram_dev_width,
 565                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK,
 566                         CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH <<
 567                         SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB);
 568
 569         debug("Configuring LOWPWREQ\n");
 570         clrsetbits_le32(&sdr_ctrl->lowpwr_eq,
 571                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK,
 572                         CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK <<
 573                         SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB);
 574
 575         debug("Configuring DRAMINTR\n");
 576         clrsetbits_le32(&sdr_ctrl->dram_intr, SDR_CTRLGRP_DRAMINTR_INTREN_MASK,
 577                         CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN <<
 578                         SDR_CTRLGRP_DRAMINTR_INTREN_LSB);
 579
 580         set_sdr_static_cfg();
 581
 582         debug("Configuring CTRLWIDTH\n");
 583         clrsetbits_le32(&sdr_ctrl->ctrl_width,
 584                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK,
 585                         CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH <<
 586                         SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB);
 587
 588         debug("Configuring PORTCFG\n");
 589         clrsetbits_le32(&sdr_ctrl->port_cfg, SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK,
 590                         CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN <<
 591                         SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB);
 592
 593         set_sdr_fifo_cfg();
 594
 595         debug("Configuring MPPRIORITY\n");
 596         clrsetbits_le32(&sdr_ctrl->mp_priority,
 597                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK,
 598                         CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY <<
 599                         SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB);
 600
 601         set_sdr_mp_weight();
 602         set_sdr_mp_pacing();
 603         set_sdr_mp_threshold();
 604
 605         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 606         setbits_le32(&sdr_ctrl->phy_ctrl0,
 607                      CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0);
 608
 609         debug("Configuring CPORTWIDTH\n");
 610         clrsetbits_le32(&sdr_ctrl->cport_width,
 611                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK,
 612                         CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH <<
 613                         SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB);
 614         debug("   Write - Address ");
 615         debug("0x%08x Data 0x%08x\n",
 616                 (unsigned)(&sdr_ctrl->cport_width),
 617                 (unsigned)reg_value);
 618         reg_value = readl(&sdr_ctrl->cport_width);
 619         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 620
 621         debug("Configuring CPORTWMAP\n");
 622         clrsetbits_le32(&sdr_ctrl->cport_wmap,
 623                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK,
 624                         CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP <<
 625                         SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB);
 626         debug("   Write - Address ");
 627         debug("0x%08x Data 0x%08x\n",
 628                 (unsigned)(&sdr_ctrl->cport_wmap),
 629                 (unsigned)reg_value);
 630         reg_value = readl(&sdr_ctrl->cport_wmap);
 631         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 632
 633         debug("Configuring CPORTRMAP\n");
 634         clrsetbits_le32(&sdr_ctrl->cport_rmap,
 635                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK,
 636                         CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP <<
 637                         SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB);
 638         debug("   Write - Address ");
 639         debug("0x%08x Data 0x%08x\n",
 640                 (unsigned)(&sdr_ctrl->cport_rmap),
 641                 (unsigned)reg_value);
 642         reg_value = readl(&sdr_ctrl->cport_rmap);
 643         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 644
 645         debug("Configuring RFIFOCMAP\n");
 646         clrsetbits_le32(&sdr_ctrl->rfifo_cmap,
 647                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK,
 648                         CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP <<
 649                         SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB);
 650         debug("   Write - Address ");
 651         debug("0x%08x Data 0x%08x\n",
 652                 (unsigned)(&sdr_ctrl->rfifo_cmap),
 653                 (unsigned)reg_value);
 654         reg_value = readl(&sdr_ctrl->rfifo_cmap);
 655         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 656
 657         debug("Configuring WFIFOCMAP\n");
 658         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 659         clrsetbits_le32(&sdr_ctrl->wfifo_cmap,
 660                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK,
 661                         CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP <<
 662                         SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB);
 663         debug("   Write - Address ");
 664         debug("0x%08x Data 0x%08x\n",
 665                 (unsigned)(&sdr_ctrl->wfifo_cmap),
 666                 (unsigned)reg_value);
 667         reg_value = readl(&sdr_ctrl->wfifo_cmap);
 668         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 669
 670         debug("Configuring CPORTRDWR\n");
 671         clrsetbits_le32(&sdr_ctrl->cport_rdwr,
 672                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK,
 673                         CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR <<
 674                         SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB);
 675         debug("   Write - Address ");
 676         debug("0x%08x Data 0x%08x\n",
 677                 (unsigned)(&sdr_ctrl->cport_rdwr),
 678                 (unsigned)reg_value);
 679         reg_value = readl(&sdr_ctrl->cport_rdwr);
 680         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 681
 682         debug("Configuring DRAMODT\n");
 683         clrsetbits_le32(&sdr_ctrl->dram_odt,
 684                         SDR_CTRLGRP_DRAMODT_READ_MASK,
 685                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ <<
 686                         SDR_CTRLGRP_DRAMODT_READ_LSB);
 687
 688         clrsetbits_le32(&sdr_ctrl->dram_odt,
 689                         SDR_CTRLGRP_DRAMODT_WRITE_MASK,
 690                         CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
 691                         SDR_CTRLGRP_DRAMODT_WRITE_LSB);
 692
 693         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 694         writel(CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST,
 695                &sysmgr_regs->iswgrp_handoff[3]);
 696
 697         /* only enable if the FPGA is programmed */
 698         if (fpgamgr_test_fpga_ready()) {
 699                 if (sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 700                     CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST) == 1) {
 701                         status = 1;
 702                         return 1;
 703                 }
 704         }
 705
 706         /* Restore the SDR PHY Register if valid */
 707         if (sdr_phy_reg != 0xffffffff)
 708                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 709
 710 /***** Final step - apply configuration changes *****/
 711         debug("Configuring STATICCFG_\n");
 712         clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 713                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 714         debug("   Write - Address ");
 715         debug("0x%08x Data 0x%08x\n",
 716                 (unsigned)(&sdr_ctrl->static_cfg),
 717                 (unsigned)reg_value);
 718         reg_value = readl(&sdr_ctrl->static_cfg);
 719         debug("   Read value without verify 0x%08x\n", (unsigned)reg_value);
 720
 721         sdram_set_protection_config(0, sdram_calculate_size());
 722
 723         sdram_dump_protection_config();
 724
 725         return status;
 726 }
 727
 728 /*
 729  * To calculate SDRAM device size based on SDRAM controller parameters.
 730  * Size is specified in bytes.
 731  *
 732  * NOTE:
 733  * This function is compiled and linked into the preloader and
 734  * Uboot (there may be others). So if this function changes, the Preloader
 735  * and UBoot must be updated simultaneously.
 736  */
 737 unsigned long sdram_calculate_size(void)
 738 {
 739         unsigned long temp;
 740         unsigned long row, bank, col, cs, width;
 741
 742         temp = readl(&sdr_ctrl->dram_addrw);
 743         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 744                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 745
 746         /* SDRAM Failure When Accessing Non-Existent Memory
 747          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 748          * since the FB specifies we modify ROWBITs to work around SDRAM
 749          * controller issue.
 750          *
 751          * If the stored handoff value for rows is 0, it probably means
 752          * the preloader is older than UBoot. Use the
 753          * #define from the SOCEDS Tools per Crucible review
 754          * uboot-socfpga-204. Note that this is not a supported
 755          * configuration and is not tested. The customer
 756          * should be using preloader and uboot built from the
 757          * same tag.
 758          */
 759         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 760         if (row == 0)
 761                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 762         /* If the stored handoff value for rows is greater than
 763          * the field width in the sdr.dramaddrw register then
 764          * something is very wrong. Revert to using the the #define
 765          * value handed off by the SOCEDS tool chain instead of
 766          * using a broken value.
 767          */
 768         if (row > 31)
 769                 row = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
 770
 771         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 772                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 773
 774         /* SDRAM Failure When Accessing Non-Existent Memory
 775          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 776          * since the FB specifies we modify CSBITs to work around SDRAM
 777          * controller issue.
 778          */
 779         cs = (temp & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 780               SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB;
 781         cs += 1;
 782
 783         cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
 784
 785         width = readl(&sdr_ctrl->dram_if_width);
 786         /* ECC would not be calculated as its not addressible */
 787         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 788                 width = 32;
 789         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 790                 width = 16;
 791
 792         /* calculate the SDRAM size base on this info */
 793         temp = 1 << (row + bank + col);
 794         temp = temp * cs * (width  / 8);
 795
 796         debug("sdram_calculate_memory returns %ld\n", temp);
 797
 798         return temp;
 799 }