2 * Copyright Altera Corporation (C) 2014-2015
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/fpga_manager.h>
11 #include <asm/arch/sdram.h>
12 #include <asm/arch/system_manager.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct sdram_prot_rule {
18 u64 sdram_start; /* SDRAM start address */
19 u64 sdram_end; /* SDRAM end address */
20 u32 rule; /* SDRAM protection rule number: 0-19 */
21 int valid; /* Rule valid or not? 1 - valid, 0 not*/
30 static struct socfpga_system_manager *sysmgr_regs =
31 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
32 static struct socfpga_sdr_ctrl *sdr_ctrl =
33 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
36 * get_errata_rows() - Up the number of DRAM rows to cover entire address space
37 * @cfg: SDRAM controller configuration data
39 * SDRAM Failure happens when accessing non-existent memory. Artificially
40 * increase the number of rows so that the memory controller thinks it has
41 * 4GB of RAM. This function returns such amount of rows.
43 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
45 /* Define constant for 4G memory - used for SDRAM errata workaround */
46 #define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
47 const unsigned long long memsize = MEMSIZE_4G;
48 const unsigned int cs =
49 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
50 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
51 const unsigned int rows =
52 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
53 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
54 const unsigned int banks =
55 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
56 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
57 const unsigned int cols =
58 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
59 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
60 const unsigned int width = 8;
62 unsigned long long newrows;
63 int bits, inewrowslog2;
65 debug("workaround rows - memsize %lld\n", memsize);
66 debug("workaround rows - cs %d\n", cs);
67 debug("workaround rows - width %d\n", width);
68 debug("workaround rows - rows %d\n", rows);
69 debug("workaround rows - banks %d\n", banks);
70 debug("workaround rows - cols %d\n", cols);
72 newrows = lldiv(memsize, cs * (width / 8));
73 debug("rows workaround - term1 %lld\n", newrows);
75 newrows = lldiv(newrows, (1 << banks) * (1 << cols));
76 debug("rows workaround - term2 %lld\n", newrows);
79 * Compute the hamming weight - same as number of bits set.
80 * Need to see if result is ordinal power of 2 before
81 * attempting log2 of result.
83 bits = generic_hweight32(newrows);
85 debug("rows workaround - bits %d\n", bits);
88 printf("SDRAM workaround failed, bits set %d\n", bits);
92 if (newrows > UINT_MAX) {
93 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
97 inewrowslog2 = __ilog2(newrows);
99 debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
101 if (inewrowslog2 == -1) {
102 printf("SDRAM workaround failed, newrows %lld\n", newrows);
109 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
110 static void sdram_set_rule(struct sdram_prot_rule *prule)
112 uint32_t lo_addr_bits;
113 uint32_t hi_addr_bits;
114 int ruleno = prule->rule;
116 /* Select the rule */
117 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
119 /* Obtain the address bits */
120 lo_addr_bits = prule->sdram_start >> 20ULL;
121 hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
123 debug("sdram set rule start %x, %lld\n", lo_addr_bits,
125 debug("sdram set rule end %x, %lld\n", hi_addr_bits,
128 /* Set rule addresses */
129 writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
131 /* Set rule protection ids */
132 writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
133 &sdr_ctrl->prot_rule_id);
135 /* Set the rule data */
136 writel(prule->security | (prule->valid << 2) |
137 (prule->portmask << 3) | (prule->result << 13),
138 &sdr_ctrl->prot_rule_data);
141 writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
143 /* Set rule number to 0 by default */
144 writel(0, &sdr_ctrl->prot_rule_rdwr);
147 static void sdram_get_rule(struct sdram_prot_rule *prule)
152 int ruleno = prule->rule;
155 writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
156 writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
158 /* Get the addresses */
159 addr = readl(&sdr_ctrl->prot_rule_addr);
160 prule->sdram_start = (addr & 0xFFF) << 20;
161 prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
163 /* Get the configured protection IDs */
164 id = readl(&sdr_ctrl->prot_rule_id);
165 prule->lo_prot_id = id & 0xFFF;
166 prule->hi_prot_id = (id >> 12) & 0xFFF;
168 /* Get protection data */
169 data = readl(&sdr_ctrl->prot_rule_data);
171 prule->security = data & 0x3;
172 prule->valid = (data >> 2) & 0x1;
173 prule->portmask = (data >> 3) & 0x3FF;
174 prule->result = (data >> 13) & 0x1;
177 static void sdram_set_protection_config(uint64_t sdram_start, uint64_t sdram_end)
179 struct sdram_prot_rule rule;
182 /* Start with accepting all SDRAM transaction */
183 writel(0x0, &sdr_ctrl->protport_default);
185 /* Clear all protection rules for warm boot case */
186 memset(&rule, 0, sizeof(rule));
188 for (rules = 0; rules < 20; rules++) {
190 sdram_set_rule(&rule);
193 /* new rule: accept SDRAM */
194 rule.sdram_start = sdram_start;
195 rule.sdram_end = sdram_end;
196 rule.lo_prot_id = 0x0;
197 rule.hi_prot_id = 0xFFF;
198 rule.portmask = 0x3FF;
205 sdram_set_rule(&rule);
207 /* default rule: reject everything */
208 writel(0x3ff, &sdr_ctrl->protport_default);
211 static void sdram_dump_protection_config(void)
213 struct sdram_prot_rule rule;
216 debug("SDRAM Prot rule, default %x\n",
217 readl(&sdr_ctrl->protport_default));
219 for (rules = 0; rules < 20; rules++) {
220 sdram_get_rule(&rule);
221 debug("Rule %d, rules ...\n", rules);
222 debug(" sdram start %llx\n", rule.sdram_start);
223 debug(" sdram end %llx\n", rule.sdram_end);
224 debug(" low prot id %d, hi prot id %d\n",
227 debug(" portmask %x\n", rule.portmask);
228 debug(" security %d\n", rule.security);
229 debug(" result %d\n", rule.result);
230 debug(" valid %d\n", rule.valid);
235 * sdram_write_verify() - write to register and verify the write.
236 * @addr: Register address
237 * @val: Value to be written and verified
239 * This function writes to a register, reads back the value and compares
240 * the result with the written value to check if the data match.
242 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
246 debug(" Write - Address 0x%p Data 0x%08x\n", addr, val);
249 debug(" Read and verify...");
252 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
262 * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
263 * @cfg: SDRAM controller configuration data
265 * Return the value of DRAM CTRLCFG register.
267 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
270 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
271 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
273 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
274 SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
276 u32 ctrl_cfg = cfg->ctrl_cfg;
279 * SDRAM Failure When Accessing Non-Existent Memory
280 * Set the addrorder field of the SDRAM control register
281 * based on the CSBITs setting.
285 debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
287 } else if (csbits == 2) {
289 debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
293 ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
294 ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
300 * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
301 * @cfg: SDRAM controller configuration data
303 * Return the value of DRAM ADDRW register.
305 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
308 * SDRAM Failure When Accessing Non-Existent Memory
309 * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
310 * log2(number of chip select bits). Since there's only
311 * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
312 * which is the same as "chip selects" - 1.
314 const int rows = get_errata_rows(cfg);
315 u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
317 return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
321 * sdr_load_regs() - Load SDRAM controller registers
322 * @cfg: SDRAM controller configuration data
324 * This function loads the register values into the SDRAM controller block.
326 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
328 const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
329 const u32 dram_addrw = sdr_get_addr_rw(cfg);
331 debug("\nConfiguring CTRLCFG\n");
332 writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
334 debug("Configuring DRAMTIMING1\n");
335 writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
337 debug("Configuring DRAMTIMING2\n");
338 writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
340 debug("Configuring DRAMTIMING3\n");
341 writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
343 debug("Configuring DRAMTIMING4\n");
344 writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
346 debug("Configuring LOWPWRTIMING\n");
347 writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
349 debug("Configuring DRAMADDRW\n");
350 writel(dram_addrw, &sdr_ctrl->dram_addrw);
352 debug("Configuring DRAMIFWIDTH\n");
353 writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
355 debug("Configuring DRAMDEVWIDTH\n");
356 writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
358 debug("Configuring LOWPWREQ\n");
359 writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
361 debug("Configuring DRAMINTR\n");
362 writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
364 debug("Configuring STATICCFG\n");
365 writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
367 debug("Configuring CTRLWIDTH\n");
368 writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
370 debug("Configuring PORTCFG\n");
371 writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
373 debug("Configuring FIFOCFG\n");
374 writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
376 debug("Configuring MPPRIORITY\n");
377 writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
379 debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
380 writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
381 writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
382 writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
383 writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
385 debug("Configuring MPPACING_MPPACING_0\n");
386 writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
387 writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
388 writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
389 writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
391 debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
392 writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
393 writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
394 writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
396 debug("Configuring PHYCTRL_PHYCTRL_0\n");
397 writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
399 debug("Configuring CPORTWIDTH\n");
400 writel(cfg->cport_width, &sdr_ctrl->cport_width);
402 debug("Configuring CPORTWMAP\n");
403 writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
405 debug("Configuring CPORTRMAP\n");
406 writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
408 debug("Configuring RFIFOCMAP\n");
409 writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
411 debug("Configuring WFIFOCMAP\n");
412 writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
414 debug("Configuring CPORTRDWR\n");
415 writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
417 debug("Configuring DRAMODT\n");
418 writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
422 * sdram_mmr_init_full() - Function to initialize SDRAM MMR
423 * @sdr_phy_reg: Value of the PHY control register 0
425 * Initialize the SDRAM MMR.
427 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
429 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
430 const unsigned int rows =
431 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
432 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
435 writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
439 /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
440 writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
442 /* only enable if the FPGA is programmed */
443 if (fpgamgr_test_fpga_ready()) {
444 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
450 /* Restore the SDR PHY Register if valid */
451 if (sdr_phy_reg != 0xffffffff)
452 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
454 /* Final step - apply configuration changes */
455 debug("Configuring STATICCFG\n");
456 clrsetbits_le32(&sdr_ctrl->static_cfg,
457 SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
458 1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
460 sdram_set_protection_config(0, sdram_calculate_size());
462 sdram_dump_protection_config();
468 * sdram_calculate_size() - Calculate SDRAM size
470 * Calculate SDRAM device size based on SDRAM controller parameters.
471 * Size is specified in bytes.
473 unsigned long sdram_calculate_size(void)
476 unsigned long row, bank, col, cs, width;
477 const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
478 const unsigned int csbits =
479 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
480 SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
481 const unsigned int rowbits =
482 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
483 SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
485 temp = readl(&sdr_ctrl->dram_addrw);
486 col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
487 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
490 * SDRAM Failure When Accessing Non-Existent Memory
491 * Use ROWBITS from Quartus/QSys to calculate SDRAM size
492 * since the FB specifies we modify ROWBITs to work around SDRAM
495 row = readl(&sysmgr_regs->iswgrp_handoff[4]);
499 * If the stored handoff value for rows is greater than
500 * the field width in the sdr.dramaddrw register then
501 * something is very wrong. Revert to using the the #define
502 * value handed off by the SOCEDS tool chain instead of
503 * using a broken value.
508 bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
509 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
512 * SDRAM Failure When Accessing Non-Existent Memory
513 * Use CSBITs from Quartus/QSys to calculate SDRAM size
514 * since the FB specifies we modify CSBITs to work around SDRAM
519 width = readl(&sdr_ctrl->dram_if_width);
521 /* ECC would not be calculated as its not addressible */
522 if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
524 if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
527 /* calculate the SDRAM size base on this info */
528 temp = 1 << (row + bank + col);
529 temp = temp * cs * (width / 8);
531 debug("%s returns %ld\n", __func__, temp);