drivers/ddr/altera/sdram.c

   1 /*
   2  * Copyright Altera Corporation (C) 2014-2015
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6 #include <common.h>
   7 #include <errno.h>
   8 #include <div64.h>
   9 #include <watchdog.h>
  10 #include <asm/arch/fpga_manager.h>
  11 #include <asm/arch/sdram.h>
  12 #include <asm/arch/system_manager.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 struct sdram_prot_rule {
  18         u32     sdram_start;    /* SDRAM start address */
  19         u32     sdram_end;      /* SDRAM end address */
  20         u32     rule;           /* SDRAM protection rule number: 0-19 */
  21         int     valid;          /* Rule valid or not? 1 - valid, 0 not*/
  22
  23         u32     security;
  24         u32     portmask;
  25         u32     result;
  26         u32     lo_prot_id;
  27         u32     hi_prot_id;
  28 };
  29
  30 static struct socfpga_system_manager *sysmgr_regs =
  31         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  32 static struct socfpga_sdr_ctrl *sdr_ctrl =
  33         (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
  34
  35 /**
  36  * get_errata_rows() - Up the number of DRAM rows to cover entire address space
  37  * @cfg:        SDRAM controller configuration data
  38  *
  39  * SDRAM Failure happens when accessing non-existent memory. Artificially
  40  * increase the number of rows so that the memory controller thinks it has
  41  * 4GB of RAM. This function returns such amount of rows.
  42  */
  43 static int get_errata_rows(const struct socfpga_sdram_config *cfg)
  44 {
  45         /* Define constant for 4G memory - used for SDRAM errata workaround */
  46 #define MEMSIZE_4G      (4ULL * 1024ULL * 1024ULL * 1024ULL)
  47         const unsigned long long memsize = MEMSIZE_4G;
  48         const unsigned int cs =
  49                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
  50                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
  51         const unsigned int rows =
  52                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
  53                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
  54         const unsigned int banks =
  55                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
  56                         SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
  57         const unsigned int cols =
  58                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
  59                         SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
  60         const unsigned int width = 8;
  61
  62         unsigned long long newrows;
  63         int bits, inewrowslog2;
  64
  65         debug("workaround rows - memsize %lld\n", memsize);
  66         debug("workaround rows - cs        %d\n", cs);
  67         debug("workaround rows - width     %d\n", width);
  68         debug("workaround rows - rows      %d\n", rows);
  69         debug("workaround rows - banks     %d\n", banks);
  70         debug("workaround rows - cols      %d\n", cols);
  71
  72         newrows = lldiv(memsize, cs * (width / 8));
  73         debug("rows workaround - term1 %lld\n", newrows);
  74
  75         newrows = lldiv(newrows, (1 << banks) * (1 << cols));
  76         debug("rows workaround - term2 %lld\n", newrows);
  77
  78         /*
  79          * Compute the hamming weight - same as number of bits set.
  80          * Need to see if result is ordinal power of 2 before
  81          * attempting log2 of result.
  82          */
  83         bits = generic_hweight32(newrows);
  84
  85         debug("rows workaround - bits %d\n", bits);
  86
  87         if (bits != 1) {
  88                 printf("SDRAM workaround failed, bits set %d\n", bits);
  89                 return rows;
  90         }
  91
  92         if (newrows > UINT_MAX) {
  93                 printf("SDRAM workaround rangecheck failed, %lld\n", newrows);
  94                 return rows;
  95         }
  96
  97         inewrowslog2 = __ilog2(newrows);
  98
  99         debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
 100
 101         if (inewrowslog2 == -1) {
 102                 printf("SDRAM workaround failed, newrows %lld\n", newrows);
 103                 return rows;
 104         }
 105
 106         return inewrowslog2;
 107 }
 108
 109 /* SDRAM protection rules vary from 0-19, a total of 20 rules. */
 110 static void sdram_set_rule(struct sdram_prot_rule *prule)
 111 {
 112         u32 lo_addr_bits;
 113         u32 hi_addr_bits;
 114         int ruleno = prule->rule;
 115
 116         /* Select the rule */
 117         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 118
 119         /* Obtain the address bits */
 120         lo_addr_bits = prule->sdram_start >> 20ULL;
 121         hi_addr_bits = (prule->sdram_end - 1) >> 20ULL;
 122
 123         debug("sdram set rule start %x, %d\n", lo_addr_bits,
 124               prule->sdram_start);
 125         debug("sdram set rule end   %x, %d\n", hi_addr_bits,
 126               prule->sdram_end);
 127
 128         /* Set rule addresses */
 129         writel(lo_addr_bits | (hi_addr_bits << 12), &sdr_ctrl->prot_rule_addr);
 130
 131         /* Set rule protection ids */
 132         writel(prule->lo_prot_id | (prule->hi_prot_id << 12),
 133                &sdr_ctrl->prot_rule_id);
 134
 135         /* Set the rule data */
 136         writel(prule->security | (prule->valid << 2) |
 137                (prule->portmask << 3) | (prule->result << 13),
 138                &sdr_ctrl->prot_rule_data);
 139
 140         /* write the rule */
 141         writel(ruleno | (1 << 5), &sdr_ctrl->prot_rule_rdwr);
 142
 143         /* Set rule number to 0 by default */
 144         writel(0, &sdr_ctrl->prot_rule_rdwr);
 145 }
 146
 147 static void sdram_get_rule(struct sdram_prot_rule *prule)
 148 {
 149         u32 addr;
 150         u32 id;
 151         u32 data;
 152         int ruleno = prule->rule;
 153
 154         /* Read the rule */
 155         writel(ruleno, &sdr_ctrl->prot_rule_rdwr);
 156         writel(ruleno | (1 << 6), &sdr_ctrl->prot_rule_rdwr);
 157
 158         /* Get the addresses */
 159         addr = readl(&sdr_ctrl->prot_rule_addr);
 160         prule->sdram_start = (addr & 0xFFF) << 20;
 161         prule->sdram_end = ((addr >> 12) & 0xFFF) << 20;
 162
 163         /* Get the configured protection IDs */
 164         id = readl(&sdr_ctrl->prot_rule_id);
 165         prule->lo_prot_id = id & 0xFFF;
 166         prule->hi_prot_id = (id >> 12) & 0xFFF;
 167
 168         /* Get protection data */
 169         data = readl(&sdr_ctrl->prot_rule_data);
 170
 171         prule->security = data & 0x3;
 172         prule->valid = (data >> 2) & 0x1;
 173         prule->portmask = (data >> 3) & 0x3FF;
 174         prule->result = (data >> 13) & 0x1;
 175 }
 176
 177 static void
 178 sdram_set_protection_config(const u32 sdram_start, const u32 sdram_end)
 179 {
 180         struct sdram_prot_rule rule;
 181         int rules;
 182
 183         /* Start with accepting all SDRAM transaction */
 184         writel(0x0, &sdr_ctrl->protport_default);
 185
 186         /* Clear all protection rules for warm boot case */
 187         memset(&rule, 0, sizeof(rule));
 188
 189         for (rules = 0; rules < 20; rules++) {
 190                 rule.rule = rules;
 191                 sdram_set_rule(&rule);
 192         }
 193
 194         /* new rule: accept SDRAM */
 195         rule.sdram_start = sdram_start;
 196         rule.sdram_end = sdram_end;
 197         rule.lo_prot_id = 0x0;
 198         rule.hi_prot_id = 0xFFF;
 199         rule.portmask = 0x3FF;
 200         rule.security = 0x3;
 201         rule.result = 0;
 202         rule.valid = 1;
 203         rule.rule = 0;
 204
 205         /* set new rule */
 206         sdram_set_rule(&rule);
 207
 208         /* default rule: reject everything */
 209         writel(0x3ff, &sdr_ctrl->protport_default);
 210 }
 211
 212 static void sdram_dump_protection_config(void)
 213 {
 214         struct sdram_prot_rule rule;
 215         int rules;
 216
 217         debug("SDRAM Prot rule, default %x\n",
 218               readl(&sdr_ctrl->protport_default));
 219
 220         for (rules = 0; rules < 20; rules++) {
 221                 rule.rule = rules;
 222                 sdram_get_rule(&rule);
 223                 debug("Rule %d, rules ...\n", rules);
 224                 debug("    sdram start %x\n", rule.sdram_start);
 225                 debug("    sdram end   %x\n", rule.sdram_end);
 226                 debug("    low prot id %d, hi prot id %d\n",
 227                       rule.lo_prot_id,
 228                       rule.hi_prot_id);
 229                 debug("    portmask %x\n", rule.portmask);
 230                 debug("    security %d\n", rule.security);
 231                 debug("    result %d\n", rule.result);
 232                 debug("    valid %d\n", rule.valid);
 233         }
 234 }
 235
 236 /**
 237  * sdram_write_verify() - write to register and verify the write.
 238  * @addr:       Register address
 239  * @val:        Value to be written and verified
 240  *
 241  * This function writes to a register, reads back the value and compares
 242  * the result with the written value to check if the data match.
 243  */
 244 static unsigned sdram_write_verify(const u32 *addr, const u32 val)
 245 {
 246         u32 rval;
 247
 248         debug("   Write - Address 0x%p Data 0x%08x\n", addr, val);
 249         writel(val, addr);
 250
 251         debug("   Read and verify...");
 252         rval = readl(addr);
 253         if (rval != val) {
 254                 debug("FAIL - Address 0x%p Expected 0x%08x Data 0x%08x\n",
 255                       addr, val, rval);
 256                 return -EINVAL;
 257         }
 258
 259         debug("correct!\n");
 260         return 0;
 261 }
 262
 263 /**
 264  * sdr_get_ctrlcfg() - Get the value of DRAM CTRLCFG register
 265  * @cfg:        SDRAM controller configuration data
 266  *
 267  * Return the value of DRAM CTRLCFG register.
 268  */
 269 static u32 sdr_get_ctrlcfg(const struct socfpga_sdram_config *cfg)
 270 {
 271         const u32 csbits =
 272                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 273                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 274         u32 addrorder =
 275                 (cfg->ctrl_cfg & SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK) >>
 276                         SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 277
 278         u32 ctrl_cfg = cfg->ctrl_cfg;
 279
 280         /*
 281          * SDRAM Failure When Accessing Non-Existent Memory
 282          * Set the addrorder field of the SDRAM control register
 283          * based on the CSBITs setting.
 284          */
 285         if (csbits == 1) {
 286                 if (addrorder != 0)
 287                         debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
 288                 addrorder = 0;
 289         } else if (csbits == 2) {
 290                 if (addrorder != 2)
 291                         debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
 292                 addrorder = 2;
 293         }
 294
 295         ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
 296         ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
 297
 298         return ctrl_cfg;
 299 }
 300
 301 /**
 302  * sdr_get_addr_rw() - Get the value of DRAM ADDRW register
 303  * @cfg:        SDRAM controller configuration data
 304  *
 305  * Return the value of DRAM ADDRW register.
 306  */
 307 static u32 sdr_get_addr_rw(const struct socfpga_sdram_config *cfg)
 308 {
 309         /*
 310          * SDRAM Failure When Accessing Non-Existent Memory
 311          * Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
 312          * log2(number of chip select bits). Since there's only
 313          * 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
 314          * which is the same as "chip selects" - 1.
 315          */
 316         const int rows = get_errata_rows(cfg);
 317         u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
 318
 319         return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
 320 }
 321
 322 /**
 323  * sdr_load_regs() - Load SDRAM controller registers
 324  * @cfg:        SDRAM controller configuration data
 325  *
 326  * This function loads the register values into the SDRAM controller block.
 327  */
 328 static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
 329 {
 330         const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
 331         const u32 dram_addrw = sdr_get_addr_rw(cfg);
 332
 333         debug("\nConfiguring CTRLCFG\n");
 334         writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
 335
 336         debug("Configuring DRAMTIMING1\n");
 337         writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
 338
 339         debug("Configuring DRAMTIMING2\n");
 340         writel(cfg->dram_timing2, &sdr_ctrl->dram_timing2);
 341
 342         debug("Configuring DRAMTIMING3\n");
 343         writel(cfg->dram_timing3, &sdr_ctrl->dram_timing3);
 344
 345         debug("Configuring DRAMTIMING4\n");
 346         writel(cfg->dram_timing4, &sdr_ctrl->dram_timing4);
 347
 348         debug("Configuring LOWPWRTIMING\n");
 349         writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
 350
 351         debug("Configuring DRAMADDRW\n");
 352         writel(dram_addrw, &sdr_ctrl->dram_addrw);
 353
 354         debug("Configuring DRAMIFWIDTH\n");
 355         writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
 356
 357         debug("Configuring DRAMDEVWIDTH\n");
 358         writel(cfg->dram_dev_width, &sdr_ctrl->dram_dev_width);
 359
 360         debug("Configuring LOWPWREQ\n");
 361         writel(cfg->lowpwr_eq, &sdr_ctrl->lowpwr_eq);
 362
 363         debug("Configuring DRAMINTR\n");
 364         writel(cfg->dram_intr, &sdr_ctrl->dram_intr);
 365
 366         debug("Configuring STATICCFG\n");
 367         writel(cfg->static_cfg, &sdr_ctrl->static_cfg);
 368
 369         debug("Configuring CTRLWIDTH\n");
 370         writel(cfg->ctrl_width, &sdr_ctrl->ctrl_width);
 371
 372         debug("Configuring PORTCFG\n");
 373         writel(cfg->port_cfg, &sdr_ctrl->port_cfg);
 374
 375         debug("Configuring FIFOCFG\n");
 376         writel(cfg->fifo_cfg, &sdr_ctrl->fifo_cfg);
 377
 378         debug("Configuring MPPRIORITY\n");
 379         writel(cfg->mp_priority, &sdr_ctrl->mp_priority);
 380
 381         debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
 382         writel(cfg->mp_weight0, &sdr_ctrl->mp_weight0);
 383         writel(cfg->mp_weight1, &sdr_ctrl->mp_weight1);
 384         writel(cfg->mp_weight2, &sdr_ctrl->mp_weight2);
 385         writel(cfg->mp_weight3, &sdr_ctrl->mp_weight3);
 386
 387         debug("Configuring MPPACING_MPPACING_0\n");
 388         writel(cfg->mp_pacing0, &sdr_ctrl->mp_pacing0);
 389         writel(cfg->mp_pacing1, &sdr_ctrl->mp_pacing1);
 390         writel(cfg->mp_pacing2, &sdr_ctrl->mp_pacing2);
 391         writel(cfg->mp_pacing3, &sdr_ctrl->mp_pacing3);
 392
 393         debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
 394         writel(cfg->mp_threshold0, &sdr_ctrl->mp_threshold0);
 395         writel(cfg->mp_threshold1, &sdr_ctrl->mp_threshold1);
 396         writel(cfg->mp_threshold2, &sdr_ctrl->mp_threshold2);
 397
 398         debug("Configuring PHYCTRL_PHYCTRL_0\n");
 399         writel(cfg->phy_ctrl0, &sdr_ctrl->phy_ctrl0);
 400
 401         debug("Configuring CPORTWIDTH\n");
 402         writel(cfg->cport_width, &sdr_ctrl->cport_width);
 403
 404         debug("Configuring CPORTWMAP\n");
 405         writel(cfg->cport_wmap, &sdr_ctrl->cport_wmap);
 406
 407         debug("Configuring CPORTRMAP\n");
 408         writel(cfg->cport_rmap, &sdr_ctrl->cport_rmap);
 409
 410         debug("Configuring RFIFOCMAP\n");
 411         writel(cfg->rfifo_cmap, &sdr_ctrl->rfifo_cmap);
 412
 413         debug("Configuring WFIFOCMAP\n");
 414         writel(cfg->wfifo_cmap, &sdr_ctrl->wfifo_cmap);
 415
 416         debug("Configuring CPORTRDWR\n");
 417         writel(cfg->cport_rdwr, &sdr_ctrl->cport_rdwr);
 418
 419         debug("Configuring DRAMODT\n");
 420         writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
 421 }
 422
 423 /**
 424  * sdram_mmr_init_full() - Function to initialize SDRAM MMR
 425  * @sdr_phy_reg:        Value of the PHY control register 0
 426  *
 427  * Initialize the SDRAM MMR.
 428  */
 429 int sdram_mmr_init_full(unsigned int sdr_phy_reg)
 430 {
 431         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 432         const unsigned int rows =
 433                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 434                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 435         int ret;
 436
 437         writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
 438
 439         sdr_load_regs(cfg);
 440
 441         /* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
 442         writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);
 443
 444         /* only enable if the FPGA is programmed */
 445         if (fpgamgr_test_fpga_ready()) {
 446                 ret = sdram_write_verify(&sdr_ctrl->fpgaport_rst,
 447                                          cfg->fpgaport_rst);
 448                 if (ret)
 449                         return ret;
 450         }
 451
 452         /* Restore the SDR PHY Register if valid */
 453         if (sdr_phy_reg != 0xffffffff)
 454                 writel(sdr_phy_reg, &sdr_ctrl->phy_ctrl0);
 455
 456         /* Final step - apply configuration changes */
 457         debug("Configuring STATICCFG\n");
 458         clrsetbits_le32(&sdr_ctrl->static_cfg,
 459                         SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK,
 460                         1 << SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB);
 461
 462         sdram_set_protection_config(0, sdram_calculate_size() - 1);
 463
 464         sdram_dump_protection_config();
 465
 466         return 0;
 467 }
 468
 469 /**
 470  * sdram_calculate_size() - Calculate SDRAM size
 471  *
 472  * Calculate SDRAM device size based on SDRAM controller parameters.
 473  * Size is specified in bytes.
 474  */
 475 unsigned long sdram_calculate_size(void)
 476 {
 477         unsigned long temp;
 478         unsigned long row, bank, col, cs, width;
 479         const struct socfpga_sdram_config *cfg = socfpga_get_sdram_config();
 480         const unsigned int csbits =
 481                 ((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
 482                         SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB) + 1;
 483         const unsigned int rowbits =
 484                 (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
 485                         SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
 486
 487         temp = readl(&sdr_ctrl->dram_addrw);
 488         col = (temp & SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK) >>
 489                 SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB;
 490
 491         /*
 492          * SDRAM Failure When Accessing Non-Existent Memory
 493          * Use ROWBITS from Quartus/QSys to calculate SDRAM size
 494          * since the FB specifies we modify ROWBITs to work around SDRAM
 495          * controller issue.
 496          */
 497         row = readl(&sysmgr_regs->iswgrp_handoff[4]);
 498         if (row == 0)
 499                 row = rowbits;
 500         /*
 501          * If the stored handoff value for rows is greater than
 502          * the field width in the sdr.dramaddrw register then
 503          * something is very wrong. Revert to using the the #define
 504          * value handed off by the SOCEDS tool chain instead of
 505          * using a broken value.
 506          */
 507         if (row > 31)
 508                 row = rowbits;
 509
 510         bank = (temp & SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK) >>
 511                 SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB;
 512
 513         /*
 514          * SDRAM Failure When Accessing Non-Existent Memory
 515          * Use CSBITs from Quartus/QSys to calculate SDRAM size
 516          * since the FB specifies we modify CSBITs to work around SDRAM
 517          * controller issue.
 518          */
 519         cs = csbits;
 520
 521         width = readl(&sdr_ctrl->dram_if_width);
 522
 523         /* ECC would not be calculated as its not addressible */
 524         if (width == SDRAM_WIDTH_32BIT_WITH_ECC)
 525                 width = 32;
 526         if (width == SDRAM_WIDTH_16BIT_WITH_ECC)
 527                 width = 16;
 528
 529         /* calculate the SDRAM size base on this info */
 530         temp = 1 << (row + bank + col);
 531         temp = temp * cs * (width  / 8);
 532
 533         debug("%s returns %ld\n", __func__, temp);
 534
 535         return temp;
 536 }