2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \
24 && defined(CONFIG_TULIP)
38 #define PCI_CFDA_PSM 0x43
40 #define CFRV_RN 0x000000f0 /* Revision Number */
42 #define WAKEUP 0x00 /* Power Saving Wakeup */
43 #define SLEEP 0x80 /* Power Saving Sleep Mode */
45 #define DC2114x_BRK 0x0020 /* CFRV break between DC21142 & DC21143 */
47 /* Ethernet chip registers.
49 #define DE4X5_BMR 0x000 /* Bus Mode Register */
50 #define DE4X5_TPD 0x008 /* Transmit Poll Demand Reg */
51 #define DE4X5_RRBA 0x018 /* RX Ring Base Address Reg */
52 #define DE4X5_TRBA 0x020 /* TX Ring Base Address Reg */
53 #define DE4X5_STS 0x028 /* Status Register */
54 #define DE4X5_OMR 0x030 /* Operation Mode Register */
55 #define DE4X5_SICR 0x068 /* SIA Connectivity Register */
56 #define DE4X5_APROM 0x048 /* Ethernet Address PROM */
60 #define BMR_SWR 0x00000001 /* Software Reset */
61 #define STS_TS 0x00700000 /* Transmit Process State */
62 #define STS_RS 0x000e0000 /* Receive Process State */
63 #define OMR_ST 0x00002000 /* Start/Stop Transmission Command */
64 #define OMR_SR 0x00000002 /* Start/Stop Receive */
65 #define OMR_PS 0x00040000 /* Port Select */
66 #define OMR_SDP 0x02000000 /* SD Polarity - MUST BE ASSERTED */
67 #define OMR_PM 0x00000080 /* Pass All Multicast */
71 #define R_OWN 0x80000000 /* Own Bit */
72 #define RD_RER 0x02000000 /* Receive End Of Ring */
73 #define RD_LS 0x00000100 /* Last Descriptor */
74 #define RD_ES 0x00008000 /* Error Summary */
75 #define TD_TER 0x02000000 /* Transmit End Of Ring */
76 #define T_OWN 0x80000000 /* Own Bit */
77 #define TD_LS 0x40000000 /* Last Segment */
78 #define TD_FS 0x20000000 /* First Segment */
79 #define TD_ES 0x00008000 /* Error Summary */
80 #define TD_SET 0x08000000 /* Setup Packet */
82 /* The EEPROM commands include the alway-set leading bit. */
83 #define SROM_WRITE_CMD 5
84 #define SROM_READ_CMD 6
85 #define SROM_ERASE_CMD 7
87 #define SROM_HWADD 0x0014 /* Hardware Address offset in SROM */
88 #define SROM_RD 0x00004000 /* Read from Boot ROM */
89 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
90 #define EE_WRITE_0 0x4801
91 #define EE_WRITE_1 0x4805
92 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
93 #define SROM_SR 0x00000800 /* Select Serial ROM when set */
95 #define DT_IN 0x00000004 /* Serial Data In */
96 #define DT_CLK 0x00000002 /* Serial ROM Clock */
97 #define DT_CS 0x00000001 /* Serial ROM Chip Select */
101 #define RESET_DE4X5(dev) {\
103 i=INL(dev, DE4X5_BMR);\
105 OUTL(dev, i | BMR_SWR, DE4X5_BMR);\
107 OUTL(dev, i, DE4X5_BMR);\
109 for (i=0;i<5;i++) {INL(dev, DE4X5_BMR); udelay(10000);}\
113 #define START_DE4X5(dev) {\
115 omr = INL(dev, DE4X5_OMR);\
116 omr |= OMR_ST | OMR_SR;\
117 OUTL(dev, omr, DE4X5_OMR); /* Enable the TX and/or RX */\
120 #define STOP_DE4X5(dev) {\
122 omr = INL(dev, DE4X5_OMR);\
123 omr &= ~(OMR_ST|OMR_SR);\
124 OUTL(dev, omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
127 #define NUM_RX_DESC PKTBUFSRX
128 #define NUM_TX_DESC 1 /* Number of TX descriptors */
129 #define RX_BUFF_SZ PKTSIZE_ALIGN
131 #define TOUT_LOOP 1000000
133 #define SETUP_FRAME_LEN 192
144 static struct de4x5_desc rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
145 static struct de4x5_desc tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
146 static int rx_new; /* RX descriptor ring pointer */
147 static int tx_new; /* TX descriptor ring pointer */
149 static char rxRingSize;
150 static char txRingSize;
152 static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
153 static int getfrom_srom(struct eth_device* dev, u_long addr);
154 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len);
155 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len);
156 static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
158 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
159 static void update_srom(struct eth_device *dev, bd_t *bis);
161 static void read_hw_addr(struct eth_device* dev, bd_t * bis);
162 static void send_setup_frame(struct eth_device* dev, bd_t * bis);
164 static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
165 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length);
166 static int dc21x4x_recv(struct eth_device* dev);
167 static void dc21x4x_halt(struct eth_device* dev);
168 #ifdef CONFIG_TULIP_SELECT_MEDIA
169 extern void dc21x4x_select_media(struct eth_device* dev);
172 #if defined(CONFIG_E500)
173 #define phys_to_bus(a) (a)
175 #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
178 static int INL(struct eth_device* dev, u_long addr)
180 return le32_to_cpu(*(volatile u_long *)(addr + dev->iobase));
183 static void OUTL(struct eth_device* dev, int command, u_long addr)
185 *(volatile u_long *)(addr + dev->iobase) = cpu_to_le32(command);
188 static struct pci_device_id supported[] = {
189 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST },
190 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142 },
194 int dc21x4x_initialize(bd_t *bis)
202 unsigned short status;
203 struct eth_device* dev;
206 devbusfn = pci_find_devices(supported, idx++);
207 if (devbusfn == -1) {
211 /* Get the chip configuration revision register. */
212 pci_read_config_dword(devbusfn, PCI_REVISION_ID, &cfrv);
214 if ((cfrv & CFRV_RN) < DC2114x_BRK ) {
215 printf("Error: The chip is not DC21143.\n");
219 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
221 #ifdef CONFIG_TULIP_USE_IO
227 pci_write_config_word(devbusfn, PCI_COMMAND, status);
229 pci_read_config_word(devbusfn, PCI_COMMAND, &status);
230 if (!(status & PCI_COMMAND_IO)) {
231 printf("Error: Can not enable I/O access.\n");
235 if (!(status & PCI_COMMAND_IO)) {
236 printf("Error: Can not enable I/O access.\n");
240 if (!(status & PCI_COMMAND_MASTER)) {
241 printf("Error: Can not enable Bus Mastering.\n");
245 /* Check the latency timer for values >= 0x60. */
246 pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
249 pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x60);
252 #ifdef CONFIG_TULIP_USE_IO
253 /* read BAR for memory space access */
254 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &iobase);
255 iobase &= PCI_BASE_ADDRESS_IO_MASK;
257 /* read BAR for memory space access */
258 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
259 iobase &= PCI_BASE_ADDRESS_MEM_MASK;
263 printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
266 dev = (struct eth_device*) malloc(sizeof *dev);
268 sprintf(dev->name, "dc21x4x#%d", card_number);
269 #ifdef CONFIG_TULIP_USE_IO
270 dev->iobase = pci_io_to_phys(devbusfn, iobase);
272 dev->iobase = pci_mem_to_phys(devbusfn, iobase);
274 dev->priv = (void*) devbusfn;
275 dev->init = dc21x4x_init;
276 dev->halt = dc21x4x_halt;
277 dev->send = dc21x4x_send;
278 dev->recv = dc21x4x_recv;
280 /* Ensure we're not sleeping. */
281 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
285 read_hw_addr(dev, bis);
295 static int dc21x4x_init(struct eth_device* dev, bd_t* bis)
298 int devbusfn = (int) dev->priv;
300 /* Ensure we're not sleeping. */
301 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
305 if ((INL(dev, DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
306 printf("Error: Cannot reset ethernet controller.\n");
310 #ifdef CONFIG_TULIP_SELECT_MEDIA
311 dc21x4x_select_media(dev);
313 OUTL(dev, OMR_SDP | OMR_PS | OMR_PM, DE4X5_OMR);
316 for (i = 0; i < NUM_RX_DESC; i++) {
317 rx_ring[i].status = cpu_to_le32(R_OWN);
318 rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
319 rx_ring[i].buf = cpu_to_le32(phys_to_bus((u32) NetRxPackets[i]));
323 for (i=0; i < NUM_TX_DESC; i++) {
324 tx_ring[i].status = 0;
330 rxRingSize = NUM_RX_DESC;
331 txRingSize = NUM_TX_DESC;
333 /* Write the end of list marker to the descriptor lists. */
334 rx_ring[rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
335 tx_ring[txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
337 /* Tell the adapter where the TX/RX rings are located. */
338 OUTL(dev, phys_to_bus((u32) &rx_ring), DE4X5_RRBA);
339 OUTL(dev, phys_to_bus((u32) &tx_ring), DE4X5_TRBA);
346 send_setup_frame(dev, bis);
351 static int dc21x4x_send(struct eth_device* dev, volatile void *packet, int length)
357 printf("%s: bad packet size: %d\n", dev->name, length);
361 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
362 if (i >= TOUT_LOOP) {
363 printf("%s: tx error buffer not ready\n", dev->name);
368 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) packet));
369 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_LS | TD_FS | length);
370 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
372 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
374 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
375 if (i >= TOUT_LOOP) {
376 printf(".%s: tx buffer not ready\n", dev->name);
381 if (le32_to_cpu(tx_ring[tx_new].status) & TD_ES) {
382 #if 0 /* test-only */
383 printf("TX error status = 0x%08X\n",
384 le32_to_cpu(tx_ring[tx_new].status));
395 static int dc21x4x_recv(struct eth_device* dev)
401 status = (s32)le32_to_cpu(rx_ring[rx_new].status);
403 if (status & R_OWN) {
407 if (status & RD_LS) {
408 /* Valid frame status.
410 if (status & RD_ES) {
412 /* There was an error.
414 printf("RX error status = 0x%08X\n", status);
416 /* A valid frame received.
418 length = (le32_to_cpu(rx_ring[rx_new].status) >> 16);
420 /* Pass the packet up to the protocol
423 NetReceive(NetRxPackets[rx_new], length - 4);
426 /* Change buffer ownership for this frame, back
429 rx_ring[rx_new].status = cpu_to_le32(R_OWN);
432 /* Update entry information.
434 rx_new = (rx_new + 1) % rxRingSize;
440 static void dc21x4x_halt(struct eth_device* dev)
442 int devbusfn = (int) dev->priv;
445 OUTL(dev, 0, DE4X5_SICR);
447 pci_write_config_byte(devbusfn, PCI_CFDA_PSM, SLEEP);
450 static void send_setup_frame(struct eth_device* dev, bd_t *bis)
453 char setup_frame[SETUP_FRAME_LEN];
454 char *pa = &setup_frame[0];
456 memset(pa, 0xff, SETUP_FRAME_LEN);
458 for (i = 0; i < ETH_ALEN; i++) {
459 *(pa + (i & 1)) = dev->enetaddr[i];
465 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
466 if (i >= TOUT_LOOP) {
467 printf("%s: tx error buffer not ready\n", dev->name);
472 tx_ring[tx_new].buf = cpu_to_le32(phys_to_bus((u32) &setup_frame[0]));
473 tx_ring[tx_new].des1 = cpu_to_le32(TD_TER | TD_SET| SETUP_FRAME_LEN);
474 tx_ring[tx_new].status = cpu_to_le32(T_OWN);
476 OUTL(dev, POLL_DEMAND, DE4X5_TPD);
478 for(i = 0; tx_ring[tx_new].status & cpu_to_le32(T_OWN); i++) {
479 if (i >= TOUT_LOOP) {
480 printf("%s: tx buffer not ready\n", dev->name);
485 if (le32_to_cpu(tx_ring[tx_new].status) != 0x7FFFFFFF) {
486 printf("TX error status2 = 0x%08X\n", le32_to_cpu(tx_ring[tx_new].status));
492 /* SROM Read and write routines.
496 sendto_srom(struct eth_device* dev, u_int command, u_long addr)
498 OUTL(dev, command, addr);
503 getfrom_srom(struct eth_device* dev, u_long addr)
507 tmp = INL(dev, addr);
513 /* Note: this routine returns extra data bits for size detection. */
514 static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len)
518 int read_cmd = location | (SROM_READ_CMD << addr_len);
520 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
521 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
524 printf(" EEPROM read at %d ", location);
527 /* Shift the read command bits out. */
528 for (i = 4 + addr_len; i >= 0; i--) {
529 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
530 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval, ioaddr);
532 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | dataval | DT_CLK, ioaddr);
535 printf("%X", getfrom_srom(dev, ioaddr) & 15);
537 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
540 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
543 printf(" :%X:", getfrom_srom(dev, ioaddr) & 15);
546 for (i = 16; i > 0; i--) {
547 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
550 printf("%X", getfrom_srom(dev, ioaddr) & 15);
552 retval = (retval << 1) | ((getfrom_srom(dev, ioaddr) & EE_DATA_READ) ? 1 : 0);
553 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
557 /* Terminate the EEPROM access. */
558 sendto_srom(dev, SROM_RD | SROM_SR, ioaddr);
561 printf(" EEPROM value at %d is %5.5x.\n", location, retval);
567 /* This executes a generic EEPROM command, typically a write or write enable.
568 It returns the data output from the EEPROM, and thus may also be used for
570 static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
575 printf(" EEPROM op 0x%x: ", cmd);
578 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS | DT_CLK, ioaddr);
580 /* Shift the command bits out. */
582 short dataval = (cmd & (1 << cmd_len)) ? EE_WRITE_1 : EE_WRITE_0;
583 sendto_srom(dev,dataval, ioaddr);
587 printf("%X", getfrom_srom(dev,ioaddr) & 15);
590 sendto_srom(dev,dataval | DT_CLK, ioaddr);
592 retval = (retval << 1) | ((getfrom_srom(dev,ioaddr) & EE_DATA_READ) ? 1 : 0);
593 } while (--cmd_len >= 0);
594 sendto_srom(dev,SROM_RD | SROM_SR | DT_CS, ioaddr);
596 /* Terminate the EEPROM access. */
597 sendto_srom(dev,SROM_RD | SROM_SR, ioaddr);
600 printf(" EEPROM result is 0x%5.5x.\n", retval);
606 static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
608 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
610 return do_eeprom_cmd(dev, ioaddr,
611 (((SROM_READ_CMD << ee_addr_size) | index) << 16)
612 | 0xffff, 3 + ee_addr_size + 16);
616 static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
618 int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
620 unsigned short newval;
622 udelay(10*1000); /* test-only */
625 printf("ee_addr_size=%d.\n", ee_addr_size);
626 printf("Writing new entry 0x%4.4x to offset %d.\n", new_value, index);
629 /* Enable programming modes. */
630 do_eeprom_cmd(dev, ioaddr, (0x4f << (ee_addr_size-4)), 3+ee_addr_size);
632 /* Do the actual write. */
633 do_eeprom_cmd(dev, ioaddr,
634 (((SROM_WRITE_CMD<<ee_addr_size)|index) << 16) | new_value,
635 3 + ee_addr_size + 16);
637 /* Poll for write finished. */
638 sendto_srom(dev, SROM_RD | SROM_SR | DT_CS, ioaddr);
639 for (i = 0; i < 10000; i++) /* Typical 2000 ticks */
640 if (getfrom_srom(dev, ioaddr) & EE_DATA_READ)
644 printf(" Write finished after %d ticks.\n", i);
647 /* Disable programming. */
648 do_eeprom_cmd(dev, ioaddr, (0x40 << (ee_addr_size-4)), 3 + ee_addr_size);
650 /* And read the result. */
651 newval = do_eeprom_cmd(dev, ioaddr,
652 (((SROM_READ_CMD<<ee_addr_size)|index) << 16)
653 | 0xffff, 3 + ee_addr_size + 16);
655 printf(" New value at offset %d is %4.4x.\n", index, newval);
661 static void read_hw_addr(struct eth_device *dev, bd_t *bis)
663 u_short tmp, *p = (short *)(&dev->enetaddr[0]);
666 for (i = 0; i < (ETH_ALEN >> 1); i++) {
667 tmp = read_srom(dev, DE4X5_APROM, ((SROM_HWADD >> 1) + i));
668 *p = le16_to_cpu(tmp);
672 if ((j == 0) || (j == 0x2fffd)) {
673 memset (dev->enetaddr, 0, ETH_ALEN);
675 printf("Warning: can't read HW address from SROM.\n");
684 update_srom(dev, bis);
690 static void update_srom(struct eth_device *dev, bd_t *bis)
693 static unsigned short eeprom[0x40] = {
694 0x140b, 0x6610, 0x0000, 0x0000, /* 00 */
695 0x0000, 0x0000, 0x0000, 0x0000, /* 04 */
696 0x00a3, 0x0103, 0x0000, 0x0000, /* 08 */
697 0x0000, 0x1f00, 0x0000, 0x0000, /* 0c */
698 0x0108, 0x038d, 0x0000, 0x0000, /* 10 */
699 0xe078, 0x0001, 0x0040, 0x0018, /* 14 */
700 0x0000, 0x0000, 0x0000, 0x0000, /* 18 */
701 0x0000, 0x0000, 0x0000, 0x0000, /* 1c */
702 0x0000, 0x0000, 0x0000, 0x0000, /* 20 */
703 0x0000, 0x0000, 0x0000, 0x0000, /* 24 */
704 0x0000, 0x0000, 0x0000, 0x0000, /* 28 */
705 0x0000, 0x0000, 0x0000, 0x0000, /* 2c */
706 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
707 0x0000, 0x0000, 0x0000, 0x0000, /* 34 */
708 0x0000, 0x0000, 0x0000, 0x0000, /* 38 */
709 0x0000, 0x0000, 0x0000, 0x4e07, /* 3c */
712 /* Ethernet Addr... */
713 eeprom[0x0a] = ((bis->bi_enetaddr[1] & 0xff) << 8) | (bis->bi_enetaddr[0] & 0xff);
714 eeprom[0x0b] = ((bis->bi_enetaddr[3] & 0xff) << 8) | (bis->bi_enetaddr[2] & 0xff);
715 eeprom[0x0c] = ((bis->bi_enetaddr[5] & 0xff) << 8) | (bis->bi_enetaddr[4] & 0xff);
717 for (i=0; i<0x40; i++)
719 write_srom(dev, DE4X5_APROM, i, eeprom[i]);