1 /* ported from ctfb.c (linux kernel):
2 * Created in Jan - July 2000 by Thomas Höhenleitner <th@visuelle-maschinen.de>
5 * (C) Copyright 2002 Denis Peter, MPL AG Switzerland
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include "videomodes.h"
36 #ifdef CONFIG_VIDEO_CT69000
42 #define PRINTF(fmt,args...) printf (fmt ,##args)
44 #define PRINTF(fmt,args...)
49 #define min( a, b ) ( ( a ) < ( b ) ) ? ( a ) : ( b )
52 #define max( a, b ) ( ( a ) > ( b ) ) ? ( a ) : ( b )
55 #error "term minmax already used."
57 #define minmax( a, x, b ) max( ( a ), min( ( x ), ( b ) ) )
58 #define N_ELTS( x ) ( sizeof( x ) / sizeof( x[ 0 ] ) )
60 /* CT Register Offsets */
61 #define CT_AR_O 0x3c0 /* Index and Data write port of the attribute Registers */
62 #define CT_GR_O 0x3ce /* Index port of the Graphic Controller Registers */
63 #define CT_SR_O 0x3c4 /* Index port of the Sequencer Controller */
64 #define CT_CR_O 0x3d4 /* Index port of the CRT Controller */
65 #define CT_XR_O 0x3d6 /* Extended Register index */
66 #define CT_MSR_W_O 0x3c2 /* Misc. Output Register (write only) */
67 #define CT_LUT_MASK_O 0x3c6 /* Color Palette Mask */
68 #define CT_LUT_START_O 0x3c8 /* Color Palette Write Mode Index */
69 #define CT_LUT_RGB_O 0x3c9 /* Color Palette Data Port */
70 #define CT_STATUS_REG0_O 0x3c2 /* Status Register 0 (read only) */
71 #define CT_STATUS_REG1_O 0x3da /* Input Status Register 1 (read only) */
73 #define CT_FP_O 0x3d0 /* Index port of the Flat panel Registers */
74 #define CT_MR_O 0x3d2 /* Index Port of the Multimedia Extension */
76 /* defines for the memory mapped registers */
77 #define BR00_o 0x400000 /* Source and Destination Span Register */
78 #define BR01_o 0x400004 /* Pattern/Source Expansion Background Color & Transparency Key Register */
79 #define BR02_o 0x400008 /* Pattern/Source Expansion Foreground Color Register */
80 #define BR03_o 0x40000C /* Monochrome Source Control Register */
81 #define BR04_o 0x400010 /* BitBLT Control Register */
82 #define BR05_o 0x400014 /* Pattern Address Registe */
83 #define BR06_o 0x400018 /* Source Address Register */
84 #define BR07_o 0x40001C /* Destination Address Register */
85 #define BR08_o 0x400020 /* Destination Width & Height Register */
86 #define BR09_o 0x400024 /* Source Expansion Background Color & Transparency Key Register */
87 #define BR0A_o 0x400028 /* Source Expansion Foreground Color Register */
89 #define CURSOR_SIZE 0x1000 /* in KByte for HW Cursor */
90 #define PATTERN_ADR (pGD->dprBase + CURSOR_SIZE) /* pattern Memory after Cursor Memory */
91 #define PATTERN_SIZE 8*8*4 /* 4 Bytes per Pixel 8 x 8 Pixel */
92 #define ACCELMEMORY (CURSOR_SIZE + PATTERN_SIZE) /* reserved Memory for BITBlt and hw cursor */
94 /* Some Mode definitions */
95 #define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
96 #define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
97 #define FB_SYNC_EXT 4 /* external sync */
98 #define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
99 #define FB_SYNC_BROADCAST 16 /* broadcast video timings */
100 /* vtotal = 144d/288n/576i => PAL */
101 /* vtotal = 121d/242n/484i => NTSC */
102 #define FB_SYNC_ON_GREEN 32 /* sync on green */
104 #define FB_VMODE_NONINTERLACED 0 /* non interlaced */
105 #define FB_VMODE_INTERLACED 1 /* interlaced */
106 #define FB_VMODE_DOUBLE 2 /* double scan */
107 #define FB_VMODE_MASK 255
109 #define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
110 #define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
111 #define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
116 /* table for VGA Initialization */
118 const unsigned char reg;
119 const unsigned char val;
122 /* this table provides some basic initialisations such as Memory Clock etc */
123 static CT_CFG_TABLE xreg[] = {
124 {0x09, 0x01}, /* CRT Controller Extensions Enable */
125 {0x0A, 0x02}, /* Frame Buffer Mapping */
126 {0x0B, 0x01}, /* PCI Write Burst support */
127 {0x20, 0x00}, /* BitBLT Configuration */
128 {0x40, 0x03}, /* Memory Access Control */
129 {0x60, 0x00}, /* Video Pin Control */
130 {0x61, 0x00}, /* DPMS Synch control */
131 {0x62, 0x00}, /* GPIO Pin Control */
132 {0x63, 0xBD}, /* GPIO Pin Data */
133 {0x67, 0x00}, /* Pin Tri-State */
134 {0x80, 0x80}, /* Pixel Pipeline Config 0 register */
135 {0xA0, 0x00}, /* Cursor 1 Control Reg */
136 {0xA1, 0x00}, /* Cursor 1 Vertical Extension Reg */
137 {0xA2, 0x00}, /* Cursor 1 Base Address Low */
138 {0xA3, 0x00}, /* Cursor 1 Base Address High */
139 {0xA4, 0x00}, /* Cursor 1 X-Position Low */
140 {0xA5, 0x00}, /* Cursor 1 X-Position High */
141 {0xA6, 0x00}, /* Cursor 1 Y-Position Low */
142 {0xA7, 0x00}, /* Cursor 1 Y-Position High */
143 {0xA8, 0x00}, /* Cursor 2 Control Reg */
144 {0xA9, 0x00}, /* Cursor 2 Vertical Extension Reg */
145 {0xAA, 0x00}, /* Cursor 2 Base Address Low */
146 {0xAB, 0x00}, /* Cursor 2 Base Address High */
147 {0xAC, 0x00}, /* Cursor 2 X-Position Low */
148 {0xAD, 0x00}, /* Cursor 2 X-Position High */
149 {0xAE, 0x00}, /* Cursor 2 Y-Position Low */
150 {0xAF, 0x00}, /* Cursor 2 Y-Position High */
151 {0xC0, 0x7D}, /* Dot Clock 0 VCO M-Divisor */
152 {0xC1, 0x07}, /* Dot Clock 0 VCO N-Divisor */
153 {0xC3, 0x34}, /* Dot Clock 0 Divisor select */
154 {0xC4, 0x55}, /* Dot Clock 1 VCO M-Divisor */
155 {0xC5, 0x09}, /* Dot Clock 1 VCO N-Divisor */
156 {0xC7, 0x24}, /* Dot Clock 1 Divisor select */
157 {0xC8, 0x7D}, /* Dot Clock 2 VCO M-Divisor */
158 {0xC9, 0x07}, /* Dot Clock 2 VCO N-Divisor */
159 {0xCB, 0x34}, /* Dot Clock 2 Divisor select */
160 {0xCC, 0x38}, /* Memory Clock 0 VCO M-Divisor */
161 {0xCD, 0x03}, /* Memory Clock 0 VCO N-Divisor */
162 {0xCE, 0x90}, /* Memory Clock 0 Divisor select */
163 {0xCF, 0x06}, /* Clock Config */
164 {0xD0, 0x0F}, /* Power Down */
165 {0xD1, 0x01}, /* Power Down BitBLT */
166 {0xFF, 0xFF} /* end of table */
173 * Bit2 and Bit4..6 are used for the Loop Divisor and Post Divisor.
174 * They are encoded as follows:
176 * +---+--------------+
177 * | 2 | Loop Divisor |
178 * +---+--------------+
180 * +---+--------------+
182 * +---+--------------+
183 * Note: The Memory Clock does not have a Loop Divisor.
184 * +---+---+---+--------------+
185 * | 6 | 5 | 4 | Post Divisor |
186 * +---+---+---+--------------+
188 * +---+---+---+--------------+
190 * +---+---+---+--------------+
192 * +---+---+---+--------------+
194 * +---+---+---+--------------+
196 * +---+---+---+--------------+
198 * +---+---+---+--------------+
199 * | 1 | 1 | X | reserved |
200 * +---+---+---+--------------+
202 * All other bits are reserved in these registers.
204 * Clock VCO M Registers:
205 * ----------------------
206 * These Registers contain the M Value -2.
208 * Clock VCO N Registers:
209 * ----------------------
210 * These Registers contain the N Value -2.
214 * Fvco = (Fref * Loop Divisor * M/N), whereas 100MHz < Fvco < 220MHz
215 * Fout = Fvco / Post Divisor
217 * Dot Clk0 (default 25MHz):
218 * -------------------------
219 * Fvco = 14.318 * 127 / 9 = 202.045MHz
220 * Fout = 202.045MHz / 8 = 25.25MHz
223 * XRC0 = (M - 2) = 125 = 0x7D
224 * XRC1 = (N - 2) = 7 = 0x07
227 * Dot Clk1 (default 28MHz):
228 * -------------------------
229 * Fvco = 14.318 * 87 / 11 = 113.24MHz
230 * Fout = 113.24MHz / 4 = 28.31MHz
233 * XRC4 = (M - 2) = 85 = 0x55
234 * XRC5 = (N - 2) = 9 = 0x09
237 * Dot Clk2 (variable for extended modes set to 25MHz):
238 * ----------------------------------------------------
239 * Fvco = 14.318 * 127 / 9 = 202.045MHz
240 * Fout = 202.045MHz / 8 = 25.25MHz
243 * XRC8 = (M - 2) = 125 = 0x7D
244 * XRC9 = (N - 2) = 7 = 0x07
247 * Memory Clk for most modes >50MHz:
248 * ----------------------------------
249 * Fvco = 14.318 * 58 / 5 = 166MHz
250 * Fout = 166MHz / 2 = 83MHz
252 * XRCC = (M - 2) = 57 = 0x38
253 * XRCD = (N - 2) = 3 = 0x03
256 * Note Bit7 enables the clock source from the VCO
260 /*******************************************************************
262 *******************************************************************/
263 struct ctfb_chips_properties {
264 int device_id; /* PCI Device ID */
265 unsigned long max_mem; /* memory for frame buffer */
266 int vld_set; /* value of VLD if bit2 in clock control is set */
267 int vld_not_set; /* value of VLD if bit2 in clock control is set */
268 int mn_diff; /* difference between M/N Value + mn_diff = M/N Register */
269 int mn_min; /* min value of M/N Value */
270 int mn_max; /* max value of M/N Value */
271 int vco_min; /* VCO Min in MHz */
272 int vco_max; /* VCO Max in MHz */
275 static const struct ctfb_chips_properties chips[] = {
276 {PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
277 {PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
278 {0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
286 /*******************************************************************************
291 /*******************************************************************************
293 * Read CT ISA register
297 ctRead (unsigned short index)
299 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
300 if (index == CT_AR_O)
301 /* synch the Flip Flop */
302 in8 (pGD->isaBase + CT_STATUS_REG1_O);
304 return (in8 (pGD->isaBase + index));
307 /*******************************************************************************
309 * Write CT ISA register
312 ctWrite (unsigned short index, unsigned char val)
314 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
316 out8 ((pGD->isaBase + index), val);
319 /*******************************************************************************
321 * Read CT ISA register indexed
324 ctRead_i (unsigned short index, char reg)
326 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
327 if (index == CT_AR_O)
328 /* synch the Flip Flop */
329 in8 (pGD->isaBase + CT_STATUS_REG1_O);
330 out8 ((pGD->isaBase + index), reg);
331 return (in8 (pGD->isaBase + index + 1));
334 /*******************************************************************************
336 * Write CT ISA register indexed
339 ctWrite_i (unsigned short index, char reg, char val)
341 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
342 if (index == CT_AR_O) {
343 /* synch the Flip Flop */
344 in8 (pGD->isaBase + CT_STATUS_REG1_O);
345 out8 ((pGD->isaBase + index), reg);
346 out8 ((pGD->isaBase + index), val);
348 out8 ((pGD->isaBase + index), reg);
349 out8 ((pGD->isaBase + index + 1), val);
353 /*******************************************************************************
355 * Write a table of CT ISA register
358 ctLoadRegs (unsigned short index, CT_CFG_TABLE * regTab)
360 while (regTab->reg != 0xFF) {
361 ctWrite_i (index, regTab->reg, regTab->val);
366 /*****************************************************************************/
372 for (i = 0; i < 0x10; i++)
373 ctWrite_i (CT_AR_O, i, i);
379 ctWrite_i (CT_AR_O, 0x10, tmp); /* Mode Control Register */
380 ctWrite_i (CT_AR_O, 0x11, 0x00); /* Overscan Color Register */
381 ctWrite_i (CT_AR_O, 0x12, 0x0f); /* Memory Plane Enable Register */
386 ctWrite_i (CT_AR_O, 0x13, tmp); /* Horizontal Pixel Panning */
387 ctWrite_i (CT_AR_O, 0x14, 0x00); /* Color Select Register */
388 ctWrite (CT_AR_O, 0x20); /* enable video */
391 /*****************************************************************************/
394 { /* Set Graphics Mode */
397 for (i = 0; i < 0x05; i++)
398 ctWrite_i (CT_GR_O, i, 0);
400 ctWrite_i (CT_GR_O, 0x05, 0x10);
401 ctWrite_i (CT_GR_O, 0x06, 0x02);
403 ctWrite_i (CT_GR_O, 0x05, 0x40);
404 ctWrite_i (CT_GR_O, 0x06, 0x05);
406 ctWrite_i (CT_GR_O, 0x07, 0x0f);
407 ctWrite_i (CT_GR_O, 0x08, 0xff);
410 /*****************************************************************************/
416 ctWrite_i (CT_SR_O, 0x00, 0x00); /* reset */
417 /*rr( sr, 0x01, tmp );
418 if( fntwidth == 8 ) tmp |= 0x01; else tmp &= ~0x01;
419 wr( sr, 0x01, tmp ); */
421 ctWrite_i (CT_SR_O, 0x01, 0x01); /* Clocking Mode Register */
423 ctWrite_i (CT_SR_O, 0x01, 0x00); /* Clocking Mode Register */
424 ctWrite_i (CT_SR_O, 0x02, 0x0f); /* Enable CPU wr access to given memory plane */
425 ctWrite_i (CT_SR_O, 0x03, 0x00); /* Character Map Select Register */
430 ctWrite_i (CT_SR_O, 0x04, tmp); /* Enable CPU accesses to the rest of the 256KB
431 total VGA memory beyond the first 64KB and set
433 ctWrite_i (CT_SR_O, 0x00, 0x03); /* enable */
436 /*****************************************************************************/
438 SetBitsPerPixelIntoXrRegs (int bpp)
440 unsigned int n = (bpp >> 3), tmp; /* only for 15, 8, 16, 24 bpp */
441 static char md[4] = { 0x04, 0x02, 0x05, 0x06 }; /* DisplayColorMode */
442 static char off[4] = { ~0x20, ~0x30, ~0x20, ~0x10 }; /* mask */
443 static char on[4] = { 0x10, 0x00, 0x10, 0x20 }; /* mask */
446 tmp = ctRead_i (CT_XR_O, 0x20);
449 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
450 ctWrite_i (CT_XR_O, 0x81, md[n]);
453 /*****************************************************************************/
455 SetCrRegs (struct ctfb_res_modes *var, int bits_per_pixel)
456 { /* he -le- ht|0 hd -ri- hs -h- he */
457 unsigned char cr[0x7a];
459 unsigned int hd, hs, he, ht, hbe; /* Horizontal. */
460 unsigned int vd, vs, ve, vt; /* vertical */
461 unsigned int bpp, wd, dblscan, interlaced, bcast, CrtHalfLine;
462 unsigned int CompSyncCharClkDelay, CompSyncPixelClkDelay;
463 unsigned int NTSC_PAL_HorizontalPulseWidth, BlDelayCtrl;
464 unsigned int HorizontalEqualizationPulses;
465 unsigned int HorizontalSerration1Start, HorizontalSerration2Start;
467 const int LineCompare = 0x3ff;
468 unsigned int TextScanLines = 1; /* this is in fact a vertical zoom factor */
469 unsigned int RAMDAC_BlankPedestalEnable = 0; /* 1=en-, 0=disable, see XR82 */
471 hd = (var->xres) / 8; /* HDisp. */
472 hs = (var->xres + var->right_margin) / 8; /* HsStrt */
473 he = (var->xres + var->right_margin + var->hsync_len) / 8; /* HsEnd */
474 ht = (var->left_margin + var->xres + var->right_margin + var->hsync_len) / 8; /* HTotal */
475 hbe = ht - 1; /* HBlankEnable todo docu wants ht here, but it does not work */
476 /* ve -up- vt|0 vd -lo- vs -v- ve */
477 vd = var->yres; /* VDisplay */
478 vs = var->yres + var->lower_margin; /* VSyncStart */
479 ve = var->yres + var->lower_margin + var->vsync_len; /* VSyncEnd */
480 vt = var->upper_margin + var->yres + var->lower_margin + var->vsync_len; /* VTotal */
481 bpp = bits_per_pixel;
482 dblscan = (var->vmode & FB_VMODE_DOUBLE) ? 1 : 0;
483 interlaced = var->vmode & FB_VMODE_INTERLACED;
484 bcast = var->sync & FB_SYNC_BROADCAST;
485 CrtHalfLine = bcast ? (hd >> 1) : 0;
486 BlDelayCtrl = bcast ? 1 : 0;
487 CompSyncCharClkDelay = 0; /* 2 bit */
488 CompSyncPixelClkDelay = 0; /* 3 bit */
490 NTSC_PAL_HorizontalPulseWidth = 7; /*( var->hsync_len >> 1 ) + 1 */
491 HorizontalEqualizationPulses = 0; /* inverse value */
492 HorizontalSerration1Start = 31; /* ( ht >> 1 ) */
493 HorizontalSerration2Start = 89; /* ( ht >> 1 ) */
495 NTSC_PAL_HorizontalPulseWidth = 0;
496 /* 4 bit: hsync pulse width = ( ( CR74[4:0] - CR74[5] )
497 * / 2 ) + 1 --> CR74[4:0] = 2*(hs-1) + CR74[5] */
498 HorizontalEqualizationPulses = 1; /* inverse value */
499 HorizontalSerration1Start = 0; /* ( ht >> 1 ) */
500 HorizontalSerration2Start = 0; /* ( ht >> 1 ) */
505 wd = var->xres * bpp / 64; /* double words per line */
506 if (interlaced) { /* we divide all vertical timings, exept vd */
511 memset (cr, 0, sizeof (cr));
512 cr[0x00] = 0xff & (ht - 5);
513 cr[0x01] = hd - 1; /* soll:4f ist 59 */
515 cr[0x03] = (hbe & 0x1F) | 0x80; /* hd + ht - hd */
517 cr[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
518 cr[0x06] = (vt - 2) & 0xFF;
519 cr[0x30] = (vt - 2) >> 8;
520 cr[0x07] = ((vt & 0x100) >> 8)
521 | ((vd & 0x100) >> 7)
522 | ((vs & 0x100) >> 6)
523 | ((vs & 0x100) >> 5)
524 | ((LineCompare & 0x100) >> 4)
525 | ((vt & 0x200) >> 4)
526 | ((vd & 0x200) >> 3)
527 | ((vs & 0x200) >> 2);
529 cr[0x09] = (dblscan << 7)
530 | ((LineCompare & 0x200) >> 3)
531 | ((vs & 0x200) >> 4)
532 | (TextScanLines - 1);
533 cr[0x10] = vs & 0xff; /* VSyncPulseStart */
534 cr[0x32] = (vs & 0xf00) >> 8; /* VSyncPulseStart */
535 cr[0x11] = (ve & 0x0f); /* | 0x20; */
536 cr[0x12] = (vd - 1) & 0xff; /* LineCount */
537 cr[0x31] = ((vd - 1) & 0xf00) >> 8; /* LineCount */
538 cr[0x13] = wd & 0xff;
539 cr[0x41] = (wd & 0xf00) >> 8;
540 cr[0x15] = vs & 0xff;
541 cr[0x33] = (vs & 0xf00) >> 8;
542 cr[0x38] = (0x100 & (ht - 5)) >> 8;
543 cr[0x3C] = 0xc0 & hbe;
544 cr[0x16] = (vt - 1) & 0xff; /* vbe - docu wants vt here, */
545 cr[0x17] = 0xe3; /* but it does not work */
546 cr[0x18] = 0xff & LineCompare;
547 cr[0x22] = 0xff; /* todo? */
548 cr[0x70] = interlaced ? (0x80 | CrtHalfLine) : 0x00; /* check:0xa6 */
549 cr[0x71] = 0x80 | (RAMDAC_BlankPedestalEnable << 6)
551 | ((0x03 & CompSyncCharClkDelay) << 3)
552 | (0x07 & CompSyncPixelClkDelay); /* todo: see XR82 */
553 cr[0x72] = HorizontalSerration1Start;
554 cr[0x73] = HorizontalSerration2Start;
555 cr[0x74] = (HorizontalEqualizationPulses << 5)
556 | NTSC_PAL_HorizontalPulseWidth;
557 /* todo: ct69000 has also 0x75-79 */
558 /* now set the registers */
559 for (i = 0; i <= 0x0d; i++) { /*CR00 .. CR0D */
560 ctWrite_i (CT_CR_O, i, cr[i]);
562 for (i = 0x10; i <= 0x18; i++) { /*CR10 .. CR18 */
563 ctWrite_i (CT_CR_O, i, cr[i]);
566 ctWrite_i (CT_CR_O, i, cr[i]);
567 for (i = 0x30; i <= 0x33; i++) { /*CR30 .. CR33 */
568 ctWrite_i (CT_CR_O, i, cr[i]);
571 ctWrite_i (CT_CR_O, i, cr[i]);
573 ctWrite_i (CT_CR_O, i, cr[i]);
574 for (i = 0x40; i <= 0x41; i++) { /*CR40 .. CR41 */
575 ctWrite_i (CT_CR_O, i, cr[i]);
577 for (i = 0x70; i <= 0x74; i++) { /*CR70 .. CR74 */
578 ctWrite_i (CT_CR_O, i, cr[i]);
580 tmp = ctRead_i (CT_CR_O, 0x40);
583 ctWrite_i (CT_CR_O, 0x40, tmp); /* StartAddressEnable */
586 /* pixelclock control */
588 /*****************************************************************************
589 We have a rational number p/q and need an m/n which is very close to p/q
590 but has m and n within mnmin and mnmax. We have no floating point in the
591 kernel. We can use long long without divide. And we have time to compute...
592 ******************************************************************************/
594 FindBestPQFittingMN (unsigned int p, unsigned int q, unsigned int mnmin,
595 unsigned int mnmax, unsigned int *pm, unsigned int *pn)
597 /* this code is not for general purpose usable but good for our number ranges */
598 unsigned int n = mnmin, m = 0;
599 long long int L = 0, P = p, Q = q, H = P >> 1;
600 long long int D = 0x7ffffffffffffffLL;
601 for (n = mnmin; n <= mnmax; n++) {
602 m = mnmin; /* p/q ~ m/n -> p*n ~ m*q -> p*n-x*q ~ 0 */
603 L = P * n - m * Q; /* n * vco - m * fref should be near 0 */
604 while (L > 0 && m < mnmax) {
605 L -= q; /* difference is greater as 0 subtract fref */
606 m++; /* and increment m */
608 /* difference is less or equal than 0 or m > maximum */
610 break; /* no solution: if we increase n we get the same situation */
612 if (-L > H && m > mnmin) { /* if difference > the half fref */
613 L += q; /* we take the situation before */
614 m--; /* because its closer to 0 */
616 L = (L < 0) ? -L : +L; /* absolute value */
617 if (D < L) /* if last difference was better take next n */
621 *pn = n; /* keep improved data */
623 break; /* best result we can get */
625 return (unsigned int) (0xffffffff & D);
628 /* that is the hardware < 69000 we have to manage
629 +---------+ +-------------------+ +----------------------+ +--+
630 | REFCLK |__|NTSC Divisor Select|__|FVCO Reference Divisor|__|÷N|__
631 | 14.3MHz | |(NTSCDS) (÷1, ÷5) | |Select (RDS) (÷1, ÷4) | | | |
632 +---------+ +-------------------+ +----------------------+ +--+ |
633 ___________________________________________________________________|
636 | +--------+ +------------+ +-----+ +-------------------+ +----+
637 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
638 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
639 | +--------+ +------------+ +-----+ | +-------------------+ +----+
641 | +--+ +---------------+ |
642 |____|÷M|___|VCO Loop Divide|__________|
643 | | |(VLD)(÷4, ÷16) |
644 +--+ +---------------+
645 ****************************************************************************
646 that is the hardware >= 69000 we have to manage
654 | +--------+ +------------+ +-----+ +-------------------+ +----+
655 +-| Phase |__|Charge Pump |__| VCO |_____|Post Divisor (PD) |___|CLK |--->
656 +-| Detect | |& Filter VCO| | | | |÷1, 2, 4, 8, 16, 32| | |
657 | +--------+ +------------+ +-----+ | +-------------------+ +----+
659 | +--+ +---------------+ |
660 |____|÷M|___|VCO Loop Divide|__________|
662 +--+ +---------------+
667 #define VIDEO_FREF 14318180; /* Hz */
668 /*****************************************************************************/
670 ReadPixClckFromXrRegsBack (struct ctfb_chips_properties *param)
672 unsigned int m, n, vld, pd, PD, fref, xr_cb, i, pixclock;
676 m = ctRead_i (CT_XR_O, 0xc8);
677 n = ctRead_i (CT_XR_O, 0xc9);
680 xr_cb = ctRead_i (CT_XR_O, 0xcb);
681 PD = (0x70 & xr_cb) >> 4;
683 for (i = 0; i < PD; i++) {
686 vld = (0x04 & xr_cb) ? param->vld_set : param->vld_not_set;
688 unsigned long long p = 1000000000000LL * pd * n;
689 unsigned long long q = (long long) fref * vld * m;
690 while ((p > 0xffffffffLL) || (q > 0xffffffffLL)) {
691 p >>= 1; /* can't divide with long long so we scale down */
694 pixclock = (unsigned) p / (unsigned) q;
696 printf ("Invalid data in xr regs.\n");
700 /*****************************************************************************/
702 FindAndSetPllParamIntoXrRegs (unsigned int pixelclock,
703 struct ctfb_chips_properties *param)
705 unsigned int m, n, vld, pd, PD, fref, xr_cb;
706 unsigned int fvcomin, fvcomax, pclckmin, pclckmax, pclk;
707 unsigned int pfreq, fvco, new_pixclock;
708 unsigned int D,nback,mback;
713 fvcomin = param->vco_min;
714 fvcomax = param->vco_max; /* MHz */
715 pclckmin = 1000000 / fvcomax + 1; /* 4546 */
716 pclckmax = 32000000 / fvcomin - 1; /* 666665 */
717 pclk = minmax (pclckmin, pixelclock, pclckmax); /* ps pp */
718 pfreq = 250 * (4000000000U / pclk);
719 fvco = pfreq; /* Hz */
721 while (fvco < fvcomin * 1000000) {
722 /* double VCO starting with the pixelclock frequency
723 * as long as it is lower than the minimal VCO frequency */
728 /* fvco is exactly pd * pixelclock and higher than the ninmal VCO frequency */
730 vld = param->vld_set;
731 D=FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n); /* rds = 1 */
735 vld = param->vld_not_set;
736 if(D<FindBestPQFittingMN (fvco / vld, fref, param->mn_min, param->mn_max, &m, &n)) { /* rds = 1 */
737 /* first try was better */
740 vld = param->vld_set;
744 PRINTF ("VCO %d, pd %d, m %d n %d vld %d \n", fvco, pd, m, n, vld);
745 xr_cb = ((0x7 & PD) << 4) | (vld == param->vld_set ? 0x04 : 0);
746 /* All four of the registers used for dot clock 2 (XRC8 - XRCB) must be
747 * written, and in order from XRC8 to XRCB, before the hardware will
748 * update the synthesizer s settings.
750 ctWrite_i (CT_XR_O, 0xc8, m);
751 ctWrite_i (CT_XR_O, 0xc9, n); /* xrca does not exist in CT69000 and CT69030 */
752 ctWrite_i (CT_XR_O, 0xca, 0); /* because of a hw bug I guess, but we write */
753 ctWrite_i (CT_XR_O, 0xcb, xr_cb); /* 0 to it for savety */
754 new_pixclock = ReadPixClckFromXrRegsBack (param);
755 PRINTF ("pixelclock.set = %d, pixelclock.real = %d \n",
756 pixelclock, new_pixclock);
759 /*****************************************************************************/
761 SetMsrRegs (struct ctfb_res_modes *mode)
763 unsigned char h_synch_high, v_synch_high;
765 h_synch_high = (mode->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 0x40; /* horizontal Synch High active */
766 v_synch_high = (mode->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 0x80; /* vertical Synch High active */
767 ctWrite (CT_MSR_W_O, (h_synch_high | v_synch_high | 0x29));
768 /* upper64K==0x20, CLC2select==0x08, RAMenable==0x02!(todo), CGA==0x01
769 * Selects the upper 64KB page.Bit5=1
770 * CLK2 (left reserved in standard VGA) Bit3|2=1|0
771 * Disables CPU access to frame buffer. Bit1=0
772 * Sets the I/O address decode for ST01, FCR, and all CR registers
773 * to the 3Dx I/O address range (CGA emulation). Bit0=1
777 /************************************************************************************/
781 ctDispRegs (unsigned short index, int from, int to)
783 unsigned char status;
786 for (i = from; i < to; i++) {
787 status = ctRead_i (index, i);
788 printf ("%02X: is %02X\n", i, status);
793 video_dump_reg (void)
797 printf ("Extended Regs:\n");
798 ctDispRegs (CT_XR_O, 0, 0xC);
799 ctDispRegs (CT_XR_O, 0xe, 0xf);
800 ctDispRegs (CT_XR_O, 0x20, 0x21);
801 ctDispRegs (CT_XR_O, 0x40, 0x50);
802 ctDispRegs (CT_XR_O, 0x60, 0x64);
803 ctDispRegs (CT_XR_O, 0x67, 0x68);
804 ctDispRegs (CT_XR_O, 0x70, 0x72);
805 ctDispRegs (CT_XR_O, 0x80, 0x83);
806 ctDispRegs (CT_XR_O, 0xA0, 0xB0);
807 ctDispRegs (CT_XR_O, 0xC0, 0xD3);
808 printf ("Sequencer Regs:\n");
809 ctDispRegs (CT_SR_O, 0, 0x8);
810 printf ("Graphic Regs:\n");
811 ctDispRegs (CT_GR_O, 0, 0x9);
812 printf ("CRT Regs:\n");
813 ctDispRegs (CT_CR_O, 0, 0x19);
814 ctDispRegs (CT_CR_O, 0x22, 0x23);
815 ctDispRegs (CT_CR_O, 0x30, 0x34);
816 ctDispRegs (CT_CR_O, 0x38, 0x39);
817 ctDispRegs (CT_CR_O, 0x3C, 0x3D);
818 ctDispRegs (CT_CR_O, 0x40, 0x42);
819 ctDispRegs (CT_CR_O, 0x70, 0x80);
820 /* don't display the attributes */
825 #ifdef CONFIG_VIDEO_HW_CURSOR
826 /***************************************************************
827 * Set Hardware Cursor in Pixel
830 video_set_hw_cursor (int x, int y)
832 int sig_x = 0, sig_y = 0;
841 ctWrite_i (CT_XR_O, 0xa4, x & 0xff);
842 ctWrite_i (CT_XR_O, 0xa5, (x >> 8) & 0x7);
843 ctWrite_i (CT_XR_O, 0xa6, y & 0xff);
844 ctWrite_i (CT_XR_O, 0xa7, (y >> 8) & 0x7);
847 /***************************************************************
848 * Init Hardware Cursor. To know the size of the Cursor,
849 * we have to know the Font size.
852 video_init_hw_cursor (int font_width, int font_height)
855 unsigned long *curs, pattern;
858 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
860 cursor_start = pGD->dprBase;
861 xr_80 = ctRead_i (CT_XR_O, 0x80);
862 /* set start address */
863 ctWrite_i (CT_XR_O, 0xa2, (cursor_start >> 8) & 0xf0);
864 ctWrite_i (CT_XR_O, 0xa3, (cursor_start >> 16) & 0x3f);
865 /* set cursor shape */
866 curs = (unsigned long *) cursor_start;
869 curs[i++] = 0xffffffff; /* AND mask */
870 curs[i++] = 0xffffffff; /* AND mask */
871 curs[i++] = 0; /* XOR mask */
872 curs[i++] = 0; /* XOR mask */
875 pattern = 0xffffffff >> font_width;
877 while (i < (font_height * 2)) {
878 curs[i++] = pattern; /* AND mask */
879 curs[i++] = pattern; /* AND mask */
880 curs[i++] = 0; /* XOR mask */
881 curs[i++] = 0; /* XOR mask */
885 ctWrite_i (CT_FP_O, 0x19, 0xf);
887 /* set cursors colors */
888 xr_80 = ctRead_i (CT_XR_O, 0x80);
889 xr_80 |= 0x1; /* alternate palette select */
890 ctWrite_i (CT_XR_O, 0x80, xr_80);
891 video_set_lut (4, CONSOLE_FG_COL, CONSOLE_FG_COL, CONSOLE_FG_COL);
892 /* position 4 is color 0 cursor 0 */
893 xr_80 &= 0xfe; /* normal palette select */
894 ctWrite_i (CT_XR_O, 0x80, xr_80);
896 ctWrite_i (CT_XR_O, 0xa0, 0x91);
897 xr_80 |= 0x10; /* enable hwcursor */
898 ctWrite_i (CT_XR_O, 0x80, xr_80);
899 video_set_hw_cursor (0, 0);
901 #endif /* CONFIG_VIDEO_HW_CURSOR */
903 /***************************************************************
904 * Wait for BitBlt ready
907 video_wait_bitblt (unsigned long addr)
912 while (br04 & 0x80000000) {
916 printf ("ERROR Timeout %lx\n", br04);
923 /***************************************************************
924 * Set up BitBlt Registrs
927 SetDrawingEngine (int bits_per_pixel)
929 unsigned long br04, br00;
932 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
934 tmp = ctRead_i (CT_XR_O, 0x20); /* BitBLT Configuration */
935 tmp |= 0x02; /* reset BitBLT */
936 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
938 tmp &= 0xfd; /* release reset BitBLT */
939 ctWrite_i (CT_XR_O, 0x20, tmp); /* BitBLT Configuration */
940 video_wait_bitblt (pGD->pciBase + BR04_o);
942 /* set pattern Address */
943 out32r (pGD->pciBase + BR05_o, PATTERN_ADR & 0x003ffff8);
945 if (bits_per_pixel == 1) {
946 br04 |= 0x00040000; /* monochome Pattern */
947 br04 |= 0x00001000; /* monochome source */
949 br00 = ((pGD->winSizeX * pGD->gdfBytesPP) << 16) + (pGD->winSizeX * pGD->gdfBytesPP); /* bytes per scanline */
950 out32r (pGD->pciBase + BR00_o, br00); /* */
951 out32r (pGD->pciBase + BR08_o, (10 << 16) + 10); /* dummy */
952 out32r (pGD->pciBase + BR04_o, br04); /* write all 0 */
953 out32r (pGD->pciBase + BR07_o, 0); /* destination */
954 video_wait_bitblt (pGD->pciBase + BR04_o);
957 /****************************************************************************
958 * supported Video Chips
960 static struct pci_device_id supported[] = {
961 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
965 /*******************************************************************************
972 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
973 unsigned short device_id;
976 unsigned long t1, hsynch, vsynch;
977 unsigned int pci_mem_base, *vm;
978 int tmp, i, bits_per_pixel;
980 struct ctfb_res_modes *res_mode;
981 struct ctfb_res_modes var_mode;
982 struct ctfb_chips_properties *chips_param;
983 /* Search for video chip */
985 if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
986 #ifdef CONFIG_VIDEO_ONBOARD
987 printf ("Video: Controller not found !\n");
993 pci_write_config_dword (devbusfn, PCI_COMMAND,
994 (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
995 pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
996 pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
997 pci_mem_base = pci_mem_to_phys (devbusfn, pci_mem_base);
999 /* get chips params */
1000 for (chips_param = (struct ctfb_chips_properties *) &chips[0];
1001 chips_param->device_id != 0; chips_param++) {
1002 if (chips_param->device_id == device_id)
1005 if (chips_param->device_id == 0) {
1006 #ifdef CONFIG_VIDEO_ONBOARD
1007 printf ("Video: controller 0x%X not supported\n", device_id);
1011 /* supported Video controller found */
1016 /* get video mode via environment */
1017 if ((penv = getenv ("videomode")) != NULL) {
1018 /* deceide if it is a string */
1019 if (penv[0] <= '9') {
1020 videomode = (int) simple_strtoul (penv, NULL, 16);
1027 /* parameter are vesa modes */
1029 for (i = 0; i < VESA_MODES_COUNT; i++) {
1030 if (vesa_modes[i].vesanr == videomode)
1033 if (i == VESA_MODES_COUNT) {
1034 printf ("no VESA Mode found, switching to mode 0x301 ");
1038 (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].
1040 bits_per_pixel = vesa_modes[i].bits_per_pixel;
1043 res_mode = (struct ctfb_res_modes *) &var_mode;
1044 bits_per_pixel = video_get_params (res_mode, penv);
1047 /* calculate available color depth for controller memory */
1048 if (bits_per_pixel == 15)
1051 tmp = bits_per_pixel >> 3; /* /8 */
1052 if (((chips_param->max_mem -
1053 ACCELMEMORY) / (res_mode->xres * res_mode->yres)) < tmp) {
1055 ((chips_param->max_mem -
1056 ACCELMEMORY) / (res_mode->xres * res_mode->yres));
1059 ("No matching videomode found .-> reduce resolution\n");
1062 printf ("Switching back to %d Bits per Pixel ",
1064 bits_per_pixel = tmp << 3;
1068 /* calculate hsynch and vsynch freq (info only) */
1069 t1 = (res_mode->left_margin + res_mode->xres +
1070 res_mode->right_margin + res_mode->hsync_len) / 8;
1072 t1 *= res_mode->pixclock;
1074 hsynch = 1000000000L / t1;
1076 (res_mode->upper_margin + res_mode->yres +
1077 res_mode->lower_margin + res_mode->vsync_len);
1079 vsynch = 1000000000L / t1;
1081 /* fill in Graphic device struct */
1082 sprintf (pGD->modeIdent, "%dx%dx%d %ldkHz %ldHz", res_mode->xres,
1083 res_mode->yres, bits_per_pixel, (hsynch / 1000),
1085 printf ("%s\n", pGD->modeIdent);
1086 pGD->winSizeX = res_mode->xres;
1087 pGD->winSizeY = res_mode->yres;
1088 pGD->plnSizeX = res_mode->xres;
1089 pGD->plnSizeY = res_mode->yres;
1090 switch (bits_per_pixel) {
1092 pGD->gdfBytesPP = 1;
1093 pGD->gdfIndex = GDF__8BIT_INDEX;
1096 pGD->gdfBytesPP = 2;
1097 pGD->gdfIndex = GDF_15BIT_555RGB;
1100 pGD->gdfBytesPP = 2;
1101 pGD->gdfIndex = GDF_16BIT_565RGB;
1104 pGD->gdfBytesPP = 3;
1105 pGD->gdfIndex = GDF_24BIT_888RGB;
1108 pGD->isaBase = CFG_ISA_IO_BASE_ADDRESS;
1109 pGD->pciBase = pci_mem_base;
1110 pGD->frameAdrs = pci_mem_base;
1111 pGD->memSize = chips_param->max_mem;
1112 /* Cursor Start Address */
1114 (pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP) + pci_mem_base;
1115 if ((pGD->dprBase & 0x0fff) != 0) {
1117 pGD->dprBase &= 0xfffff000;
1118 pGD->dprBase += 0x00001000;
1120 PRINTF ("Cursor Start %x Pattern Start %x\n", pGD->dprBase,
1122 pGD->vprBase = pci_mem_base; /* Dummy */
1123 pGD->cprBase = pci_mem_base; /* Dummy */
1124 /* set up Hardware */
1126 ctWrite (CT_MSR_W_O, 0x01);
1128 /* set the extended Registers */
1129 ctLoadRegs (CT_XR_O, xreg);
1130 /* set atribute registers */
1132 /* set Graphics register */
1138 SetMsrRegs (res_mode);
1140 /* set CRT Registers */
1141 SetCrRegs (res_mode, bits_per_pixel);
1142 /* set color mode */
1143 SetBitsPerPixelIntoXrRegs (bits_per_pixel);
1146 FindAndSetPllParamIntoXrRegs (res_mode->pixclock, chips_param);
1148 ctWrite_i (CT_SR_O, 0, 0x03); /* clear synchronous reset */
1149 /* Clear video memory */
1150 i = pGD->memSize / 4;
1151 vm = (unsigned int *) pGD->pciBase;
1154 SetDrawingEngine (bits_per_pixel);
1159 return ((void *) &ctfb);
1162 /*******************************************************************************
1164 * Set a RGB color in the LUT (8 bit index)
1167 video_set_lut (unsigned int index, /* color number */
1168 unsigned char r, /* red */
1169 unsigned char g, /* green */
1170 unsigned char b /* blue */
1174 ctWrite (CT_LUT_MASK_O, 0xff);
1176 ctWrite (CT_LUT_START_O, (char) index);
1178 ctWrite (CT_LUT_RGB_O, r); /* red */
1179 ctWrite (CT_LUT_RGB_O, g); /* green */
1180 ctWrite (CT_LUT_RGB_O, b); /* blue */
1182 ctWrite (CT_LUT_MASK_O, 0xff);
1185 /*******************************************************************************
1187 * Drawing engine fill on screen region
1190 video_hw_rectfill (unsigned int bpp, /* bytes per pixel */
1191 unsigned int dst_x, /* dest pos x */
1192 unsigned int dst_y, /* dest pos y */
1193 unsigned int dim_x, /* frame width */
1194 unsigned int dim_y, /* frame height */
1195 unsigned int color /* fill color */
1198 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1199 unsigned long *p, br04;
1201 video_wait_bitblt (pGD->pciBase + BR04_o);
1203 p = (unsigned long *) PATTERN_ADR;
1206 bpp++; /* 24Bit needs a 32bit pattern */
1207 memset (p, color, (bpp * sizeof (unsigned char) * 8 * 8)); /* 8 x 8 pattern data */
1208 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1209 br04 = in32r (pGD->pciBase + BR04_o) & 0xffffff00;
1210 br04 |= 0xF0; /* write Pattern P -> D */
1211 out32r (pGD->pciBase + BR04_o, br04); /* */
1212 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* starts the BITBlt */
1213 video_wait_bitblt (pGD->pciBase + BR04_o);
1216 /*******************************************************************************
1218 * Drawing engine bitblt with screen region
1221 video_hw_bitblt (unsigned int bpp, /* bytes per pixel */
1222 unsigned int src_x, /* source pos x */
1223 unsigned int src_y, /* source pos y */
1224 unsigned int dst_x, /* dest pos x */
1225 unsigned int dst_y, /* dest pos y */
1226 unsigned int dim_x, /* frame width */
1227 unsigned int dim_y /* frame height */
1230 GraphicDevice *pGD = (GraphicDevice *) & ctfb;
1233 br04 = in32r (pGD->pciBase + BR04_o);
1235 /* to prevent data corruption due to overlap, we have to
1236 * find out if, and how the frames overlaps */
1237 if (src_x < dst_x) {
1238 /* src is more left than dest
1239 * the frame may overlap -> start from right to left */
1240 br04 |= 0x00000100; /* set bit 8 */
1244 br04 &= 0xfffffeff; /* clear bit 8 left to right */
1246 if (src_y < dst_y) {
1247 /* src is higher than dst
1248 * the frame may overlap => start from bottom */
1249 br04 |= 0x00000200; /* set bit 9 */
1253 br04 &= 0xfffffdff; /* clear bit 9 top to bottom */
1256 out32r (pGD->pciBase + BR06_o, ((pGD->winSizeX * src_y) + src_x) * pGD->gdfBytesPP); /* source */
1257 out32r (pGD->pciBase + BR07_o, ((pGD->winSizeX * dst_y) + dst_x) * pGD->gdfBytesPP); /* destination */
1259 br04 |= 0x000000CC; /* S -> D */
1260 out32r (pGD->pciBase + BR04_o, br04); /* */
1261 out32r (pGD->pciBase + BR08_o, (dim_y << 16) + dim_x); /* start the BITBlt */
1262 video_wait_bitblt (pGD->pciBase + BR04_o);
1265 #endif /* CONFIG_CT69000 */
1267 #endif /* CONFIG_VIDEO */