drivers/crypto/n2_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
   3  *
   4  * Copyright (C) 2010, 2011 David S. Miller <davem@davemloft.net>
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/cpumask.h>
  14 #include <linux/slab.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/crypto.h>
  17 #include <crypto/md5.h>
  18 #include <crypto/sha.h>
  19 #include <crypto/aes.h>
  20 #include <crypto/des.h>
  21 #include <linux/mutex.h>
  22 #include <linux/delay.h>
  23 #include <linux/sched.h>
  24
  25 #include <crypto/internal/hash.h>
  26 #include <crypto/scatterwalk.h>
  27 #include <crypto/algapi.h>
  28
  29 #include <asm/hypervisor.h>
  30 #include <asm/mdesc.h>
  31
  32 #include "n2_core.h"
  33
  34 #define DRV_MODULE_NAME         "n2_crypto"
  35 #define DRV_MODULE_VERSION      "0.2"
  36 #define DRV_MODULE_RELDATE      "July 28, 2011"
  37
  38 static const char version[] =
  39         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  40
  41 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
  42 MODULE_DESCRIPTION("Niagara2 Crypto driver");
  43 MODULE_LICENSE("GPL");
  44 MODULE_VERSION(DRV_MODULE_VERSION);
  45
  46 #define N2_CRA_PRIORITY         200
  47
  48 static DEFINE_MUTEX(spu_lock);
  49
  50 struct spu_queue {
  51         cpumask_t               sharing;
  52         unsigned long           qhandle;
  53
  54         spinlock_t              lock;
  55         u8                      q_type;
  56         void                    *q;
  57         unsigned long           head;
  58         unsigned long           tail;
  59         struct list_head        jobs;
  60
  61         unsigned long           devino;
  62
  63         char                    irq_name[32];
  64         unsigned int            irq;
  65
  66         struct list_head        list;
  67 };
  68
  69 struct spu_qreg {
  70         struct spu_queue        *queue;
  71         unsigned long           type;
  72 };
  73
  74 static struct spu_queue **cpu_to_cwq;
  75 static struct spu_queue **cpu_to_mau;
  76
  77 static unsigned long spu_next_offset(struct spu_queue *q, unsigned long off)
  78 {
  79         if (q->q_type == HV_NCS_QTYPE_MAU) {
  80                 off += MAU_ENTRY_SIZE;
  81                 if (off == (MAU_ENTRY_SIZE * MAU_NUM_ENTRIES))
  82                         off = 0;
  83         } else {
  84                 off += CWQ_ENTRY_SIZE;
  85                 if (off == (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES))
  86                         off = 0;
  87         }
  88         return off;
  89 }
  90
  91 struct n2_request_common {
  92         struct list_head        entry;
  93         unsigned int            offset;
  94 };
  95 #define OFFSET_NOT_RUNNING      (~(unsigned int)0)
  96
  97 /* An async job request records the final tail value it used in
  98  * n2_request_common->offset, test to see if that offset is in
  99  * the range old_head, new_head, inclusive.
 100  */
 101 static inline bool job_finished(struct spu_queue *q, unsigned int offset,
 102                                 unsigned long old_head, unsigned long new_head)
 103 {
 104         if (old_head <= new_head) {
 105                 if (offset > old_head && offset <= new_head)
 106                         return true;
 107         } else {
 108                 if (offset > old_head || offset <= new_head)
 109                         return true;
 110         }
 111         return false;
 112 }
 113
 114 /* When the HEAD marker is unequal to the actual HEAD, we get
 115  * a virtual device INO interrupt.  We should process the
 116  * completed CWQ entries and adjust the HEAD marker to clear
 117  * the IRQ.
 118  */
 119 static irqreturn_t cwq_intr(int irq, void *dev_id)
 120 {
 121         unsigned long off, new_head, hv_ret;
 122         struct spu_queue *q = dev_id;
 123
 124         pr_err("CPU[%d]: Got CWQ interrupt for qhdl[%lx]\n",
 125                smp_processor_id(), q->qhandle);
 126
 127         spin_lock(&q->lock);
 128
 129         hv_ret = sun4v_ncs_gethead(q->qhandle, &new_head);
 130
 131         pr_err("CPU[%d]: CWQ gethead[%lx] hv_ret[%lu]\n",
 132                smp_processor_id(), new_head, hv_ret);
 133
 134         for (off = q->head; off != new_head; off = spu_next_offset(q, off)) {
 135                 /* XXX ... XXX */
 136         }
 137
 138         hv_ret = sun4v_ncs_sethead_marker(q->qhandle, new_head);
 139         if (hv_ret == HV_EOK)
 140                 q->head = new_head;
 141
 142         spin_unlock(&q->lock);
 143
 144         return IRQ_HANDLED;
 145 }
 146
 147 static irqreturn_t mau_intr(int irq, void *dev_id)
 148 {
 149         struct spu_queue *q = dev_id;
 150         unsigned long head, hv_ret;
 151
 152         spin_lock(&q->lock);
 153
 154         pr_err("CPU[%d]: Got MAU interrupt for qhdl[%lx]\n",
 155                smp_processor_id(), q->qhandle);
 156
 157         hv_ret = sun4v_ncs_gethead(q->qhandle, &head);
 158
 159         pr_err("CPU[%d]: MAU gethead[%lx] hv_ret[%lu]\n",
 160                smp_processor_id(), head, hv_ret);
 161
 162         sun4v_ncs_sethead_marker(q->qhandle, head);
 163
 164         spin_unlock(&q->lock);
 165
 166         return IRQ_HANDLED;
 167 }
 168
 169 static void *spu_queue_next(struct spu_queue *q, void *cur)
 170 {
 171         return q->q + spu_next_offset(q, cur - q->q);
 172 }
 173
 174 static int spu_queue_num_free(struct spu_queue *q)
 175 {
 176         unsigned long head = q->head;
 177         unsigned long tail = q->tail;
 178         unsigned long end = (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES);
 179         unsigned long diff;
 180
 181         if (head > tail)
 182                 diff = head - tail;
 183         else
 184                 diff = (end - tail) + head;
 185
 186         return (diff / CWQ_ENTRY_SIZE) - 1;
 187 }
 188
 189 static void *spu_queue_alloc(struct spu_queue *q, int num_entries)
 190 {
 191         int avail = spu_queue_num_free(q);
 192
 193         if (avail >= num_entries)
 194                 return q->q + q->tail;
 195
 196         return NULL;
 197 }
 198
 199 static unsigned long spu_queue_submit(struct spu_queue *q, void *last)
 200 {
 201         unsigned long hv_ret, new_tail;
 202
 203         new_tail = spu_next_offset(q, last - q->q);
 204
 205         hv_ret = sun4v_ncs_settail(q->qhandle, new_tail);
 206         if (hv_ret == HV_EOK)
 207                 q->tail = new_tail;
 208         return hv_ret;
 209 }
 210
 211 static u64 control_word_base(unsigned int len, unsigned int hmac_key_len,
 212                              int enc_type, int auth_type,
 213                              unsigned int hash_len,
 214                              bool sfas, bool sob, bool eob, bool encrypt,
 215                              int opcode)
 216 {
 217         u64 word = (len - 1) & CONTROL_LEN;
 218
 219         word |= ((u64) opcode << CONTROL_OPCODE_SHIFT);
 220         word |= ((u64) enc_type << CONTROL_ENC_TYPE_SHIFT);
 221         word |= ((u64) auth_type << CONTROL_AUTH_TYPE_SHIFT);
 222         if (sfas)
 223                 word |= CONTROL_STORE_FINAL_AUTH_STATE;
 224         if (sob)
 225                 word |= CONTROL_START_OF_BLOCK;
 226         if (eob)
 227                 word |= CONTROL_END_OF_BLOCK;
 228         if (encrypt)
 229                 word |= CONTROL_ENCRYPT;
 230         if (hmac_key_len)
 231                 word |= ((u64) (hmac_key_len - 1)) << CONTROL_HMAC_KEY_LEN_SHIFT;
 232         if (hash_len)
 233                 word |= ((u64) (hash_len - 1)) << CONTROL_HASH_LEN_SHIFT;
 234
 235         return word;
 236 }
 237
 238 #if 0
 239 static inline bool n2_should_run_async(struct spu_queue *qp, int this_len)
 240 {
 241         if (this_len >= 64 ||
 242             qp->head != qp->tail)
 243                 return true;
 244         return false;
 245 }
 246 #endif
 247
 248 struct n2_ahash_alg {
 249         struct list_head        entry;
 250         const u8                *hash_zero;
 251         const u32               *hash_init;
 252         u8                      hw_op_hashsz;
 253         u8                      digest_size;
 254         u8                      auth_type;
 255         u8                      hmac_type;
 256         struct ahash_alg        alg;
 257 };
 258
 259 static inline struct n2_ahash_alg *n2_ahash_alg(struct crypto_tfm *tfm)
 260 {
 261         struct crypto_alg *alg = tfm->__crt_alg;
 262         struct ahash_alg *ahash_alg;
 263
 264         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 265
 266         return container_of(ahash_alg, struct n2_ahash_alg, alg);
 267 }
 268
 269 struct n2_hmac_alg {
 270         const char              *child_alg;
 271         struct n2_ahash_alg     derived;
 272 };
 273
 274 static inline struct n2_hmac_alg *n2_hmac_alg(struct crypto_tfm *tfm)
 275 {
 276         struct crypto_alg *alg = tfm->__crt_alg;
 277         struct ahash_alg *ahash_alg;
 278
 279         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 280
 281         return container_of(ahash_alg, struct n2_hmac_alg, derived.alg);
 282 }
 283
 284 struct n2_hash_ctx {
 285         struct crypto_ahash             *fallback_tfm;
 286 };
 287
 288 #define N2_HASH_KEY_MAX                 32 /* HW limit for all HMAC requests */
 289
 290 struct n2_hmac_ctx {
 291         struct n2_hash_ctx              base;
 292
 293         struct crypto_shash             *child_shash;
 294
 295         int                             hash_key_len;
 296         unsigned char                   hash_key[N2_HASH_KEY_MAX];
 297 };
 298
 299 struct n2_hash_req_ctx {
 300         union {
 301                 struct md5_state        md5;
 302                 struct sha1_state       sha1;
 303                 struct sha256_state     sha256;
 304         } u;
 305
 306         struct ahash_request            fallback_req;
 307 };
 308
 309 static int n2_hash_async_init(struct ahash_request *req)
 310 {
 311         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 312         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 313         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 314
 315         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 316         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 317
 318         return crypto_ahash_init(&rctx->fallback_req);
 319 }
 320
 321 static int n2_hash_async_update(struct ahash_request *req)
 322 {
 323         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 324         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 325         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 326
 327         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 328         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 329         rctx->fallback_req.nbytes = req->nbytes;
 330         rctx->fallback_req.src = req->src;
 331
 332         return crypto_ahash_update(&rctx->fallback_req);
 333 }
 334
 335 static int n2_hash_async_final(struct ahash_request *req)
 336 {
 337         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 338         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 339         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 340
 341         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 342         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 343         rctx->fallback_req.result = req->result;
 344
 345         return crypto_ahash_final(&rctx->fallback_req);
 346 }
 347
 348 static int n2_hash_async_finup(struct ahash_request *req)
 349 {
 350         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 351         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 352         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 353
 354         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 355         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 356         rctx->fallback_req.nbytes = req->nbytes;
 357         rctx->fallback_req.src = req->src;
 358         rctx->fallback_req.result = req->result;
 359
 360         return crypto_ahash_finup(&rctx->fallback_req);
 361 }
 362
 363 static int n2_hash_async_noimport(struct ahash_request *req, const void *in)
 364 {
 365         return -ENOSYS;
 366 }
 367
 368 static int n2_hash_async_noexport(struct ahash_request *req, void *out)
 369 {
 370         return -ENOSYS;
 371 }
 372
 373 static int n2_hash_cra_init(struct crypto_tfm *tfm)
 374 {
 375         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 376         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 377         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 378         struct crypto_ahash *fallback_tfm;
 379         int err;
 380
 381         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 382                                           CRYPTO_ALG_NEED_FALLBACK);
 383         if (IS_ERR(fallback_tfm)) {
 384                 pr_warning("Fallback driver '%s' could not be loaded!\n",
 385                            fallback_driver_name);
 386                 err = PTR_ERR(fallback_tfm);
 387                 goto out;
 388         }
 389
 390         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 391                                          crypto_ahash_reqsize(fallback_tfm)));
 392
 393         ctx->fallback_tfm = fallback_tfm;
 394         return 0;
 395
 396 out:
 397         return err;
 398 }
 399
 400 static void n2_hash_cra_exit(struct crypto_tfm *tfm)
 401 {
 402         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 403         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 404
 405         crypto_free_ahash(ctx->fallback_tfm);
 406 }
 407
 408 static int n2_hmac_cra_init(struct crypto_tfm *tfm)
 409 {
 410         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 411         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 412         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 413         struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
 414         struct crypto_ahash *fallback_tfm;
 415         struct crypto_shash *child_shash;
 416         int err;
 417
 418         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 419                                           CRYPTO_ALG_NEED_FALLBACK);
 420         if (IS_ERR(fallback_tfm)) {
 421                 pr_warning("Fallback driver '%s' could not be loaded!\n",
 422                            fallback_driver_name);
 423                 err = PTR_ERR(fallback_tfm);
 424                 goto out;
 425         }
 426
 427         child_shash = crypto_alloc_shash(n2alg->child_alg, 0, 0);
 428         if (IS_ERR(child_shash)) {
 429                 pr_warning("Child shash '%s' could not be loaded!\n",
 430                            n2alg->child_alg);
 431                 err = PTR_ERR(child_shash);
 432                 goto out_free_fallback;
 433         }
 434
 435         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 436                                          crypto_ahash_reqsize(fallback_tfm)));
 437
 438         ctx->child_shash = child_shash;
 439         ctx->base.fallback_tfm = fallback_tfm;
 440         return 0;
 441
 442 out_free_fallback:
 443         crypto_free_ahash(fallback_tfm);
 444
 445 out:
 446         return err;
 447 }
 448
 449 static void n2_hmac_cra_exit(struct crypto_tfm *tfm)
 450 {
 451         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 452         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 453
 454         crypto_free_ahash(ctx->base.fallback_tfm);
 455         crypto_free_shash(ctx->child_shash);
 456 }
 457
 458 static int n2_hmac_async_setkey(struct crypto_ahash *tfm, const u8 *key,
 459                                 unsigned int keylen)
 460 {
 461         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 462         struct crypto_shash *child_shash = ctx->child_shash;
 463         struct crypto_ahash *fallback_tfm;
 464         SHASH_DESC_ON_STACK(shash, child_shash);
 465         int err, bs, ds;
 466
 467         fallback_tfm = ctx->base.fallback_tfm;
 468         err = crypto_ahash_setkey(fallback_tfm, key, keylen);
 469         if (err)
 470                 return err;
 471
 472         shash->tfm = child_shash;
 473
 474         bs = crypto_shash_blocksize(child_shash);
 475         ds = crypto_shash_digestsize(child_shash);
 476         BUG_ON(ds > N2_HASH_KEY_MAX);
 477         if (keylen > bs) {
 478                 err = crypto_shash_digest(shash, key, keylen,
 479                                           ctx->hash_key);
 480                 if (err)
 481                         return err;
 482                 keylen = ds;
 483         } else if (keylen <= N2_HASH_KEY_MAX)
 484                 memcpy(ctx->hash_key, key, keylen);
 485
 486         ctx->hash_key_len = keylen;
 487
 488         return err;
 489 }
 490
 491 static unsigned long wait_for_tail(struct spu_queue *qp)
 492 {
 493         unsigned long head, hv_ret;
 494
 495         do {
 496                 hv_ret = sun4v_ncs_gethead(qp->qhandle, &head);
 497                 if (hv_ret != HV_EOK) {
 498                         pr_err("Hypervisor error on gethead\n");
 499                         break;
 500                 }
 501                 if (head == qp->tail) {
 502                         qp->head = head;
 503                         break;
 504                 }
 505         } while (1);
 506         return hv_ret;
 507 }
 508
 509 static unsigned long submit_and_wait_for_tail(struct spu_queue *qp,
 510                                               struct cwq_initial_entry *ent)
 511 {
 512         unsigned long hv_ret = spu_queue_submit(qp, ent);
 513
 514         if (hv_ret == HV_EOK)
 515                 hv_ret = wait_for_tail(qp);
 516
 517         return hv_ret;
 518 }
 519
 520 static int n2_do_async_digest(struct ahash_request *req,
 521                               unsigned int auth_type, unsigned int digest_size,
 522                               unsigned int result_size, void *hash_loc,
 523                               unsigned long auth_key, unsigned int auth_key_len)
 524 {
 525         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 526         struct cwq_initial_entry *ent;
 527         struct crypto_hash_walk walk;
 528         struct spu_queue *qp;
 529         unsigned long flags;
 530         int err = -ENODEV;
 531         int nbytes, cpu;
 532
 533         /* The total effective length of the operation may not
 534          * exceed 2^16.
 535          */
 536         if (unlikely(req->nbytes > (1 << 16))) {
 537                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 538                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 539
 540                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 541                 rctx->fallback_req.base.flags =
 542                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 543                 rctx->fallback_req.nbytes = req->nbytes;
 544                 rctx->fallback_req.src = req->src;
 545                 rctx->fallback_req.result = req->result;
 546
 547                 return crypto_ahash_digest(&rctx->fallback_req);
 548         }
 549
 550         nbytes = crypto_hash_walk_first(req, &walk);
 551
 552         cpu = get_cpu();
 553         qp = cpu_to_cwq[cpu];
 554         if (!qp)
 555                 goto out;
 556
 557         spin_lock_irqsave(&qp->lock, flags);
 558
 559         /* XXX can do better, improve this later by doing a by-hand scatterlist
 560          * XXX walk, etc.
 561          */
 562         ent = qp->q + qp->tail;
 563
 564         ent->control = control_word_base(nbytes, auth_key_len, 0,
 565                                          auth_type, digest_size,
 566                                          false, true, false, false,
 567                                          OPCODE_INPLACE_BIT |
 568                                          OPCODE_AUTH_MAC);
 569         ent->src_addr = __pa(walk.data);
 570         ent->auth_key_addr = auth_key;
 571         ent->auth_iv_addr = __pa(hash_loc);
 572         ent->final_auth_state_addr = 0UL;
 573         ent->enc_key_addr = 0UL;
 574         ent->enc_iv_addr = 0UL;
 575         ent->dest_addr = __pa(hash_loc);
 576
 577         nbytes = crypto_hash_walk_done(&walk, 0);
 578         while (nbytes > 0) {
 579                 ent = spu_queue_next(qp, ent);
 580
 581                 ent->control = (nbytes - 1);
 582                 ent->src_addr = __pa(walk.data);
 583                 ent->auth_key_addr = 0UL;
 584                 ent->auth_iv_addr = 0UL;
 585                 ent->final_auth_state_addr = 0UL;
 586                 ent->enc_key_addr = 0UL;
 587                 ent->enc_iv_addr = 0UL;
 588                 ent->dest_addr = 0UL;
 589
 590                 nbytes = crypto_hash_walk_done(&walk, 0);
 591         }
 592         ent->control |= CONTROL_END_OF_BLOCK;
 593
 594         if (submit_and_wait_for_tail(qp, ent) != HV_EOK)
 595                 err = -EINVAL;
 596         else
 597                 err = 0;
 598
 599         spin_unlock_irqrestore(&qp->lock, flags);
 600
 601         if (!err)
 602                 memcpy(req->result, hash_loc, result_size);
 603 out:
 604         put_cpu();
 605
 606         return err;
 607 }
 608
 609 static int n2_hash_async_digest(struct ahash_request *req)
 610 {
 611         struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm);
 612         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 613         int ds;
 614
 615         ds = n2alg->digest_size;
 616         if (unlikely(req->nbytes == 0)) {
 617                 memcpy(req->result, n2alg->hash_zero, ds);
 618                 return 0;
 619         }
 620         memcpy(&rctx->u, n2alg->hash_init, n2alg->hw_op_hashsz);
 621
 622         return n2_do_async_digest(req, n2alg->auth_type,
 623                                   n2alg->hw_op_hashsz, ds,
 624                                   &rctx->u, 0UL, 0);
 625 }
 626
 627 static int n2_hmac_async_digest(struct ahash_request *req)
 628 {
 629         struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm);
 630         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 631         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 632         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 633         int ds;
 634
 635         ds = n2alg->derived.digest_size;
 636         if (unlikely(req->nbytes == 0) ||
 637             unlikely(ctx->hash_key_len > N2_HASH_KEY_MAX)) {
 638                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 639                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 640
 641                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 642                 rctx->fallback_req.base.flags =
 643                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 644                 rctx->fallback_req.nbytes = req->nbytes;
 645                 rctx->fallback_req.src = req->src;
 646                 rctx->fallback_req.result = req->result;
 647
 648                 return crypto_ahash_digest(&rctx->fallback_req);
 649         }
 650         memcpy(&rctx->u, n2alg->derived.hash_init,
 651                n2alg->derived.hw_op_hashsz);
 652
 653         return n2_do_async_digest(req, n2alg->derived.hmac_type,
 654                                   n2alg->derived.hw_op_hashsz, ds,
 655                                   &rctx->u,
 656                                   __pa(&ctx->hash_key),
 657                                   ctx->hash_key_len);
 658 }
 659
 660 struct n2_cipher_context {
 661         int                     key_len;
 662         int                     enc_type;
 663         union {
 664                 u8              aes[AES_MAX_KEY_SIZE];
 665                 u8              des[DES_KEY_SIZE];
 666                 u8              des3[3 * DES_KEY_SIZE];
 667                 u8              arc4[258]; /* S-box, X, Y */
 668         } key;
 669 };
 670
 671 #define N2_CHUNK_ARR_LEN        16
 672
 673 struct n2_crypto_chunk {
 674         struct list_head        entry;
 675         unsigned long           iv_paddr : 44;
 676         unsigned long           arr_len : 20;
 677         unsigned long           dest_paddr;
 678         unsigned long           dest_final;
 679         struct {
 680                 unsigned long   src_paddr : 44;
 681                 unsigned long   src_len : 20;
 682         } arr[N2_CHUNK_ARR_LEN];
 683 };
 684
 685 struct n2_request_context {
 686         struct ablkcipher_walk  walk;
 687         struct list_head        chunk_list;
 688         struct n2_crypto_chunk  chunk;
 689         u8                      temp_iv[16];
 690 };
 691
 692 /* The SPU allows some level of flexibility for partial cipher blocks
 693  * being specified in a descriptor.
 694  *
 695  * It merely requires that every descriptor's length field is at least
 696  * as large as the cipher block size.  This means that a cipher block
 697  * can span at most 2 descriptors.  However, this does not allow a
 698  * partial block to span into the final descriptor as that would
 699  * violate the rule (since every descriptor's length must be at lest
 700  * the block size).  So, for example, assuming an 8 byte block size:
 701  *
 702  *      0xe --> 0xa --> 0x8
 703  *
 704  * is a valid length sequence, whereas:
 705  *
 706  *      0xe --> 0xb --> 0x7
 707  *
 708  * is not a valid sequence.
 709  */
 710
 711 struct n2_cipher_alg {
 712         struct list_head        entry;
 713         u8                      enc_type;
 714         struct crypto_alg       alg;
 715 };
 716
 717 static inline struct n2_cipher_alg *n2_cipher_alg(struct crypto_tfm *tfm)
 718 {
 719         struct crypto_alg *alg = tfm->__crt_alg;
 720
 721         return container_of(alg, struct n2_cipher_alg, alg);
 722 }
 723
 724 struct n2_cipher_request_context {
 725         struct ablkcipher_walk  walk;
 726 };
 727
 728 static int n2_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 729                          unsigned int keylen)
 730 {
 731         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 732         struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
 733         struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
 734
 735         ctx->enc_type = (n2alg->enc_type & ENC_TYPE_CHAINING_MASK);
 736
 737         switch (keylen) {
 738         case AES_KEYSIZE_128:
 739                 ctx->enc_type |= ENC_TYPE_ALG_AES128;
 740                 break;
 741         case AES_KEYSIZE_192:
 742                 ctx->enc_type |= ENC_TYPE_ALG_AES192;
 743                 break;
 744         case AES_KEYSIZE_256:
 745                 ctx->enc_type |= ENC_TYPE_ALG_AES256;
 746                 break;
 747         default:
 748                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 749                 return -EINVAL;
 750         }
 751
 752         ctx->key_len = keylen;
 753         memcpy(ctx->key.aes, key, keylen);
 754         return 0;
 755 }
 756
 757 static int n2_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 758                          unsigned int keylen)
 759 {
 760         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 761         struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
 762         struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
 763         u32 tmp[DES_EXPKEY_WORDS];
 764         int err;
 765
 766         ctx->enc_type = n2alg->enc_type;
 767
 768         if (keylen != DES_KEY_SIZE) {
 769                 crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
 770                 return -EINVAL;
 771         }
 772
 773         err = des_ekey(tmp, key);
 774         if (err == 0 && (tfm->crt_flags & CRYPTO_TFM_REQ_FORBID_WEAK_KEYS)) {
 775                 tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
 776                 return -EINVAL;
 777         }
 778
 779         ctx->key_len = keylen;
 780         memcpy(ctx->key.des, key, keylen);
 781         return 0;
 782 }
 783
 784 static int n2_3des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 785                           unsigned int keylen)
 786 {
 787         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 788         struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
 789         struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
 790         u32 flags;
 791         int err;
 792
 793         flags = crypto_ablkcipher_get_flags(cipher);
 794         err = __des3_verify_key(&flags, key);
 795         if (unlikely(err)) {
 796                 crypto_ablkcipher_set_flags(cipher, flags);
 797                 return err;
 798         }
 799
 800         ctx->enc_type = n2alg->enc_type;
 801
 802         ctx->key_len = keylen;
 803         memcpy(ctx->key.des3, key, keylen);
 804         return 0;
 805 }
 806
 807 static int n2_arc4_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
 808                           unsigned int keylen)
 809 {
 810         struct crypto_tfm *tfm = crypto_ablkcipher_tfm(cipher);
 811         struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
 812         struct n2_cipher_alg *n2alg = n2_cipher_alg(tfm);
 813         u8 *s = ctx->key.arc4;
 814         u8 *x = s + 256;
 815         u8 *y = x + 1;
 816         int i, j, k;
 817
 818         ctx->enc_type = n2alg->enc_type;
 819
 820         j = k = 0;
 821         *x = 0;
 822         *y = 0;
 823         for (i = 0; i < 256; i++)
 824                 s[i] = i;
 825         for (i = 0; i < 256; i++) {
 826                 u8 a = s[i];
 827                 j = (j + key[k] + a) & 0xff;
 828                 s[i] = s[j];
 829                 s[j] = a;
 830                 if (++k >= keylen)
 831                         k = 0;
 832         }
 833
 834         return 0;
 835 }
 836
 837 static inline int cipher_descriptor_len(int nbytes, unsigned int block_size)
 838 {
 839         int this_len = nbytes;
 840
 841         this_len -= (nbytes & (block_size - 1));
 842         return this_len > (1 << 16) ? (1 << 16) : this_len;
 843 }
 844
 845 static int __n2_crypt_chunk(struct crypto_tfm *tfm, struct n2_crypto_chunk *cp,
 846                             struct spu_queue *qp, bool encrypt)
 847 {
 848         struct n2_cipher_context *ctx = crypto_tfm_ctx(tfm);
 849         struct cwq_initial_entry *ent;
 850         bool in_place;
 851         int i;
 852
 853         ent = spu_queue_alloc(qp, cp->arr_len);
 854         if (!ent) {
 855                 pr_info("queue_alloc() of %d fails\n",
 856                         cp->arr_len);
 857                 return -EBUSY;
 858         }
 859
 860         in_place = (cp->dest_paddr == cp->arr[0].src_paddr);
 861
 862         ent->control = control_word_base(cp->arr[0].src_len,
 863                                          0, ctx->enc_type, 0, 0,
 864                                          false, true, false, encrypt,
 865                                          OPCODE_ENCRYPT |
 866                                          (in_place ? OPCODE_INPLACE_BIT : 0));
 867         ent->src_addr = cp->arr[0].src_paddr;
 868         ent->auth_key_addr = 0UL;
 869         ent->auth_iv_addr = 0UL;
 870         ent->final_auth_state_addr = 0UL;
 871         ent->enc_key_addr = __pa(&ctx->key);
 872         ent->enc_iv_addr = cp->iv_paddr;
 873         ent->dest_addr = (in_place ? 0UL : cp->dest_paddr);
 874
 875         for (i = 1; i < cp->arr_len; i++) {
 876                 ent = spu_queue_next(qp, ent);
 877
 878                 ent->control = cp->arr[i].src_len - 1;
 879                 ent->src_addr = cp->arr[i].src_paddr;
 880                 ent->auth_key_addr = 0UL;
 881                 ent->auth_iv_addr = 0UL;
 882                 ent->final_auth_state_addr = 0UL;
 883                 ent->enc_key_addr = 0UL;
 884                 ent->enc_iv_addr = 0UL;
 885                 ent->dest_addr = 0UL;
 886         }
 887         ent->control |= CONTROL_END_OF_BLOCK;
 888
 889         return (spu_queue_submit(qp, ent) != HV_EOK) ? -EINVAL : 0;
 890 }
 891
 892 static int n2_compute_chunks(struct ablkcipher_request *req)
 893 {
 894         struct n2_request_context *rctx = ablkcipher_request_ctx(req);
 895         struct ablkcipher_walk *walk = &rctx->walk;
 896         struct n2_crypto_chunk *chunk;
 897         unsigned long dest_prev;
 898         unsigned int tot_len;
 899         bool prev_in_place;
 900         int err, nbytes;
 901
 902         ablkcipher_walk_init(walk, req->dst, req->src, req->nbytes);
 903         err = ablkcipher_walk_phys(req, walk);
 904         if (err)
 905                 return err;
 906
 907         INIT_LIST_HEAD(&rctx->chunk_list);
 908
 909         chunk = &rctx->chunk;
 910         INIT_LIST_HEAD(&chunk->entry);
 911
 912         chunk->iv_paddr = 0UL;
 913         chunk->arr_len = 0;
 914         chunk->dest_paddr = 0UL;
 915
 916         prev_in_place = false;
 917         dest_prev = ~0UL;
 918         tot_len = 0;
 919
 920         while ((nbytes = walk->nbytes) != 0) {
 921                 unsigned long dest_paddr, src_paddr;
 922                 bool in_place;
 923                 int this_len;
 924
 925                 src_paddr = (page_to_phys(walk->src.page) +
 926                              walk->src.offset);
 927                 dest_paddr = (page_to_phys(walk->dst.page) +
 928                               walk->dst.offset);
 929                 in_place = (src_paddr == dest_paddr);
 930                 this_len = cipher_descriptor_len(nbytes, walk->blocksize);
 931
 932                 if (chunk->arr_len != 0) {
 933                         if (in_place != prev_in_place ||
 934                             (!prev_in_place &&
 935                              dest_paddr != dest_prev) ||
 936                             chunk->arr_len == N2_CHUNK_ARR_LEN ||
 937                             tot_len + this_len > (1 << 16)) {
 938                                 chunk->dest_final = dest_prev;
 939                                 list_add_tail(&chunk->entry,
 940                                               &rctx->chunk_list);
 941                                 chunk = kzalloc(sizeof(*chunk), GFP_ATOMIC);
 942                                 if (!chunk) {
 943                                         err = -ENOMEM;
 944                                         break;
 945                                 }
 946                                 INIT_LIST_HEAD(&chunk->entry);
 947                         }
 948                 }
 949                 if (chunk->arr_len == 0) {
 950                         chunk->dest_paddr = dest_paddr;
 951                         tot_len = 0;
 952                 }
 953                 chunk->arr[chunk->arr_len].src_paddr = src_paddr;
 954                 chunk->arr[chunk->arr_len].src_len = this_len;
 955                 chunk->arr_len++;
 956
 957                 dest_prev = dest_paddr + this_len;
 958                 prev_in_place = in_place;
 959                 tot_len += this_len;
 960
 961                 err = ablkcipher_walk_done(req, walk, nbytes - this_len);
 962                 if (err)
 963                         break;
 964         }
 965         if (!err && chunk->arr_len != 0) {
 966                 chunk->dest_final = dest_prev;
 967                 list_add_tail(&chunk->entry, &rctx->chunk_list);
 968         }
 969
 970         return err;
 971 }
 972
 973 static void n2_chunk_complete(struct ablkcipher_request *req, void *final_iv)
 974 {
 975         struct n2_request_context *rctx = ablkcipher_request_ctx(req);
 976         struct n2_crypto_chunk *c, *tmp;
 977
 978         if (final_iv)
 979                 memcpy(rctx->walk.iv, final_iv, rctx->walk.blocksize);
 980
 981         ablkcipher_walk_complete(&rctx->walk);
 982         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
 983                 list_del(&c->entry);
 984                 if (unlikely(c != &rctx->chunk))
 985                         kfree(c);
 986         }
 987
 988 }
 989
 990 static int n2_do_ecb(struct ablkcipher_request *req, bool encrypt)
 991 {
 992         struct n2_request_context *rctx = ablkcipher_request_ctx(req);
 993         struct crypto_tfm *tfm = req->base.tfm;
 994         int err = n2_compute_chunks(req);
 995         struct n2_crypto_chunk *c, *tmp;
 996         unsigned long flags, hv_ret;
 997         struct spu_queue *qp;
 998
 999         if (err)
1000                 return err;
1001
1002         qp = cpu_to_cwq[get_cpu()];
1003         err = -ENODEV;
1004         if (!qp)
1005                 goto out;
1006
1007         spin_lock_irqsave(&qp->lock, flags);
1008
1009         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
1010                 err = __n2_crypt_chunk(tfm, c, qp, encrypt);
1011                 if (err)
1012                         break;
1013                 list_del(&c->entry);
1014                 if (unlikely(c != &rctx->chunk))
1015                         kfree(c);
1016         }
1017         if (!err) {
1018                 hv_ret = wait_for_tail(qp);
1019                 if (hv_ret != HV_EOK)
1020                         err = -EINVAL;
1021         }
1022
1023         spin_unlock_irqrestore(&qp->lock, flags);
1024
1025 out:
1026         put_cpu();
1027
1028         n2_chunk_complete(req, NULL);
1029         return err;
1030 }
1031
1032 static int n2_encrypt_ecb(struct ablkcipher_request *req)
1033 {
1034         return n2_do_ecb(req, true);
1035 }
1036
1037 static int n2_decrypt_ecb(struct ablkcipher_request *req)
1038 {
1039         return n2_do_ecb(req, false);
1040 }
1041
1042 static int n2_do_chaining(struct ablkcipher_request *req, bool encrypt)
1043 {
1044         struct n2_request_context *rctx = ablkcipher_request_ctx(req);
1045         struct crypto_tfm *tfm = req->base.tfm;
1046         unsigned long flags, hv_ret, iv_paddr;
1047         int err = n2_compute_chunks(req);
1048         struct n2_crypto_chunk *c, *tmp;
1049         struct spu_queue *qp;
1050         void *final_iv_addr;
1051
1052         final_iv_addr = NULL;
1053
1054         if (err)
1055                 return err;
1056
1057         qp = cpu_to_cwq[get_cpu()];
1058         err = -ENODEV;
1059         if (!qp)
1060                 goto out;
1061
1062         spin_lock_irqsave(&qp->lock, flags);
1063
1064         if (encrypt) {
1065                 iv_paddr = __pa(rctx->walk.iv);
1066                 list_for_each_entry_safe(c, tmp, &rctx->chunk_list,
1067                                          entry) {
1068                         c->iv_paddr = iv_paddr;
1069                         err = __n2_crypt_chunk(tfm, c, qp, true);
1070                         if (err)
1071                                 break;
1072                         iv_paddr = c->dest_final - rctx->walk.blocksize;
1073                         list_del(&c->entry);
1074                         if (unlikely(c != &rctx->chunk))
1075                                 kfree(c);
1076                 }
1077                 final_iv_addr = __va(iv_paddr);
1078         } else {
1079                 list_for_each_entry_safe_reverse(c, tmp, &rctx->chunk_list,
1080                                                  entry) {
1081                         if (c == &rctx->chunk) {
1082                                 iv_paddr = __pa(rctx->walk.iv);
1083                         } else {
1084                                 iv_paddr = (tmp->arr[tmp->arr_len-1].src_paddr +
1085                                             tmp->arr[tmp->arr_len-1].src_len -
1086                                             rctx->walk.blocksize);
1087                         }
1088                         if (!final_iv_addr) {
1089                                 unsigned long pa;
1090
1091                                 pa = (c->arr[c->arr_len-1].src_paddr +
1092                                       c->arr[c->arr_len-1].src_len -
1093                                       rctx->walk.blocksize);
1094                                 final_iv_addr = rctx->temp_iv;
1095                                 memcpy(rctx->temp_iv, __va(pa),
1096                                        rctx->walk.blocksize);
1097                         }
1098                         c->iv_paddr = iv_paddr;
1099                         err = __n2_crypt_chunk(tfm, c, qp, false);
1100                         if (err)
1101                                 break;
1102                         list_del(&c->entry);
1103                         if (unlikely(c != &rctx->chunk))
1104                                 kfree(c);
1105                 }
1106         }
1107         if (!err) {
1108                 hv_ret = wait_for_tail(qp);
1109                 if (hv_ret != HV_EOK)
1110                         err = -EINVAL;
1111         }
1112
1113         spin_unlock_irqrestore(&qp->lock, flags);
1114
1115 out:
1116         put_cpu();
1117
1118         n2_chunk_complete(req, err ? NULL : final_iv_addr);
1119         return err;
1120 }
1121
1122 static int n2_encrypt_chaining(struct ablkcipher_request *req)
1123 {
1124         return n2_do_chaining(req, true);
1125 }
1126
1127 static int n2_decrypt_chaining(struct ablkcipher_request *req)
1128 {
1129         return n2_do_chaining(req, false);
1130 }
1131
1132 struct n2_cipher_tmpl {
1133         const char              *name;
1134         const char              *drv_name;
1135         u8                      block_size;
1136         u8                      enc_type;
1137         struct ablkcipher_alg   ablkcipher;
1138 };
1139
1140 static const struct n2_cipher_tmpl cipher_tmpls[] = {
1141         /* ARC4: only ECB is supported (chaining bits ignored) */
1142         {       .name           = "ecb(arc4)",
1143                 .drv_name       = "ecb-arc4",
1144                 .block_size     = 1,
1145                 .enc_type       = (ENC_TYPE_ALG_RC4_STREAM |
1146                                    ENC_TYPE_CHAINING_ECB),
1147                 .ablkcipher     = {
1148                         .min_keysize    = 1,
1149                         .max_keysize    = 256,
1150                         .setkey         = n2_arc4_setkey,
1151                         .encrypt        = n2_encrypt_ecb,
1152                         .decrypt        = n2_decrypt_ecb,
1153                 },
1154         },
1155
1156         /* DES: ECB CBC and CFB are supported */
1157         {       .name           = "ecb(des)",
1158                 .drv_name       = "ecb-des",
1159                 .block_size     = DES_BLOCK_SIZE,
1160                 .enc_type       = (ENC_TYPE_ALG_DES |
1161                                    ENC_TYPE_CHAINING_ECB),
1162                 .ablkcipher     = {
1163                         .min_keysize    = DES_KEY_SIZE,
1164                         .max_keysize    = DES_KEY_SIZE,
1165                         .setkey         = n2_des_setkey,
1166                         .encrypt        = n2_encrypt_ecb,
1167                         .decrypt        = n2_decrypt_ecb,
1168                 },
1169         },
1170         {       .name           = "cbc(des)",
1171                 .drv_name       = "cbc-des",
1172                 .block_size     = DES_BLOCK_SIZE,
1173                 .enc_type       = (ENC_TYPE_ALG_DES |
1174                                    ENC_TYPE_CHAINING_CBC),
1175                 .ablkcipher     = {
1176                         .ivsize         = DES_BLOCK_SIZE,
1177                         .min_keysize    = DES_KEY_SIZE,
1178                         .max_keysize    = DES_KEY_SIZE,
1179                         .setkey         = n2_des_setkey,
1180                         .encrypt        = n2_encrypt_chaining,
1181                         .decrypt        = n2_decrypt_chaining,
1182                 },
1183         },
1184         {       .name           = "cfb(des)",
1185                 .drv_name       = "cfb-des",
1186                 .block_size     = DES_BLOCK_SIZE,
1187                 .enc_type       = (ENC_TYPE_ALG_DES |
1188                                    ENC_TYPE_CHAINING_CFB),
1189                 .ablkcipher     = {
1190                         .min_keysize    = DES_KEY_SIZE,
1191                         .max_keysize    = DES_KEY_SIZE,
1192                         .setkey         = n2_des_setkey,
1193                         .encrypt        = n2_encrypt_chaining,
1194                         .decrypt        = n2_decrypt_chaining,
1195                 },
1196         },
1197
1198         /* 3DES: ECB CBC and CFB are supported */
1199         {       .name           = "ecb(des3_ede)",
1200                 .drv_name       = "ecb-3des",
1201                 .block_size     = DES_BLOCK_SIZE,
1202                 .enc_type       = (ENC_TYPE_ALG_3DES |
1203                                    ENC_TYPE_CHAINING_ECB),
1204                 .ablkcipher     = {
1205                         .min_keysize    = 3 * DES_KEY_SIZE,
1206                         .max_keysize    = 3 * DES_KEY_SIZE,
1207                         .setkey         = n2_3des_setkey,
1208                         .encrypt        = n2_encrypt_ecb,
1209                         .decrypt        = n2_decrypt_ecb,
1210                 },
1211         },
1212         {       .name           = "cbc(des3_ede)",
1213                 .drv_name       = "cbc-3des",
1214                 .block_size     = DES_BLOCK_SIZE,
1215                 .enc_type       = (ENC_TYPE_ALG_3DES |
1216                                    ENC_TYPE_CHAINING_CBC),
1217                 .ablkcipher     = {
1218                         .ivsize         = DES_BLOCK_SIZE,
1219                         .min_keysize    = 3 * DES_KEY_SIZE,
1220                         .max_keysize    = 3 * DES_KEY_SIZE,
1221                         .setkey         = n2_3des_setkey,
1222                         .encrypt        = n2_encrypt_chaining,
1223                         .decrypt        = n2_decrypt_chaining,
1224                 },
1225         },
1226         {       .name           = "cfb(des3_ede)",
1227                 .drv_name       = "cfb-3des",
1228                 .block_size     = DES_BLOCK_SIZE,
1229                 .enc_type       = (ENC_TYPE_ALG_3DES |
1230                                    ENC_TYPE_CHAINING_CFB),
1231                 .ablkcipher     = {
1232                         .min_keysize    = 3 * DES_KEY_SIZE,
1233                         .max_keysize    = 3 * DES_KEY_SIZE,
1234                         .setkey         = n2_3des_setkey,
1235                         .encrypt        = n2_encrypt_chaining,
1236                         .decrypt        = n2_decrypt_chaining,
1237                 },
1238         },
1239         /* AES: ECB CBC and CTR are supported */
1240         {       .name           = "ecb(aes)",
1241                 .drv_name       = "ecb-aes",
1242                 .block_size     = AES_BLOCK_SIZE,
1243                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1244                                    ENC_TYPE_CHAINING_ECB),
1245                 .ablkcipher     = {
1246                         .min_keysize    = AES_MIN_KEY_SIZE,
1247                         .max_keysize    = AES_MAX_KEY_SIZE,
1248                         .setkey         = n2_aes_setkey,
1249                         .encrypt        = n2_encrypt_ecb,
1250                         .decrypt        = n2_decrypt_ecb,
1251                 },
1252         },
1253         {       .name           = "cbc(aes)",
1254                 .drv_name       = "cbc-aes",
1255                 .block_size     = AES_BLOCK_SIZE,
1256                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1257                                    ENC_TYPE_CHAINING_CBC),
1258                 .ablkcipher     = {
1259                         .ivsize         = AES_BLOCK_SIZE,
1260                         .min_keysize    = AES_MIN_KEY_SIZE,
1261                         .max_keysize    = AES_MAX_KEY_SIZE,
1262                         .setkey         = n2_aes_setkey,
1263                         .encrypt        = n2_encrypt_chaining,
1264                         .decrypt        = n2_decrypt_chaining,
1265                 },
1266         },
1267         {       .name           = "ctr(aes)",
1268                 .drv_name       = "ctr-aes",
1269                 .block_size     = AES_BLOCK_SIZE,
1270                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1271                                    ENC_TYPE_CHAINING_COUNTER),
1272                 .ablkcipher     = {
1273                         .ivsize         = AES_BLOCK_SIZE,
1274                         .min_keysize    = AES_MIN_KEY_SIZE,
1275                         .max_keysize    = AES_MAX_KEY_SIZE,
1276                         .setkey         = n2_aes_setkey,
1277                         .encrypt        = n2_encrypt_chaining,
1278                         .decrypt        = n2_encrypt_chaining,
1279                 },
1280         },
1281
1282 };
1283 #define NUM_CIPHER_TMPLS ARRAY_SIZE(cipher_tmpls)
1284
1285 static LIST_HEAD(cipher_algs);
1286
1287 struct n2_hash_tmpl {
1288         const char      *name;
1289         const u8        *hash_zero;
1290         const u32       *hash_init;
1291         u8              hw_op_hashsz;
1292         u8              digest_size;
1293         u8              block_size;
1294         u8              auth_type;
1295         u8              hmac_type;
1296 };
1297
1298 static const u32 md5_init[MD5_HASH_WORDS] = {
1299         cpu_to_le32(MD5_H0),
1300         cpu_to_le32(MD5_H1),
1301         cpu_to_le32(MD5_H2),
1302         cpu_to_le32(MD5_H3),
1303 };
1304 static const u32 sha1_init[SHA1_DIGEST_SIZE / 4] = {
1305         SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
1306 };
1307 static const u32 sha256_init[SHA256_DIGEST_SIZE / 4] = {
1308         SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
1309         SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7,
1310 };
1311 static const u32 sha224_init[SHA256_DIGEST_SIZE / 4] = {
1312         SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
1313         SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7,
1314 };
1315
1316 static const struct n2_hash_tmpl hash_tmpls[] = {
1317         { .name         = "md5",
1318           .hash_zero    = md5_zero_message_hash,
1319           .hash_init    = md5_init,
1320           .auth_type    = AUTH_TYPE_MD5,
1321           .hmac_type    = AUTH_TYPE_HMAC_MD5,
1322           .hw_op_hashsz = MD5_DIGEST_SIZE,
1323           .digest_size  = MD5_DIGEST_SIZE,
1324           .block_size   = MD5_HMAC_BLOCK_SIZE },
1325         { .name         = "sha1",
1326           .hash_zero    = sha1_zero_message_hash,
1327           .hash_init    = sha1_init,
1328           .auth_type    = AUTH_TYPE_SHA1,
1329           .hmac_type    = AUTH_TYPE_HMAC_SHA1,
1330           .hw_op_hashsz = SHA1_DIGEST_SIZE,
1331           .digest_size  = SHA1_DIGEST_SIZE,
1332           .block_size   = SHA1_BLOCK_SIZE },
1333         { .name         = "sha256",
1334           .hash_zero    = sha256_zero_message_hash,
1335           .hash_init    = sha256_init,
1336           .auth_type    = AUTH_TYPE_SHA256,
1337           .hmac_type    = AUTH_TYPE_HMAC_SHA256,
1338           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1339           .digest_size  = SHA256_DIGEST_SIZE,
1340           .block_size   = SHA256_BLOCK_SIZE },
1341         { .name         = "sha224",
1342           .hash_zero    = sha224_zero_message_hash,
1343           .hash_init    = sha224_init,
1344           .auth_type    = AUTH_TYPE_SHA256,
1345           .hmac_type    = AUTH_TYPE_RESERVED,
1346           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1347           .digest_size  = SHA224_DIGEST_SIZE,
1348           .block_size   = SHA224_BLOCK_SIZE },
1349 };
1350 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
1351
1352 static LIST_HEAD(ahash_algs);
1353 static LIST_HEAD(hmac_algs);
1354
1355 static int algs_registered;
1356
1357 static void __n2_unregister_algs(void)
1358 {
1359         struct n2_cipher_alg *cipher, *cipher_tmp;
1360         struct n2_ahash_alg *alg, *alg_tmp;
1361         struct n2_hmac_alg *hmac, *hmac_tmp;
1362
1363         list_for_each_entry_safe(cipher, cipher_tmp, &cipher_algs, entry) {
1364                 crypto_unregister_alg(&cipher->alg);
1365                 list_del(&cipher->entry);
1366                 kfree(cipher);
1367         }
1368         list_for_each_entry_safe(hmac, hmac_tmp, &hmac_algs, derived.entry) {
1369                 crypto_unregister_ahash(&hmac->derived.alg);
1370                 list_del(&hmac->derived.entry);
1371                 kfree(hmac);
1372         }
1373         list_for_each_entry_safe(alg, alg_tmp, &ahash_algs, entry) {
1374                 crypto_unregister_ahash(&alg->alg);
1375                 list_del(&alg->entry);
1376                 kfree(alg);
1377         }
1378 }
1379
1380 static int n2_cipher_cra_init(struct crypto_tfm *tfm)
1381 {
1382         tfm->crt_ablkcipher.reqsize = sizeof(struct n2_request_context);
1383         return 0;
1384 }
1385
1386 static int __n2_register_one_cipher(const struct n2_cipher_tmpl *tmpl)
1387 {
1388         struct n2_cipher_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1389         struct crypto_alg *alg;
1390         int err;
1391
1392         if (!p)
1393                 return -ENOMEM;
1394
1395         alg = &p->alg;
1396
1397         snprintf(alg->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1398         snprintf(alg->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name);
1399         alg->cra_priority = N2_CRA_PRIORITY;
1400         alg->cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
1401                          CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
1402         alg->cra_blocksize = tmpl->block_size;
1403         p->enc_type = tmpl->enc_type;
1404         alg->cra_ctxsize = sizeof(struct n2_cipher_context);
1405         alg->cra_type = &crypto_ablkcipher_type;
1406         alg->cra_u.ablkcipher = tmpl->ablkcipher;
1407         alg->cra_init = n2_cipher_cra_init;
1408         alg->cra_module = THIS_MODULE;
1409
1410         list_add(&p->entry, &cipher_algs);
1411         err = crypto_register_alg(alg);
1412         if (err) {
1413                 pr_err("%s alg registration failed\n", alg->cra_name);
1414                 list_del(&p->entry);
1415                 kfree(p);
1416         } else {
1417                 pr_info("%s alg registered\n", alg->cra_name);
1418         }
1419         return err;
1420 }
1421
1422 static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)
1423 {
1424         struct n2_hmac_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1425         struct ahash_alg *ahash;
1426         struct crypto_alg *base;
1427         int err;
1428
1429         if (!p)
1430                 return -ENOMEM;
1431
1432         p->child_alg = n2ahash->alg.halg.base.cra_name;
1433         memcpy(&p->derived, n2ahash, sizeof(struct n2_ahash_alg));
1434         INIT_LIST_HEAD(&p->derived.entry);
1435
1436         ahash = &p->derived.alg;
1437         ahash->digest = n2_hmac_async_digest;
1438         ahash->setkey = n2_hmac_async_setkey;
1439
1440         base = &ahash->halg.base;
1441         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)", p->child_alg);
1442         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2", p->child_alg);
1443
1444         base->cra_ctxsize = sizeof(struct n2_hmac_ctx);
1445         base->cra_init = n2_hmac_cra_init;
1446         base->cra_exit = n2_hmac_cra_exit;
1447
1448         list_add(&p->derived.entry, &hmac_algs);
1449         err = crypto_register_ahash(ahash);
1450         if (err) {
1451                 pr_err("%s alg registration failed\n", base->cra_name);
1452                 list_del(&p->derived.entry);
1453                 kfree(p);
1454         } else {
1455                 pr_info("%s alg registered\n", base->cra_name);
1456         }
1457         return err;
1458 }
1459
1460 static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
1461 {
1462         struct n2_ahash_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1463         struct hash_alg_common *halg;
1464         struct crypto_alg *base;
1465         struct ahash_alg *ahash;
1466         int err;
1467
1468         if (!p)
1469                 return -ENOMEM;
1470
1471         p->hash_zero = tmpl->hash_zero;
1472         p->hash_init = tmpl->hash_init;
1473         p->auth_type = tmpl->auth_type;
1474         p->hmac_type = tmpl->hmac_type;
1475         p->hw_op_hashsz = tmpl->hw_op_hashsz;
1476         p->digest_size = tmpl->digest_size;
1477
1478         ahash = &p->alg;
1479         ahash->init = n2_hash_async_init;
1480         ahash->update = n2_hash_async_update;
1481         ahash->final = n2_hash_async_final;
1482         ahash->finup = n2_hash_async_finup;
1483         ahash->digest = n2_hash_async_digest;
1484         ahash->export = n2_hash_async_noexport;
1485         ahash->import = n2_hash_async_noimport;
1486
1487         halg = &ahash->halg;
1488         halg->digestsize = tmpl->digest_size;
1489
1490         base = &halg->base;
1491         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1492         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name);
1493         base->cra_priority = N2_CRA_PRIORITY;
1494         base->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1495                           CRYPTO_ALG_NEED_FALLBACK;
1496         base->cra_blocksize = tmpl->block_size;
1497         base->cra_ctxsize = sizeof(struct n2_hash_ctx);
1498         base->cra_module = THIS_MODULE;
1499         base->cra_init = n2_hash_cra_init;
1500         base->cra_exit = n2_hash_cra_exit;
1501
1502         list_add(&p->entry, &ahash_algs);
1503         err = crypto_register_ahash(ahash);
1504         if (err) {
1505                 pr_err("%s alg registration failed\n", base->cra_name);
1506                 list_del(&p->entry);
1507                 kfree(p);
1508         } else {
1509                 pr_info("%s alg registered\n", base->cra_name);
1510         }
1511         if (!err && p->hmac_type != AUTH_TYPE_RESERVED)
1512                 err = __n2_register_one_hmac(p);
1513         return err;
1514 }
1515
1516 static int n2_register_algs(void)
1517 {
1518         int i, err = 0;
1519
1520         mutex_lock(&spu_lock);
1521         if (algs_registered++)
1522                 goto out;
1523
1524         for (i = 0; i < NUM_HASH_TMPLS; i++) {
1525                 err = __n2_register_one_ahash(&hash_tmpls[i]);
1526                 if (err) {
1527                         __n2_unregister_algs();
1528                         goto out;
1529                 }
1530         }
1531         for (i = 0; i < NUM_CIPHER_TMPLS; i++) {
1532                 err = __n2_register_one_cipher(&cipher_tmpls[i]);
1533                 if (err) {
1534                         __n2_unregister_algs();
1535                         goto out;
1536                 }
1537         }
1538
1539 out:
1540         mutex_unlock(&spu_lock);
1541         return err;
1542 }
1543
1544 static void n2_unregister_algs(void)
1545 {
1546         mutex_lock(&spu_lock);
1547         if (!--algs_registered)
1548                 __n2_unregister_algs();
1549         mutex_unlock(&spu_lock);
1550 }
1551
1552 /* To map CWQ queues to interrupt sources, the hypervisor API provides
1553  * a devino.  This isn't very useful to us because all of the
1554  * interrupts listed in the device_node have been translated to
1555  * Linux virtual IRQ cookie numbers.
1556  *
1557  * So we have to back-translate, going through the 'intr' and 'ino'
1558  * property tables of the n2cp MDESC node, matching it with the OF
1559  * 'interrupts' property entries, in order to to figure out which
1560  * devino goes to which already-translated IRQ.
1561  */
1562 static int find_devino_index(struct platform_device *dev, struct spu_mdesc_info *ip,
1563                              unsigned long dev_ino)
1564 {
1565         const unsigned int *dev_intrs;
1566         unsigned int intr;
1567         int i;
1568
1569         for (i = 0; i < ip->num_intrs; i++) {
1570                 if (ip->ino_table[i].ino == dev_ino)
1571                         break;
1572         }
1573         if (i == ip->num_intrs)
1574                 return -ENODEV;
1575
1576         intr = ip->ino_table[i].intr;
1577
1578         dev_intrs = of_get_property(dev->dev.of_node, "interrupts", NULL);
1579         if (!dev_intrs)
1580                 return -ENODEV;
1581
1582         for (i = 0; i < dev->archdata.num_irqs; i++) {
1583                 if (dev_intrs[i] == intr)
1584                         return i;
1585         }
1586
1587         return -ENODEV;
1588 }
1589
1590 static int spu_map_ino(struct platform_device *dev, struct spu_mdesc_info *ip,
1591                        const char *irq_name, struct spu_queue *p,
1592                        irq_handler_t handler)
1593 {
1594         unsigned long herr;
1595         int index;
1596
1597         herr = sun4v_ncs_qhandle_to_devino(p->qhandle, &p->devino);
1598         if (herr)
1599                 return -EINVAL;
1600
1601         index = find_devino_index(dev, ip, p->devino);
1602         if (index < 0)
1603                 return index;
1604
1605         p->irq = dev->archdata.irqs[index];
1606
1607         sprintf(p->irq_name, "%s-%d", irq_name, index);
1608
1609         return request_irq(p->irq, handler, 0, p->irq_name, p);
1610 }
1611
1612 static struct kmem_cache *queue_cache[2];
1613
1614 static void *new_queue(unsigned long q_type)
1615 {
1616         return kmem_cache_zalloc(queue_cache[q_type - 1], GFP_KERNEL);
1617 }
1618
1619 static void free_queue(void *p, unsigned long q_type)
1620 {
1621         kmem_cache_free(queue_cache[q_type - 1], p);
1622 }
1623
1624 static int queue_cache_init(void)
1625 {
1626         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1627                 queue_cache[HV_NCS_QTYPE_MAU - 1] =
1628                         kmem_cache_create("mau_queue",
1629                                           (MAU_NUM_ENTRIES *
1630                                            MAU_ENTRY_SIZE),
1631                                           MAU_ENTRY_SIZE, 0, NULL);
1632         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1633                 return -ENOMEM;
1634
1635         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1])
1636                 queue_cache[HV_NCS_QTYPE_CWQ - 1] =
1637                         kmem_cache_create("cwq_queue",
1638                                           (CWQ_NUM_ENTRIES *
1639                                            CWQ_ENTRY_SIZE),
1640                                           CWQ_ENTRY_SIZE, 0, NULL);
1641         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1]) {
1642                 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1643                 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1644                 return -ENOMEM;
1645         }
1646         return 0;
1647 }
1648
1649 static void queue_cache_destroy(void)
1650 {
1651         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1652         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_CWQ - 1]);
1653         queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1654         queue_cache[HV_NCS_QTYPE_CWQ - 1] = NULL;
1655 }
1656
1657 static long spu_queue_register_workfn(void *arg)
1658 {
1659         struct spu_qreg *qr = arg;
1660         struct spu_queue *p = qr->queue;
1661         unsigned long q_type = qr->type;
1662         unsigned long hv_ret;
1663
1664         hv_ret = sun4v_ncs_qconf(q_type, __pa(p->q),
1665                                  CWQ_NUM_ENTRIES, &p->qhandle);
1666         if (!hv_ret)
1667                 sun4v_ncs_sethead_marker(p->qhandle, 0);
1668
1669         return hv_ret ? -EINVAL : 0;
1670 }
1671
1672 static int spu_queue_register(struct spu_queue *p, unsigned long q_type)
1673 {
1674         int cpu = cpumask_any_and(&p->sharing, cpu_online_mask);
1675         struct spu_qreg qr = { .queue = p, .type = q_type };
1676
1677         return work_on_cpu_safe(cpu, spu_queue_register_workfn, &qr);
1678 }
1679
1680 static int spu_queue_setup(struct spu_queue *p)
1681 {
1682         int err;
1683
1684         p->q = new_queue(p->q_type);
1685         if (!p->q)
1686                 return -ENOMEM;
1687
1688         err = spu_queue_register(p, p->q_type);
1689         if (err) {
1690                 free_queue(p->q, p->q_type);
1691                 p->q = NULL;
1692         }
1693
1694         return err;
1695 }
1696
1697 static void spu_queue_destroy(struct spu_queue *p)
1698 {
1699         unsigned long hv_ret;
1700
1701         if (!p->q)
1702                 return;
1703
1704         hv_ret = sun4v_ncs_qconf(p->q_type, p->qhandle, 0, &p->qhandle);
1705
1706         if (!hv_ret)
1707                 free_queue(p->q, p->q_type);
1708 }
1709
1710 static void spu_list_destroy(struct list_head *list)
1711 {
1712         struct spu_queue *p, *n;
1713
1714         list_for_each_entry_safe(p, n, list, list) {
1715                 int i;
1716
1717                 for (i = 0; i < NR_CPUS; i++) {
1718                         if (cpu_to_cwq[i] == p)
1719                                 cpu_to_cwq[i] = NULL;
1720                 }
1721
1722                 if (p->irq) {
1723                         free_irq(p->irq, p);
1724                         p->irq = 0;
1725                 }
1726                 spu_queue_destroy(p);
1727                 list_del(&p->list);
1728                 kfree(p);
1729         }
1730 }
1731
1732 /* Walk the backward arcs of a CWQ 'exec-unit' node,
1733  * gathering cpu membership information.
1734  */
1735 static int spu_mdesc_walk_arcs(struct mdesc_handle *mdesc,
1736                                struct platform_device *dev,
1737                                u64 node, struct spu_queue *p,
1738                                struct spu_queue **table)
1739 {
1740         u64 arc;
1741
1742         mdesc_for_each_arc(arc, mdesc, node, MDESC_ARC_TYPE_BACK) {
1743                 u64 tgt = mdesc_arc_target(mdesc, arc);
1744                 const char *name = mdesc_node_name(mdesc, tgt);
1745                 const u64 *id;
1746
1747                 if (strcmp(name, "cpu"))
1748                         continue;
1749                 id = mdesc_get_property(mdesc, tgt, "id", NULL);
1750                 if (table[*id] != NULL) {
1751                         dev_err(&dev->dev, "%pOF: SPU cpu slot already set.\n",
1752                                 dev->dev.of_node);
1753                         return -EINVAL;
1754                 }
1755                 cpumask_set_cpu(*id, &p->sharing);
1756                 table[*id] = p;
1757         }
1758         return 0;
1759 }
1760
1761 /* Process an 'exec-unit' MDESC node of type 'cwq'.  */
1762 static int handle_exec_unit(struct spu_mdesc_info *ip, struct list_head *list,
1763                             struct platform_device *dev, struct mdesc_handle *mdesc,
1764                             u64 node, const char *iname, unsigned long q_type,
1765                             irq_handler_t handler, struct spu_queue **table)
1766 {
1767         struct spu_queue *p;
1768         int err;
1769
1770         p = kzalloc(sizeof(struct spu_queue), GFP_KERNEL);
1771         if (!p) {
1772                 dev_err(&dev->dev, "%pOF: Could not allocate SPU queue.\n",
1773                         dev->dev.of_node);
1774                 return -ENOMEM;
1775         }
1776
1777         cpumask_clear(&p->sharing);
1778         spin_lock_init(&p->lock);
1779         p->q_type = q_type;
1780         INIT_LIST_HEAD(&p->jobs);
1781         list_add(&p->list, list);
1782
1783         err = spu_mdesc_walk_arcs(mdesc, dev, node, p, table);
1784         if (err)
1785                 return err;
1786
1787         err = spu_queue_setup(p);
1788         if (err)
1789                 return err;
1790
1791         return spu_map_ino(dev, ip, iname, p, handler);
1792 }
1793
1794 static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *dev,
1795                           struct spu_mdesc_info *ip, struct list_head *list,
1796                           const char *exec_name, unsigned long q_type,
1797                           irq_handler_t handler, struct spu_queue **table)
1798 {
1799         int err = 0;
1800         u64 node;
1801
1802         mdesc_for_each_node_by_name(mdesc, node, "exec-unit") {
1803                 const char *type;
1804
1805                 type = mdesc_get_property(mdesc, node, "type", NULL);
1806                 if (!type || strcmp(type, exec_name))
1807                         continue;
1808
1809                 err = handle_exec_unit(ip, list, dev, mdesc, node,
1810                                        exec_name, q_type, handler, table);
1811                 if (err) {
1812                         spu_list_destroy(list);
1813                         break;
1814                 }
1815         }
1816
1817         return err;
1818 }
1819
1820 static int get_irq_props(struct mdesc_handle *mdesc, u64 node,
1821                          struct spu_mdesc_info *ip)
1822 {
1823         const u64 *ino;
1824         int ino_len;
1825         int i;
1826
1827         ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
1828         if (!ino) {
1829                 printk("NO 'ino'\n");
1830                 return -ENODEV;
1831         }
1832
1833         ip->num_intrs = ino_len / sizeof(u64);
1834         ip->ino_table = kzalloc((sizeof(struct ino_blob) *
1835                                  ip->num_intrs),
1836                                 GFP_KERNEL);
1837         if (!ip->ino_table)
1838                 return -ENOMEM;
1839
1840         for (i = 0; i < ip->num_intrs; i++) {
1841                 struct ino_blob *b = &ip->ino_table[i];
1842                 b->intr = i + 1;
1843                 b->ino = ino[i];
1844         }
1845
1846         return 0;
1847 }
1848
1849 static int grab_mdesc_irq_props(struct mdesc_handle *mdesc,
1850                                 struct platform_device *dev,
1851                                 struct spu_mdesc_info *ip,
1852                                 const char *node_name)
1853 {
1854         const unsigned int *reg;
1855         u64 node;
1856
1857         reg = of_get_property(dev->dev.of_node, "reg", NULL);
1858         if (!reg)
1859                 return -ENODEV;
1860
1861         mdesc_for_each_node_by_name(mdesc, node, "virtual-device") {
1862                 const char *name;
1863                 const u64 *chdl;
1864
1865                 name = mdesc_get_property(mdesc, node, "name", NULL);
1866                 if (!name || strcmp(name, node_name))
1867                         continue;
1868                 chdl = mdesc_get_property(mdesc, node, "cfg-handle", NULL);
1869                 if (!chdl || (*chdl != *reg))
1870                         continue;
1871                 ip->cfg_handle = *chdl;
1872                 return get_irq_props(mdesc, node, ip);
1873         }
1874
1875         return -ENODEV;
1876 }
1877
1878 static unsigned long n2_spu_hvapi_major;
1879 static unsigned long n2_spu_hvapi_minor;
1880
1881 static int n2_spu_hvapi_register(void)
1882 {
1883         int err;
1884
1885         n2_spu_hvapi_major = 2;
1886         n2_spu_hvapi_minor = 0;
1887
1888         err = sun4v_hvapi_register(HV_GRP_NCS,
1889                                    n2_spu_hvapi_major,
1890                                    &n2_spu_hvapi_minor);
1891
1892         if (!err)
1893                 pr_info("Registered NCS HVAPI version %lu.%lu\n",
1894                         n2_spu_hvapi_major,
1895                         n2_spu_hvapi_minor);
1896
1897         return err;
1898 }
1899
1900 static void n2_spu_hvapi_unregister(void)
1901 {
1902         sun4v_hvapi_unregister(HV_GRP_NCS);
1903 }
1904
1905 static int global_ref;
1906
1907 static int grab_global_resources(void)
1908 {
1909         int err = 0;
1910
1911         mutex_lock(&spu_lock);
1912
1913         if (global_ref++)
1914                 goto out;
1915
1916         err = n2_spu_hvapi_register();
1917         if (err)
1918                 goto out;
1919
1920         err = queue_cache_init();
1921         if (err)
1922                 goto out_hvapi_release;
1923
1924         err = -ENOMEM;
1925         cpu_to_cwq = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1926                              GFP_KERNEL);
1927         if (!cpu_to_cwq)
1928                 goto out_queue_cache_destroy;
1929
1930         cpu_to_mau = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1931                              GFP_KERNEL);
1932         if (!cpu_to_mau)
1933                 goto out_free_cwq_table;
1934
1935         err = 0;
1936
1937 out:
1938         if (err)
1939                 global_ref--;
1940         mutex_unlock(&spu_lock);
1941         return err;
1942
1943 out_free_cwq_table:
1944         kfree(cpu_to_cwq);
1945         cpu_to_cwq = NULL;
1946
1947 out_queue_cache_destroy:
1948         queue_cache_destroy();
1949
1950 out_hvapi_release:
1951         n2_spu_hvapi_unregister();
1952         goto out;
1953 }
1954
1955 static void release_global_resources(void)
1956 {
1957         mutex_lock(&spu_lock);
1958         if (!--global_ref) {
1959                 kfree(cpu_to_cwq);
1960                 cpu_to_cwq = NULL;
1961
1962                 kfree(cpu_to_mau);
1963                 cpu_to_mau = NULL;
1964
1965                 queue_cache_destroy();
1966                 n2_spu_hvapi_unregister();
1967         }
1968         mutex_unlock(&spu_lock);
1969 }
1970
1971 static struct n2_crypto *alloc_n2cp(void)
1972 {
1973         struct n2_crypto *np = kzalloc(sizeof(struct n2_crypto), GFP_KERNEL);
1974
1975         if (np)
1976                 INIT_LIST_HEAD(&np->cwq_list);
1977
1978         return np;
1979 }
1980
1981 static void free_n2cp(struct n2_crypto *np)
1982 {
1983         kfree(np->cwq_info.ino_table);
1984         np->cwq_info.ino_table = NULL;
1985
1986         kfree(np);
1987 }
1988
1989 static void n2_spu_driver_version(void)
1990 {
1991         static int n2_spu_version_printed;
1992
1993         if (n2_spu_version_printed++ == 0)
1994                 pr_info("%s", version);
1995 }
1996
1997 static int n2_crypto_probe(struct platform_device *dev)
1998 {
1999         struct mdesc_handle *mdesc;
2000         struct n2_crypto *np;
2001         int err;
2002
2003         n2_spu_driver_version();
2004
2005         pr_info("Found N2CP at %pOF\n", dev->dev.of_node);
2006
2007         np = alloc_n2cp();
2008         if (!np) {
2009                 dev_err(&dev->dev, "%pOF: Unable to allocate n2cp.\n",
2010                         dev->dev.of_node);
2011                 return -ENOMEM;
2012         }
2013
2014         err = grab_global_resources();
2015         if (err) {
2016                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2017                         dev->dev.of_node);
2018                 goto out_free_n2cp;
2019         }
2020
2021         mdesc = mdesc_grab();
2022
2023         if (!mdesc) {
2024                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2025                         dev->dev.of_node);
2026                 err = -ENODEV;
2027                 goto out_free_global;
2028         }
2029         err = grab_mdesc_irq_props(mdesc, dev, &np->cwq_info, "n2cp");
2030         if (err) {
2031                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2032                         dev->dev.of_node);
2033                 mdesc_release(mdesc);
2034                 goto out_free_global;
2035         }
2036
2037         err = spu_mdesc_scan(mdesc, dev, &np->cwq_info, &np->cwq_list,
2038                              "cwq", HV_NCS_QTYPE_CWQ, cwq_intr,
2039                              cpu_to_cwq);
2040         mdesc_release(mdesc);
2041
2042         if (err) {
2043                 dev_err(&dev->dev, "%pOF: CWQ MDESC scan failed.\n",
2044                         dev->dev.of_node);
2045                 goto out_free_global;
2046         }
2047
2048         err = n2_register_algs();
2049         if (err) {
2050                 dev_err(&dev->dev, "%pOF: Unable to register algorithms.\n",
2051                         dev->dev.of_node);
2052                 goto out_free_spu_list;
2053         }
2054
2055         dev_set_drvdata(&dev->dev, np);
2056
2057         return 0;
2058
2059 out_free_spu_list:
2060         spu_list_destroy(&np->cwq_list);
2061
2062 out_free_global:
2063         release_global_resources();
2064
2065 out_free_n2cp:
2066         free_n2cp(np);
2067
2068         return err;
2069 }
2070
2071 static int n2_crypto_remove(struct platform_device *dev)
2072 {
2073         struct n2_crypto *np = dev_get_drvdata(&dev->dev);
2074
2075         n2_unregister_algs();
2076
2077         spu_list_destroy(&np->cwq_list);
2078
2079         release_global_resources();
2080
2081         free_n2cp(np);
2082
2083         return 0;
2084 }
2085
2086 static struct n2_mau *alloc_ncp(void)
2087 {
2088         struct n2_mau *mp = kzalloc(sizeof(struct n2_mau), GFP_KERNEL);
2089
2090         if (mp)
2091                 INIT_LIST_HEAD(&mp->mau_list);
2092
2093         return mp;
2094 }
2095
2096 static void free_ncp(struct n2_mau *mp)
2097 {
2098         kfree(mp->mau_info.ino_table);
2099         mp->mau_info.ino_table = NULL;
2100
2101         kfree(mp);
2102 }
2103
2104 static int n2_mau_probe(struct platform_device *dev)
2105 {
2106         struct mdesc_handle *mdesc;
2107         struct n2_mau *mp;
2108         int err;
2109
2110         n2_spu_driver_version();
2111
2112         pr_info("Found NCP at %pOF\n", dev->dev.of_node);
2113
2114         mp = alloc_ncp();
2115         if (!mp) {
2116                 dev_err(&dev->dev, "%pOF: Unable to allocate ncp.\n",
2117                         dev->dev.of_node);
2118                 return -ENOMEM;
2119         }
2120
2121         err = grab_global_resources();
2122         if (err) {
2123                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2124                         dev->dev.of_node);
2125                 goto out_free_ncp;
2126         }
2127
2128         mdesc = mdesc_grab();
2129
2130         if (!mdesc) {
2131                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2132                         dev->dev.of_node);
2133                 err = -ENODEV;
2134                 goto out_free_global;
2135         }
2136
2137         err = grab_mdesc_irq_props(mdesc, dev, &mp->mau_info, "ncp");
2138         if (err) {
2139                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2140                         dev->dev.of_node);
2141                 mdesc_release(mdesc);
2142                 goto out_free_global;
2143         }
2144
2145         err = spu_mdesc_scan(mdesc, dev, &mp->mau_info, &mp->mau_list,
2146                              "mau", HV_NCS_QTYPE_MAU, mau_intr,
2147                              cpu_to_mau);
2148         mdesc_release(mdesc);
2149
2150         if (err) {
2151                 dev_err(&dev->dev, "%pOF: MAU MDESC scan failed.\n",
2152                         dev->dev.of_node);
2153                 goto out_free_global;
2154         }
2155
2156         dev_set_drvdata(&dev->dev, mp);
2157
2158         return 0;
2159
2160 out_free_global:
2161         release_global_resources();
2162
2163 out_free_ncp:
2164         free_ncp(mp);
2165
2166         return err;
2167 }
2168
2169 static int n2_mau_remove(struct platform_device *dev)
2170 {
2171         struct n2_mau *mp = dev_get_drvdata(&dev->dev);
2172
2173         spu_list_destroy(&mp->mau_list);
2174
2175         release_global_resources();
2176
2177         free_ncp(mp);
2178
2179         return 0;
2180 }
2181
2182 static const struct of_device_id n2_crypto_match[] = {
2183         {
2184                 .name = "n2cp",
2185                 .compatible = "SUNW,n2-cwq",
2186         },
2187         {
2188                 .name = "n2cp",
2189                 .compatible = "SUNW,vf-cwq",
2190         },
2191         {
2192                 .name = "n2cp",
2193                 .compatible = "SUNW,kt-cwq",
2194         },
2195         {},
2196 };
2197
2198 MODULE_DEVICE_TABLE(of, n2_crypto_match);
2199
2200 static struct platform_driver n2_crypto_driver = {
2201         .driver = {
2202                 .name           =       "n2cp",
2203                 .of_match_table =       n2_crypto_match,
2204         },
2205         .probe          =       n2_crypto_probe,
2206         .remove         =       n2_crypto_remove,
2207 };
2208
2209 static const struct of_device_id n2_mau_match[] = {
2210         {
2211                 .name = "ncp",
2212                 .compatible = "SUNW,n2-mau",
2213         },
2214         {
2215                 .name = "ncp",
2216                 .compatible = "SUNW,vf-mau",
2217         },
2218         {
2219                 .name = "ncp",
2220                 .compatible = "SUNW,kt-mau",
2221         },
2222         {},
2223 };
2224
2225 MODULE_DEVICE_TABLE(of, n2_mau_match);
2226
2227 static struct platform_driver n2_mau_driver = {
2228         .driver = {
2229                 .name           =       "ncp",
2230                 .of_match_table =       n2_mau_match,
2231         },
2232         .probe          =       n2_mau_probe,
2233         .remove         =       n2_mau_remove,
2234 };
2235
2236 static struct platform_driver * const drivers[] = {
2237         &n2_crypto_driver,
2238         &n2_mau_driver,
2239 };
2240
2241 static int __init n2_init(void)
2242 {
2243         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2244 }
2245
2246 static void __exit n2_exit(void)
2247 {
2248         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2249 }
2250
2251 module_init(n2_init);
2252 module_exit(n2_exit);