1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_pstate.c: Native P state management for Intel processors
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <trace/events/power.h>
29 #include <asm/div64.h>
31 #include <asm/cpu_device_id.h>
32 #include <asm/cpufeature.h>
33 #include <asm/intel-family.h>
35 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
37 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
38 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
41 #include <acpi/processor.h>
42 #include <acpi/cppc_acpi.h>
46 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
47 #define fp_toint(X) ((X) >> FRAC_BITS)
49 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
52 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
53 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
54 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
56 static inline int32_t mul_fp(int32_t x, int32_t y)
58 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
61 static inline int32_t div_fp(s64 x, s64 y)
63 return div64_s64((int64_t)x << FRAC_BITS, y);
66 static inline int ceiling_fp(int32_t x)
71 mask = (1 << FRAC_BITS) - 1;
77 static inline int32_t percent_fp(int percent)
79 return div_fp(percent, 100);
82 static inline u64 mul_ext_fp(u64 x, u64 y)
84 return (x * y) >> EXT_FRAC_BITS;
87 static inline u64 div_ext_fp(u64 x, u64 y)
89 return div64_u64(x << EXT_FRAC_BITS, y);
92 static inline int32_t percent_ext_fp(int percent)
94 return div_ext_fp(percent, 100);
98 * struct sample - Store performance sample
99 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
100 * performance during last sample period
101 * @busy_scaled: Scaled busy value which is used to calculate next
102 * P state. This can be different than core_avg_perf
103 * to account for cpu idle period
104 * @aperf: Difference of actual performance frequency clock count
105 * read from APERF MSR between last and current sample
106 * @mperf: Difference of maximum performance frequency clock count
107 * read from MPERF MSR between last and current sample
108 * @tsc: Difference of time stamp counter between last and
110 * @time: Current time from scheduler
112 * This structure is used in the cpudata structure to store performance sample
113 * data for choosing next P State.
116 int32_t core_avg_perf;
125 * struct pstate_data - Store P state data
126 * @current_pstate: Current requested P state
127 * @min_pstate: Min P state possible for this platform
128 * @max_pstate: Max P state possible for this platform
129 * @max_pstate_physical:This is physical Max P state for a processor
130 * This can be higher than the max_pstate which can
131 * be limited by platform thermal design power limits
132 * @scaling: Scaling factor to convert frequency to cpufreq
134 * @turbo_pstate: Max Turbo P state possible for this platform
135 * @max_freq: @max_pstate frequency in cpufreq units
136 * @turbo_freq: @turbo_pstate frequency in cpufreq units
138 * Stores the per cpu model P state limits and current P state.
144 int max_pstate_physical;
147 unsigned int max_freq;
148 unsigned int turbo_freq;
152 * struct vid_data - Stores voltage information data
153 * @min: VID data for this platform corresponding to
155 * @max: VID data corresponding to the highest P State.
156 * @turbo: VID data for turbo P state
157 * @ratio: Ratio of (vid max - vid min) /
158 * (max P state - Min P State)
160 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
161 * This data is used in Atom platforms, where in addition to target P state,
162 * the voltage data needs to be specified to select next P State.
172 * struct global_params - Global parameters, mostly tunable via sysfs.
173 * @no_turbo: Whether or not to use turbo P-states.
174 * @turbo_disabled: Whethet or not turbo P-states are available at all,
175 * based on the MSR_IA32_MISC_ENABLE value and whether or
176 * not the maximum reported turbo P-state is different from
177 * the maximum reported non-turbo one.
178 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
179 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
181 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
184 struct global_params {
187 bool turbo_disabled_mf;
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
228 * @hwp_boost_min: Last HWP boosted min performance
230 * This structure stores per CPU instance data for all CPUs.
236 struct update_util_data update_util;
237 bool update_util_set;
239 struct pstate_data pstate;
243 u64 last_sample_time;
244 u64 aperf_mperf_shift;
248 u64 prev_cummulative_iowait;
249 struct sample sample;
250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
256 unsigned int iowait_boost;
264 unsigned int sched_flags;
268 static struct cpudata **all_cpu_data;
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
283 struct pstate_funcs {
284 int (*get_max)(void);
285 int (*get_max_physical)(void);
286 int (*get_min)(void);
287 int (*get_turbo)(void);
288 int (*get_scaling)(void);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
294 static struct pstate_funcs pstate_funcs __read_mostly;
296 static int hwp_active __read_mostly;
297 static int hwp_mode_bdw __read_mostly;
298 static bool per_cpu_limits __read_mostly;
299 static bool hwp_boost __read_mostly;
301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304 static bool acpi_ppc;
307 static struct global_params global;
309 static DEFINE_MUTEX(intel_pstate_driver_lock);
310 static DEFINE_MUTEX(intel_pstate_limits_lock);
314 static bool intel_pstate_acpi_pm_profile_server(void)
316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
323 static bool intel_pstate_get_ppc_enable_status(void)
325 if (intel_pstate_acpi_pm_profile_server())
331 #ifdef CONFIG_ACPI_CPPC_LIB
333 /* The work item is needed to avoid CPU hotplug locking issues */
334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
336 sched_set_itmt_support();
339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
341 static void intel_pstate_set_itmt_prio(int cpu)
343 struct cppc_perf_caps cppc_perf;
344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
347 ret = cppc_get_perf_caps(cpu, &cppc_perf);
352 * The priorities can be set regardless of whether or not
353 * sched_set_itmt_support(true) has been called and it is valid to
354 * update them at any time after it has been called.
356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
358 if (max_highest_perf <= min_highest_perf) {
359 if (cppc_perf.highest_perf > max_highest_perf)
360 max_highest_perf = cppc_perf.highest_perf;
362 if (cppc_perf.highest_perf < min_highest_perf)
363 min_highest_perf = cppc_perf.highest_perf;
365 if (max_highest_perf > min_highest_perf) {
367 * This code can be run during CPU online under the
368 * CPU hotplug locks, so sched_set_itmt_support()
369 * cannot be called from here. Queue up a work item
372 schedule_work(&sched_itmt_work);
377 static int intel_pstate_get_cppc_guranteed(int cpu)
379 struct cppc_perf_caps cppc_perf;
382 ret = cppc_get_perf_caps(cpu, &cppc_perf);
386 if (cppc_perf.guaranteed_perf)
387 return cppc_perf.guaranteed_perf;
389 return cppc_perf.nominal_perf;
392 #else /* CONFIG_ACPI_CPPC_LIB */
393 static void intel_pstate_set_itmt_prio(int cpu)
396 #endif /* CONFIG_ACPI_CPPC_LIB */
398 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
405 intel_pstate_set_itmt_prio(policy->cpu);
409 if (!intel_pstate_get_ppc_enable_status())
412 cpu = all_cpu_data[policy->cpu];
414 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
420 * Check if the control value in _PSS is for PERF_CTL MSR, which should
421 * guarantee that the states returned by it map to the states in our
424 if (cpu->acpi_perf_data.control_register.space_id !=
425 ACPI_ADR_SPACE_FIXED_HARDWARE)
429 * If there is only one entry _PSS, simply ignore _PSS and continue as
430 * usual without taking _PSS into account
432 if (cpu->acpi_perf_data.state_count < 2)
435 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
436 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
437 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
438 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
439 (u32) cpu->acpi_perf_data.states[i].core_frequency,
440 (u32) cpu->acpi_perf_data.states[i].power,
441 (u32) cpu->acpi_perf_data.states[i].control);
445 * The _PSS table doesn't contain whole turbo frequency range.
446 * This just contains +1 MHZ above the max non turbo frequency,
447 * with control value corresponding to max turbo ratio. But
448 * when cpufreq set policy is called, it will call with this
449 * max frequency, which will cause a reduced performance as
450 * this driver uses real max turbo frequency as the max
451 * frequency. So correct this frequency in _PSS table to
452 * correct max turbo frequency based on the turbo state.
453 * Also need to convert to MHz as _PSS freq is in MHz.
455 if (!global.turbo_disabled)
456 cpu->acpi_perf_data.states[0].core_frequency =
457 policy->cpuinfo.max_freq / 1000;
458 cpu->valid_pss_table = true;
459 pr_debug("_PPC limits will be enforced\n");
464 cpu->valid_pss_table = false;
465 acpi_processor_unregister_performance(policy->cpu);
468 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
472 cpu = all_cpu_data[policy->cpu];
473 if (!cpu->valid_pss_table)
476 acpi_processor_unregister_performance(policy->cpu);
478 #else /* CONFIG_ACPI */
479 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
483 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
487 static inline bool intel_pstate_acpi_pm_profile_server(void)
491 #endif /* CONFIG_ACPI */
493 #ifndef CONFIG_ACPI_CPPC_LIB
494 static int intel_pstate_get_cppc_guranteed(int cpu)
498 #endif /* CONFIG_ACPI_CPPC_LIB */
500 static inline void update_turbo_state(void)
505 cpu = all_cpu_data[0];
506 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
507 global.turbo_disabled =
508 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
509 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
512 static int min_perf_pct_min(void)
514 struct cpudata *cpu = all_cpu_data[0];
515 int turbo_pstate = cpu->pstate.turbo_pstate;
517 return turbo_pstate ?
518 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
521 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
526 if (!boot_cpu_has(X86_FEATURE_EPB))
529 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
533 return (s16)(epb & 0x0f);
536 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
540 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
542 * When hwp_req_data is 0, means that caller didn't read
543 * MSR_HWP_REQUEST, so need to read and get EPP.
546 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
551 epp = (hwp_req_data >> 24) & 0xff;
553 /* When there is no EPP present, HWP uses EPB settings */
554 epp = intel_pstate_get_epb(cpu_data);
560 static int intel_pstate_set_epb(int cpu, s16 pref)
565 if (!boot_cpu_has(X86_FEATURE_EPB))
568 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
572 epb = (epb & ~0x0f) | pref;
573 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
579 * EPP/EPB display strings corresponding to EPP index in the
580 * energy_perf_strings[]
582 *-------------------------------------
585 * 2 balance_performance
589 static const char * const energy_perf_strings[] = {
592 "balance_performance",
597 static const unsigned int epp_values[] = {
599 HWP_EPP_BALANCE_PERFORMANCE,
600 HWP_EPP_BALANCE_POWERSAVE,
604 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
609 epp = intel_pstate_get_epp(cpu_data, 0);
613 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
614 if (epp == HWP_EPP_PERFORMANCE)
616 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
618 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
622 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
625 * 0x00-0x03 : Performance
626 * 0x04-0x07 : Balance performance
627 * 0x08-0x0B : Balance power
629 * The EPB is a 4 bit value, but our ranges restrict the
630 * value which can be set. Here only using top two bits
633 index = (epp >> 2) + 1;
639 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
646 epp = cpu_data->epp_default;
648 mutex_lock(&intel_pstate_limits_lock);
650 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
653 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
657 value &= ~GENMASK_ULL(31, 24);
660 epp = epp_values[pref_index - 1];
662 value |= (u64)epp << 24;
663 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
666 epp = (pref_index - 1) << 2;
667 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
670 mutex_unlock(&intel_pstate_limits_lock);
675 static ssize_t show_energy_performance_available_preferences(
676 struct cpufreq_policy *policy, char *buf)
681 while (energy_perf_strings[i] != NULL)
682 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
684 ret += sprintf(&buf[ret], "\n");
689 cpufreq_freq_attr_ro(energy_performance_available_preferences);
691 static ssize_t store_energy_performance_preference(
692 struct cpufreq_policy *policy, const char *buf, size_t count)
694 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
695 char str_preference[21];
698 ret = sscanf(buf, "%20s", str_preference);
702 ret = match_string(energy_perf_strings, -1, str_preference);
706 intel_pstate_set_energy_pref_index(cpu_data, ret);
710 static ssize_t show_energy_performance_preference(
711 struct cpufreq_policy *policy, char *buf)
713 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
716 preference = intel_pstate_get_energy_pref_index(cpu_data);
720 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
723 cpufreq_freq_attr_rw(energy_performance_preference);
725 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
731 ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
733 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
734 ratio = HWP_GUARANTEED_PERF(cap);
737 cpu = all_cpu_data[policy->cpu];
739 return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
742 cpufreq_freq_attr_ro(base_frequency);
744 static struct freq_attr *hwp_cpufreq_attrs[] = {
745 &energy_performance_preference,
746 &energy_performance_available_preferences,
751 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
756 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
757 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
759 *current_max = HWP_GUARANTEED_PERF(cap);
761 *current_max = HWP_HIGHEST_PERF(cap);
763 *phy_max = HWP_HIGHEST_PERF(cap);
766 static void intel_pstate_hwp_set(unsigned int cpu)
768 struct cpudata *cpu_data = all_cpu_data[cpu];
773 max = cpu_data->max_perf_ratio;
774 min = cpu_data->min_perf_ratio;
776 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
779 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
781 value &= ~HWP_MIN_PERF(~0L);
782 value |= HWP_MIN_PERF(min);
784 value &= ~HWP_MAX_PERF(~0L);
785 value |= HWP_MAX_PERF(max);
787 if (cpu_data->epp_policy == cpu_data->policy)
790 cpu_data->epp_policy = cpu_data->policy;
792 if (cpu_data->epp_saved >= 0) {
793 epp = cpu_data->epp_saved;
794 cpu_data->epp_saved = -EINVAL;
798 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
799 epp = intel_pstate_get_epp(cpu_data, value);
800 cpu_data->epp_powersave = epp;
801 /* If EPP read was failed, then don't try to write */
807 /* skip setting EPP, when saved value is invalid */
808 if (cpu_data->epp_powersave < 0)
812 * No need to restore EPP when it is not zero. This
814 * - Policy is not changed
815 * - user has manually changed
816 * - Error reading EPB
818 epp = intel_pstate_get_epp(cpu_data, value);
822 epp = cpu_data->epp_powersave;
825 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
826 value &= ~GENMASK_ULL(31, 24);
827 value |= (u64)epp << 24;
829 intel_pstate_set_epb(cpu, epp);
832 WRITE_ONCE(cpu_data->hwp_req_cached, value);
833 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
836 static void intel_pstate_hwp_force_min_perf(int cpu)
841 value = all_cpu_data[cpu]->hwp_req_cached;
842 value &= ~GENMASK_ULL(31, 0);
843 min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
845 /* Set hwp_max = hwp_min */
846 value |= HWP_MAX_PERF(min_perf);
847 value |= HWP_MIN_PERF(min_perf);
850 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
851 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
853 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
856 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
858 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
863 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
868 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
870 static int intel_pstate_resume(struct cpufreq_policy *policy)
875 mutex_lock(&intel_pstate_limits_lock);
877 if (policy->cpu == 0)
878 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
880 all_cpu_data[policy->cpu]->epp_policy = 0;
881 intel_pstate_hwp_set(policy->cpu);
883 mutex_unlock(&intel_pstate_limits_lock);
888 static void intel_pstate_update_policies(void)
892 for_each_possible_cpu(cpu)
893 cpufreq_update_policy(cpu);
896 static void intel_pstate_update_max_freq(unsigned int cpu)
898 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
899 struct cpudata *cpudata;
904 cpudata = all_cpu_data[cpu];
905 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
906 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
908 refresh_frequency_limits(policy);
910 cpufreq_cpu_release(policy);
913 static void intel_pstate_update_limits(unsigned int cpu)
915 mutex_lock(&intel_pstate_driver_lock);
917 update_turbo_state();
919 * If turbo has been turned on or off globally, policy limits for
920 * all CPUs need to be updated to reflect that.
922 if (global.turbo_disabled_mf != global.turbo_disabled) {
923 global.turbo_disabled_mf = global.turbo_disabled;
924 for_each_possible_cpu(cpu)
925 intel_pstate_update_max_freq(cpu);
927 cpufreq_update_policy(cpu);
930 mutex_unlock(&intel_pstate_driver_lock);
933 /************************** sysfs begin ************************/
934 #define show_one(file_name, object) \
935 static ssize_t show_##file_name \
936 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
938 return sprintf(buf, "%u\n", global.object); \
941 static ssize_t intel_pstate_show_status(char *buf);
942 static int intel_pstate_update_status(const char *buf, size_t size);
944 static ssize_t show_status(struct kobject *kobj,
945 struct kobj_attribute *attr, char *buf)
949 mutex_lock(&intel_pstate_driver_lock);
950 ret = intel_pstate_show_status(buf);
951 mutex_unlock(&intel_pstate_driver_lock);
956 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
957 const char *buf, size_t count)
959 char *p = memchr(buf, '\n', count);
962 mutex_lock(&intel_pstate_driver_lock);
963 ret = intel_pstate_update_status(buf, p ? p - buf : count);
964 mutex_unlock(&intel_pstate_driver_lock);
966 return ret < 0 ? ret : count;
969 static ssize_t show_turbo_pct(struct kobject *kobj,
970 struct kobj_attribute *attr, char *buf)
973 int total, no_turbo, turbo_pct;
976 mutex_lock(&intel_pstate_driver_lock);
978 if (!intel_pstate_driver) {
979 mutex_unlock(&intel_pstate_driver_lock);
983 cpu = all_cpu_data[0];
985 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
986 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
987 turbo_fp = div_fp(no_turbo, total);
988 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
990 mutex_unlock(&intel_pstate_driver_lock);
992 return sprintf(buf, "%u\n", turbo_pct);
995 static ssize_t show_num_pstates(struct kobject *kobj,
996 struct kobj_attribute *attr, char *buf)
1001 mutex_lock(&intel_pstate_driver_lock);
1003 if (!intel_pstate_driver) {
1004 mutex_unlock(&intel_pstate_driver_lock);
1008 cpu = all_cpu_data[0];
1009 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1011 mutex_unlock(&intel_pstate_driver_lock);
1013 return sprintf(buf, "%u\n", total);
1016 static ssize_t show_no_turbo(struct kobject *kobj,
1017 struct kobj_attribute *attr, char *buf)
1021 mutex_lock(&intel_pstate_driver_lock);
1023 if (!intel_pstate_driver) {
1024 mutex_unlock(&intel_pstate_driver_lock);
1028 update_turbo_state();
1029 if (global.turbo_disabled)
1030 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1032 ret = sprintf(buf, "%u\n", global.no_turbo);
1034 mutex_unlock(&intel_pstate_driver_lock);
1039 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1040 const char *buf, size_t count)
1045 ret = sscanf(buf, "%u", &input);
1049 mutex_lock(&intel_pstate_driver_lock);
1051 if (!intel_pstate_driver) {
1052 mutex_unlock(&intel_pstate_driver_lock);
1056 mutex_lock(&intel_pstate_limits_lock);
1058 update_turbo_state();
1059 if (global.turbo_disabled) {
1060 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1061 mutex_unlock(&intel_pstate_limits_lock);
1062 mutex_unlock(&intel_pstate_driver_lock);
1066 global.no_turbo = clamp_t(int, input, 0, 1);
1068 if (global.no_turbo) {
1069 struct cpudata *cpu = all_cpu_data[0];
1070 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1072 /* Squash the global minimum into the permitted range. */
1073 if (global.min_perf_pct > pct)
1074 global.min_perf_pct = pct;
1077 mutex_unlock(&intel_pstate_limits_lock);
1079 intel_pstate_update_policies();
1081 mutex_unlock(&intel_pstate_driver_lock);
1086 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1087 const char *buf, size_t count)
1092 ret = sscanf(buf, "%u", &input);
1096 mutex_lock(&intel_pstate_driver_lock);
1098 if (!intel_pstate_driver) {
1099 mutex_unlock(&intel_pstate_driver_lock);
1103 mutex_lock(&intel_pstate_limits_lock);
1105 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1107 mutex_unlock(&intel_pstate_limits_lock);
1109 intel_pstate_update_policies();
1111 mutex_unlock(&intel_pstate_driver_lock);
1116 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1117 const char *buf, size_t count)
1122 ret = sscanf(buf, "%u", &input);
1126 mutex_lock(&intel_pstate_driver_lock);
1128 if (!intel_pstate_driver) {
1129 mutex_unlock(&intel_pstate_driver_lock);
1133 mutex_lock(&intel_pstate_limits_lock);
1135 global.min_perf_pct = clamp_t(int, input,
1136 min_perf_pct_min(), global.max_perf_pct);
1138 mutex_unlock(&intel_pstate_limits_lock);
1140 intel_pstate_update_policies();
1142 mutex_unlock(&intel_pstate_driver_lock);
1147 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1148 struct kobj_attribute *attr, char *buf)
1150 return sprintf(buf, "%u\n", hwp_boost);
1153 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1154 struct kobj_attribute *b,
1155 const char *buf, size_t count)
1160 ret = kstrtouint(buf, 10, &input);
1164 mutex_lock(&intel_pstate_driver_lock);
1165 hwp_boost = !!input;
1166 intel_pstate_update_policies();
1167 mutex_unlock(&intel_pstate_driver_lock);
1172 show_one(max_perf_pct, max_perf_pct);
1173 show_one(min_perf_pct, min_perf_pct);
1175 define_one_global_rw(status);
1176 define_one_global_rw(no_turbo);
1177 define_one_global_rw(max_perf_pct);
1178 define_one_global_rw(min_perf_pct);
1179 define_one_global_ro(turbo_pct);
1180 define_one_global_ro(num_pstates);
1181 define_one_global_rw(hwp_dynamic_boost);
1183 static struct attribute *intel_pstate_attributes[] = {
1191 static const struct attribute_group intel_pstate_attr_group = {
1192 .attrs = intel_pstate_attributes,
1195 static void __init intel_pstate_sysfs_expose_params(void)
1197 struct kobject *intel_pstate_kobject;
1200 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1201 &cpu_subsys.dev_root->kobj);
1202 if (WARN_ON(!intel_pstate_kobject))
1205 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1210 * If per cpu limits are enforced there are no global limits, so
1211 * return without creating max/min_perf_pct attributes
1216 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1219 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1223 rc = sysfs_create_file(intel_pstate_kobject,
1224 &hwp_dynamic_boost.attr);
1228 /************************** sysfs end ************************/
1230 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1232 /* First disable HWP notification interrupt as we don't process them */
1233 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1234 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1236 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1237 cpudata->epp_policy = 0;
1238 if (cpudata->epp_default == -EINVAL)
1239 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1242 #define MSR_IA32_POWER_CTL_BIT_EE 19
1244 /* Disable energy efficiency optimization */
1245 static void intel_pstate_disable_ee(int cpu)
1250 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1254 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1255 pr_info("Disabling energy efficiency optimization\n");
1256 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1257 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1261 static int atom_get_min_pstate(void)
1265 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1266 return (value >> 8) & 0x7F;
1269 static int atom_get_max_pstate(void)
1273 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1274 return (value >> 16) & 0x7F;
1277 static int atom_get_turbo_pstate(void)
1281 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1282 return value & 0x7F;
1285 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1291 val = (u64)pstate << 8;
1292 if (global.no_turbo && !global.turbo_disabled)
1293 val |= (u64)1 << 32;
1295 vid_fp = cpudata->vid.min + mul_fp(
1296 int_tofp(pstate - cpudata->pstate.min_pstate),
1297 cpudata->vid.ratio);
1299 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1300 vid = ceiling_fp(vid_fp);
1302 if (pstate > cpudata->pstate.max_pstate)
1303 vid = cpudata->vid.turbo;
1308 static int silvermont_get_scaling(void)
1312 /* Defined in Table 35-6 from SDM (Sept 2015) */
1313 static int silvermont_freq_table[] = {
1314 83300, 100000, 133300, 116700, 80000};
1316 rdmsrl(MSR_FSB_FREQ, value);
1320 return silvermont_freq_table[i];
1323 static int airmont_get_scaling(void)
1327 /* Defined in Table 35-10 from SDM (Sept 2015) */
1328 static int airmont_freq_table[] = {
1329 83300, 100000, 133300, 116700, 80000,
1330 93300, 90000, 88900, 87500};
1332 rdmsrl(MSR_FSB_FREQ, value);
1336 return airmont_freq_table[i];
1339 static void atom_get_vid(struct cpudata *cpudata)
1343 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1344 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1345 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1346 cpudata->vid.ratio = div_fp(
1347 cpudata->vid.max - cpudata->vid.min,
1348 int_tofp(cpudata->pstate.max_pstate -
1349 cpudata->pstate.min_pstate));
1351 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1352 cpudata->vid.turbo = value & 0x7f;
1355 static int core_get_min_pstate(void)
1359 rdmsrl(MSR_PLATFORM_INFO, value);
1360 return (value >> 40) & 0xFF;
1363 static int core_get_max_pstate_physical(void)
1367 rdmsrl(MSR_PLATFORM_INFO, value);
1368 return (value >> 8) & 0xFF;
1371 static int core_get_tdp_ratio(u64 plat_info)
1373 /* Check how many TDP levels present */
1374 if (plat_info & 0x600000000) {
1380 /* Get the TDP level (0, 1, 2) to get ratios */
1381 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1385 /* TDP MSR are continuous starting at 0x648 */
1386 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1387 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1391 /* For level 1 and 2, bits[23:16] contain the ratio */
1392 if (tdp_ctrl & 0x03)
1395 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1396 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1398 return (int)tdp_ratio;
1404 static int core_get_max_pstate(void)
1412 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1413 max_pstate = (plat_info >> 8) & 0xFF;
1415 tdp_ratio = core_get_tdp_ratio(plat_info);
1420 /* Turbo activation ratio is not used on HWP platforms */
1424 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1428 /* Do some sanity checking for safety */
1429 tar_levels = tar & 0xff;
1430 if (tdp_ratio - 1 == tar_levels) {
1431 max_pstate = tar_levels;
1432 pr_debug("max_pstate=TAC %x\n", max_pstate);
1439 static int core_get_turbo_pstate(void)
1444 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1445 nont = core_get_max_pstate();
1446 ret = (value) & 255;
1452 static inline int core_get_scaling(void)
1457 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1461 val = (u64)pstate << 8;
1462 if (global.no_turbo && !global.turbo_disabled)
1463 val |= (u64)1 << 32;
1468 static int knl_get_aperf_mperf_shift(void)
1473 static int knl_get_turbo_pstate(void)
1478 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1479 nont = core_get_max_pstate();
1480 ret = (((value) >> 8) & 0xFF);
1486 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1488 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1489 cpu->pstate.current_pstate = pstate;
1491 * Generally, there is no guarantee that this code will always run on
1492 * the CPU being updated, so force the register update to run on the
1495 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1496 pstate_funcs.get_val(cpu, pstate));
1499 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1501 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1504 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1506 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1508 update_turbo_state();
1509 intel_pstate_set_pstate(cpu, pstate);
1512 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1514 cpu->pstate.min_pstate = pstate_funcs.get_min();
1515 cpu->pstate.max_pstate = pstate_funcs.get_max();
1516 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1517 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1518 cpu->pstate.scaling = pstate_funcs.get_scaling();
1519 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1521 if (hwp_active && !hwp_mode_bdw) {
1522 unsigned int phy_max, current_max;
1524 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max);
1525 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1527 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1530 if (pstate_funcs.get_aperf_mperf_shift)
1531 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1533 if (pstate_funcs.get_vid)
1534 pstate_funcs.get_vid(cpu);
1536 intel_pstate_set_min_pstate(cpu);
1540 * Long hold time will keep high perf limits for long time,
1541 * which negatively impacts perf/watt for some workloads,
1542 * like specpower. 3ms is based on experiements on some
1545 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1547 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1549 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1550 u32 max_limit = (hwp_req & 0xff00) >> 8;
1551 u32 min_limit = (hwp_req & 0xff);
1555 * Cases to consider (User changes via sysfs or boot time):
1556 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1558 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1559 * Should result in one level boost only for P0.
1560 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1561 * Should result in two level boost:
1562 * (min + p1)/2 and P1.
1563 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1564 * Should result in three level boost:
1565 * (min + p1)/2, P1 and P0.
1568 /* If max and min are equal or already at max, nothing to boost */
1569 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1572 if (!cpu->hwp_boost_min)
1573 cpu->hwp_boost_min = min_limit;
1575 /* level at half way mark between min and guranteed */
1576 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1578 if (cpu->hwp_boost_min < boost_level1)
1579 cpu->hwp_boost_min = boost_level1;
1580 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1581 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1582 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1583 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1584 cpu->hwp_boost_min = max_limit;
1588 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1589 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1590 cpu->last_update = cpu->sample.time;
1593 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1595 if (cpu->hwp_boost_min) {
1598 /* Check if we are idle for hold time to boost down */
1599 expired = time_after64(cpu->sample.time, cpu->last_update +
1600 hwp_boost_hold_time_ns);
1602 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1603 cpu->hwp_boost_min = 0;
1606 cpu->last_update = cpu->sample.time;
1609 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1612 cpu->sample.time = time;
1614 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1617 cpu->sched_flags = 0;
1619 * Set iowait_boost flag and update time. Since IO WAIT flag
1620 * is set all the time, we can't just conclude that there is
1621 * some IO bound activity is scheduled on this CPU with just
1622 * one occurrence. If we receive at least two in two
1623 * consecutive ticks, then we treat as boost candidate.
1625 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1628 cpu->last_io_update = time;
1631 intel_pstate_hwp_boost_up(cpu);
1634 intel_pstate_hwp_boost_down(cpu);
1638 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1639 u64 time, unsigned int flags)
1641 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1643 cpu->sched_flags |= flags;
1645 if (smp_processor_id() == cpu->cpu)
1646 intel_pstate_update_util_hwp_local(cpu, time);
1649 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1651 struct sample *sample = &cpu->sample;
1653 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1656 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1659 unsigned long flags;
1662 local_irq_save(flags);
1663 rdmsrl(MSR_IA32_APERF, aperf);
1664 rdmsrl(MSR_IA32_MPERF, mperf);
1666 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1667 local_irq_restore(flags);
1670 local_irq_restore(flags);
1672 cpu->last_sample_time = cpu->sample.time;
1673 cpu->sample.time = time;
1674 cpu->sample.aperf = aperf;
1675 cpu->sample.mperf = mperf;
1676 cpu->sample.tsc = tsc;
1677 cpu->sample.aperf -= cpu->prev_aperf;
1678 cpu->sample.mperf -= cpu->prev_mperf;
1679 cpu->sample.tsc -= cpu->prev_tsc;
1681 cpu->prev_aperf = aperf;
1682 cpu->prev_mperf = mperf;
1683 cpu->prev_tsc = tsc;
1685 * First time this function is invoked in a given cycle, all of the
1686 * previous sample data fields are equal to zero or stale and they must
1687 * be populated with meaningful numbers for things to work, so assume
1688 * that sample.time will always be reset before setting the utilization
1689 * update hook and make the caller skip the sample then.
1691 if (cpu->last_sample_time) {
1692 intel_pstate_calc_avg_perf(cpu);
1698 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1700 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1703 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1705 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1706 cpu->sample.core_avg_perf);
1709 static inline int32_t get_target_pstate(struct cpudata *cpu)
1711 struct sample *sample = &cpu->sample;
1713 int target, avg_pstate;
1715 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1718 if (busy_frac < cpu->iowait_boost)
1719 busy_frac = cpu->iowait_boost;
1721 sample->busy_scaled = busy_frac * 100;
1723 target = global.no_turbo || global.turbo_disabled ?
1724 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1725 target += target >> 2;
1726 target = mul_fp(target, busy_frac);
1727 if (target < cpu->pstate.min_pstate)
1728 target = cpu->pstate.min_pstate;
1731 * If the average P-state during the previous cycle was higher than the
1732 * current target, add 50% of the difference to the target to reduce
1733 * possible performance oscillations and offset possible performance
1734 * loss related to moving the workload from one CPU to another within
1737 avg_pstate = get_avg_pstate(cpu);
1738 if (avg_pstate > target)
1739 target += (avg_pstate - target) >> 1;
1744 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1746 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1747 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1749 return clamp_t(int, pstate, min_pstate, max_pstate);
1752 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1754 if (pstate == cpu->pstate.current_pstate)
1757 cpu->pstate.current_pstate = pstate;
1758 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1761 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1763 int from = cpu->pstate.current_pstate;
1764 struct sample *sample;
1767 update_turbo_state();
1769 target_pstate = get_target_pstate(cpu);
1770 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1771 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1772 intel_pstate_update_pstate(cpu, target_pstate);
1774 sample = &cpu->sample;
1775 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1776 fp_toint(sample->busy_scaled),
1778 cpu->pstate.current_pstate,
1782 get_avg_frequency(cpu),
1783 fp_toint(cpu->iowait_boost * 100));
1786 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1789 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1792 /* Don't allow remote callbacks */
1793 if (smp_processor_id() != cpu->cpu)
1796 delta_ns = time - cpu->last_update;
1797 if (flags & SCHED_CPUFREQ_IOWAIT) {
1798 /* Start over if the CPU may have been idle. */
1799 if (delta_ns > TICK_NSEC) {
1800 cpu->iowait_boost = ONE_EIGHTH_FP;
1801 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
1802 cpu->iowait_boost <<= 1;
1803 if (cpu->iowait_boost > int_tofp(1))
1804 cpu->iowait_boost = int_tofp(1);
1806 cpu->iowait_boost = ONE_EIGHTH_FP;
1808 } else if (cpu->iowait_boost) {
1809 /* Clear iowait_boost if the CPU may have been idle. */
1810 if (delta_ns > TICK_NSEC)
1811 cpu->iowait_boost = 0;
1813 cpu->iowait_boost >>= 1;
1815 cpu->last_update = time;
1816 delta_ns = time - cpu->sample.time;
1817 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1820 if (intel_pstate_sample(cpu, time))
1821 intel_pstate_adjust_pstate(cpu);
1824 static struct pstate_funcs core_funcs = {
1825 .get_max = core_get_max_pstate,
1826 .get_max_physical = core_get_max_pstate_physical,
1827 .get_min = core_get_min_pstate,
1828 .get_turbo = core_get_turbo_pstate,
1829 .get_scaling = core_get_scaling,
1830 .get_val = core_get_val,
1833 static const struct pstate_funcs silvermont_funcs = {
1834 .get_max = atom_get_max_pstate,
1835 .get_max_physical = atom_get_max_pstate,
1836 .get_min = atom_get_min_pstate,
1837 .get_turbo = atom_get_turbo_pstate,
1838 .get_val = atom_get_val,
1839 .get_scaling = silvermont_get_scaling,
1840 .get_vid = atom_get_vid,
1843 static const struct pstate_funcs airmont_funcs = {
1844 .get_max = atom_get_max_pstate,
1845 .get_max_physical = atom_get_max_pstate,
1846 .get_min = atom_get_min_pstate,
1847 .get_turbo = atom_get_turbo_pstate,
1848 .get_val = atom_get_val,
1849 .get_scaling = airmont_get_scaling,
1850 .get_vid = atom_get_vid,
1853 static const struct pstate_funcs knl_funcs = {
1854 .get_max = core_get_max_pstate,
1855 .get_max_physical = core_get_max_pstate_physical,
1856 .get_min = core_get_min_pstate,
1857 .get_turbo = knl_get_turbo_pstate,
1858 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1859 .get_scaling = core_get_scaling,
1860 .get_val = core_get_val,
1863 #define ICPU(model, policy) \
1864 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1865 (unsigned long)&policy }
1867 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1868 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1869 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1870 ICPU(INTEL_FAM6_ATOM_SILVERMONT, silvermont_funcs),
1871 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1872 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1873 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1874 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1875 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1876 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1877 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1878 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1879 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1880 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1881 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1882 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1883 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1884 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1885 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1886 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1887 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS, core_funcs),
1888 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1891 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1893 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1894 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1895 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1896 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1900 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1901 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1905 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1906 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1907 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1911 static int intel_pstate_init_cpu(unsigned int cpunum)
1913 struct cpudata *cpu;
1915 cpu = all_cpu_data[cpunum];
1918 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1922 all_cpu_data[cpunum] = cpu;
1924 cpu->epp_default = -EINVAL;
1925 cpu->epp_powersave = -EINVAL;
1926 cpu->epp_saved = -EINVAL;
1929 cpu = all_cpu_data[cpunum];
1934 const struct x86_cpu_id *id;
1936 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1938 intel_pstate_disable_ee(cpunum);
1940 intel_pstate_hwp_enable(cpu);
1942 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1943 if (id && intel_pstate_acpi_pm_profile_server())
1947 intel_pstate_get_cpu_pstates(cpu);
1949 pr_debug("controlling: cpu %d\n", cpunum);
1954 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1956 struct cpudata *cpu = all_cpu_data[cpu_num];
1958 if (hwp_active && !hwp_boost)
1961 if (cpu->update_util_set)
1964 /* Prevent intel_pstate_update_util() from using stale data. */
1965 cpu->sample.time = 0;
1966 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1968 intel_pstate_update_util_hwp :
1969 intel_pstate_update_util));
1970 cpu->update_util_set = true;
1973 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1975 struct cpudata *cpu_data = all_cpu_data[cpu];
1977 if (!cpu_data->update_util_set)
1980 cpufreq_remove_update_util_hook(cpu);
1981 cpu_data->update_util_set = false;
1985 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1987 return global.turbo_disabled || global.no_turbo ?
1988 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1991 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1992 struct cpudata *cpu)
1994 int max_freq = intel_pstate_get_max_freq(cpu);
1995 int32_t max_policy_perf, min_policy_perf;
1996 int max_state, turbo_max;
1999 * HWP needs some special consideration, because on BDX the
2000 * HWP_REQUEST uses abstract value to represent performance
2001 * rather than pure ratios.
2004 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2006 max_state = global.no_turbo || global.turbo_disabled ?
2007 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2008 turbo_max = cpu->pstate.turbo_pstate;
2011 max_policy_perf = max_state * policy->max / max_freq;
2012 if (policy->max == policy->min) {
2013 min_policy_perf = max_policy_perf;
2015 min_policy_perf = max_state * policy->min / max_freq;
2016 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2017 0, max_policy_perf);
2020 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2021 policy->cpu, max_state,
2022 min_policy_perf, max_policy_perf);
2024 /* Normalize user input to [min_perf, max_perf] */
2025 if (per_cpu_limits) {
2026 cpu->min_perf_ratio = min_policy_perf;
2027 cpu->max_perf_ratio = max_policy_perf;
2029 int32_t global_min, global_max;
2031 /* Global limits are in percent of the maximum turbo P-state. */
2032 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2033 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2034 global_min = clamp_t(int32_t, global_min, 0, global_max);
2036 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
2037 global_min, global_max);
2039 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2040 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2041 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2042 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2044 /* Make sure min_perf <= max_perf */
2045 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2046 cpu->max_perf_ratio);
2049 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
2050 cpu->max_perf_ratio,
2051 cpu->min_perf_ratio);
2054 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2056 struct cpudata *cpu;
2058 if (!policy->cpuinfo.max_freq)
2061 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2062 policy->cpuinfo.max_freq, policy->max);
2064 cpu = all_cpu_data[policy->cpu];
2065 cpu->policy = policy->policy;
2067 mutex_lock(&intel_pstate_limits_lock);
2069 intel_pstate_update_perf_limits(policy, cpu);
2071 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2073 * NOHZ_FULL CPUs need this as the governor callback may not
2074 * be invoked on them.
2076 intel_pstate_clear_update_util_hook(policy->cpu);
2077 intel_pstate_max_within_limits(cpu);
2079 intel_pstate_set_update_util_hook(policy->cpu);
2084 * When hwp_boost was active before and dynamically it
2085 * was turned off, in that case we need to clear the
2089 intel_pstate_clear_update_util_hook(policy->cpu);
2090 intel_pstate_hwp_set(policy->cpu);
2093 mutex_unlock(&intel_pstate_limits_lock);
2098 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2099 struct cpudata *cpu)
2102 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2103 policy->max < policy->cpuinfo.max_freq &&
2104 policy->max > cpu->pstate.max_freq) {
2105 pr_debug("policy->max > max non turbo frequency\n");
2106 policy->max = policy->cpuinfo.max_freq;
2110 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2112 struct cpudata *cpu = all_cpu_data[policy->cpu];
2114 update_turbo_state();
2115 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2116 intel_pstate_get_max_freq(cpu));
2118 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2119 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2122 intel_pstate_adjust_policy_max(policy, cpu);
2127 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2129 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2132 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2134 pr_debug("CPU %d exiting\n", policy->cpu);
2136 intel_pstate_clear_update_util_hook(policy->cpu);
2138 intel_pstate_hwp_save_state(policy);
2139 intel_pstate_hwp_force_min_perf(policy->cpu);
2141 intel_cpufreq_stop_cpu(policy);
2145 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2147 intel_pstate_exit_perf_limits(policy);
2149 policy->fast_switch_possible = false;
2154 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2156 struct cpudata *cpu;
2159 rc = intel_pstate_init_cpu(policy->cpu);
2163 cpu = all_cpu_data[policy->cpu];
2165 cpu->max_perf_ratio = 0xFF;
2166 cpu->min_perf_ratio = 0;
2168 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2169 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2171 /* cpuinfo and default policy values */
2172 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2173 update_turbo_state();
2174 global.turbo_disabled_mf = global.turbo_disabled;
2175 policy->cpuinfo.max_freq = global.turbo_disabled ?
2176 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2177 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2180 unsigned int max_freq;
2182 max_freq = global.turbo_disabled ?
2183 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2184 if (max_freq < policy->cpuinfo.max_freq)
2185 policy->cpuinfo.max_freq = max_freq;
2188 intel_pstate_init_acpi_perf_limits(policy);
2190 policy->fast_switch_possible = true;
2195 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2197 int ret = __intel_pstate_cpu_init(policy);
2202 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2203 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2205 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2210 static struct cpufreq_driver intel_pstate = {
2211 .flags = CPUFREQ_CONST_LOOPS,
2212 .verify = intel_pstate_verify_policy,
2213 .setpolicy = intel_pstate_set_policy,
2214 .suspend = intel_pstate_hwp_save_state,
2215 .resume = intel_pstate_resume,
2216 .init = intel_pstate_cpu_init,
2217 .exit = intel_pstate_cpu_exit,
2218 .stop_cpu = intel_pstate_stop_cpu,
2219 .update_limits = intel_pstate_update_limits,
2220 .name = "intel_pstate",
2223 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2225 struct cpudata *cpu = all_cpu_data[policy->cpu];
2227 update_turbo_state();
2228 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2229 intel_pstate_get_max_freq(cpu));
2231 intel_pstate_adjust_policy_max(policy, cpu);
2233 intel_pstate_update_perf_limits(policy, cpu);
2238 /* Use of trace in passive mode:
2240 * In passive mode the trace core_busy field (also known as the
2241 * performance field, and lablelled as such on the graphs; also known as
2242 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2243 * driver call was via the normal or fast switch path. Various graphs
2244 * output from the intel_pstate_tracer.py utility that include core_busy
2245 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2246 * so we use 10 to indicate the the normal path through the driver, and
2247 * 90 to indicate the fast switch path through the driver.
2248 * The scaled_busy field is not used, and is set to 0.
2251 #define INTEL_PSTATE_TRACE_TARGET 10
2252 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2254 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2256 struct sample *sample;
2258 if (!trace_pstate_sample_enabled())
2261 if (!intel_pstate_sample(cpu, ktime_get()))
2264 sample = &cpu->sample;
2265 trace_pstate_sample(trace_type,
2268 cpu->pstate.current_pstate,
2272 get_avg_frequency(cpu),
2273 fp_toint(cpu->iowait_boost * 100));
2276 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2277 unsigned int target_freq,
2278 unsigned int relation)
2280 struct cpudata *cpu = all_cpu_data[policy->cpu];
2281 struct cpufreq_freqs freqs;
2282 int target_pstate, old_pstate;
2284 update_turbo_state();
2286 freqs.old = policy->cur;
2287 freqs.new = target_freq;
2289 cpufreq_freq_transition_begin(policy, &freqs);
2291 case CPUFREQ_RELATION_L:
2292 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2294 case CPUFREQ_RELATION_H:
2295 target_pstate = freqs.new / cpu->pstate.scaling;
2298 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2301 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2302 old_pstate = cpu->pstate.current_pstate;
2303 if (target_pstate != cpu->pstate.current_pstate) {
2304 cpu->pstate.current_pstate = target_pstate;
2305 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2306 pstate_funcs.get_val(cpu, target_pstate));
2308 freqs.new = target_pstate * cpu->pstate.scaling;
2309 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2310 cpufreq_freq_transition_end(policy, &freqs, false);
2315 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2316 unsigned int target_freq)
2318 struct cpudata *cpu = all_cpu_data[policy->cpu];
2319 int target_pstate, old_pstate;
2321 update_turbo_state();
2323 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2324 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2325 old_pstate = cpu->pstate.current_pstate;
2326 intel_pstate_update_pstate(cpu, target_pstate);
2327 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2328 return target_pstate * cpu->pstate.scaling;
2331 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2333 int ret = __intel_pstate_cpu_init(policy);
2338 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2339 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2340 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2341 policy->cur = policy->cpuinfo.min_freq;
2346 static struct cpufreq_driver intel_cpufreq = {
2347 .flags = CPUFREQ_CONST_LOOPS,
2348 .verify = intel_cpufreq_verify_policy,
2349 .target = intel_cpufreq_target,
2350 .fast_switch = intel_cpufreq_fast_switch,
2351 .init = intel_cpufreq_cpu_init,
2352 .exit = intel_pstate_cpu_exit,
2353 .stop_cpu = intel_cpufreq_stop_cpu,
2354 .update_limits = intel_pstate_update_limits,
2355 .name = "intel_cpufreq",
2358 static struct cpufreq_driver *default_driver = &intel_pstate;
2360 static void intel_pstate_driver_cleanup(void)
2365 for_each_online_cpu(cpu) {
2366 if (all_cpu_data[cpu]) {
2367 if (intel_pstate_driver == &intel_pstate)
2368 intel_pstate_clear_update_util_hook(cpu);
2370 kfree(all_cpu_data[cpu]);
2371 all_cpu_data[cpu] = NULL;
2375 intel_pstate_driver = NULL;
2378 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2382 memset(&global, 0, sizeof(global));
2383 global.max_perf_pct = 100;
2385 intel_pstate_driver = driver;
2386 ret = cpufreq_register_driver(intel_pstate_driver);
2388 intel_pstate_driver_cleanup();
2392 global.min_perf_pct = min_perf_pct_min();
2397 static int intel_pstate_unregister_driver(void)
2402 cpufreq_unregister_driver(intel_pstate_driver);
2403 intel_pstate_driver_cleanup();
2408 static ssize_t intel_pstate_show_status(char *buf)
2410 if (!intel_pstate_driver)
2411 return sprintf(buf, "off\n");
2413 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2414 "active" : "passive");
2417 static int intel_pstate_update_status(const char *buf, size_t size)
2421 if (size == 3 && !strncmp(buf, "off", size))
2422 return intel_pstate_driver ?
2423 intel_pstate_unregister_driver() : -EINVAL;
2425 if (size == 6 && !strncmp(buf, "active", size)) {
2426 if (intel_pstate_driver) {
2427 if (intel_pstate_driver == &intel_pstate)
2430 ret = intel_pstate_unregister_driver();
2435 return intel_pstate_register_driver(&intel_pstate);
2438 if (size == 7 && !strncmp(buf, "passive", size)) {
2439 if (intel_pstate_driver) {
2440 if (intel_pstate_driver == &intel_cpufreq)
2443 ret = intel_pstate_unregister_driver();
2448 return intel_pstate_register_driver(&intel_cpufreq);
2454 static int no_load __initdata;
2455 static int no_hwp __initdata;
2456 static int hwp_only __initdata;
2457 static unsigned int force_load __initdata;
2459 static int __init intel_pstate_msrs_not_valid(void)
2461 if (!pstate_funcs.get_max() ||
2462 !pstate_funcs.get_min() ||
2463 !pstate_funcs.get_turbo())
2469 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2471 pstate_funcs.get_max = funcs->get_max;
2472 pstate_funcs.get_max_physical = funcs->get_max_physical;
2473 pstate_funcs.get_min = funcs->get_min;
2474 pstate_funcs.get_turbo = funcs->get_turbo;
2475 pstate_funcs.get_scaling = funcs->get_scaling;
2476 pstate_funcs.get_val = funcs->get_val;
2477 pstate_funcs.get_vid = funcs->get_vid;
2478 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2483 static bool __init intel_pstate_no_acpi_pss(void)
2487 for_each_possible_cpu(i) {
2489 union acpi_object *pss;
2490 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2491 struct acpi_processor *pr = per_cpu(processors, i);
2496 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2497 if (ACPI_FAILURE(status))
2500 pss = buffer.pointer;
2501 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2509 pr_debug("ACPI _PSS not found\n");
2513 static bool __init intel_pstate_no_acpi_pcch(void)
2518 status = acpi_get_handle(NULL, "\\_SB", &handle);
2519 if (ACPI_FAILURE(status))
2522 if (acpi_has_method(handle, "PCCH"))
2526 pr_debug("ACPI PCCH not found\n");
2530 static bool __init intel_pstate_has_acpi_ppc(void)
2534 for_each_possible_cpu(i) {
2535 struct acpi_processor *pr = per_cpu(processors, i);
2539 if (acpi_has_method(pr->handle, "_PPC"))
2542 pr_debug("ACPI _PPC not found\n");
2551 /* Hardware vendor-specific info that has its own power management modes */
2552 static struct acpi_platform_list plat_info[] __initdata = {
2553 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2554 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2555 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2556 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2557 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2558 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2559 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2560 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2561 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2562 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2563 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2564 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2565 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2566 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2567 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2571 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2573 const struct x86_cpu_id *id;
2577 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2579 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2580 if (misc_pwr & (1 << 8)) {
2581 pr_debug("Bit 8 in the MISC_PWR_MGMT MSR set\n");
2586 idx = acpi_match_platform_list(plat_info);
2590 switch (plat_info[idx].data) {
2592 if (!intel_pstate_no_acpi_pss())
2595 return intel_pstate_no_acpi_pcch();
2597 return intel_pstate_has_acpi_ppc() && !force_load;
2603 static void intel_pstate_request_control_from_smm(void)
2606 * It may be unsafe to request P-states control from SMM if _PPC support
2607 * has not been enabled.
2610 acpi_processor_pstate_control();
2612 #else /* CONFIG_ACPI not enabled */
2613 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2614 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2615 static inline void intel_pstate_request_control_from_smm(void) {}
2616 #endif /* CONFIG_ACPI */
2618 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2620 #define ICPU_HWP(model, hwp_mode) \
2621 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2623 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2624 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2625 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2626 ICPU_HWP(X86_MODEL_ANY, 0),
2630 static int __init intel_pstate_init(void)
2632 const struct x86_cpu_id *id;
2635 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2641 id = x86_match_cpu(hwp_support_ids);
2643 copy_cpu_funcs(&core_funcs);
2646 hwp_mode_bdw = id->driver_data;
2647 intel_pstate.attr = hwp_cpufreq_attrs;
2648 goto hwp_cpu_matched;
2651 id = x86_match_cpu(intel_pstate_cpu_ids);
2653 pr_info("CPU model not supported\n");
2657 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2660 if (intel_pstate_msrs_not_valid()) {
2661 pr_info("Invalid MSRs\n");
2667 * The Intel pstate driver will be ignored if the platform
2668 * firmware has its own power management modes.
2670 if (intel_pstate_platform_pwr_mgmt_exists()) {
2671 pr_info("P-states controlled by the platform\n");
2675 if (!hwp_active && hwp_only)
2678 pr_info("Intel P-state driver initializing\n");
2680 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2684 intel_pstate_request_control_from_smm();
2686 intel_pstate_sysfs_expose_params();
2688 mutex_lock(&intel_pstate_driver_lock);
2689 rc = intel_pstate_register_driver(default_driver);
2690 mutex_unlock(&intel_pstate_driver_lock);
2695 pr_info("HWP enabled\n");
2699 device_initcall(intel_pstate_init);
2701 static int __init intel_pstate_setup(char *str)
2706 if (!strcmp(str, "disable")) {
2708 } else if (!strcmp(str, "passive")) {
2709 pr_info("Passive mode enabled\n");
2710 default_driver = &intel_cpufreq;
2713 if (!strcmp(str, "no_hwp")) {
2714 pr_info("HWP disabled\n");
2717 if (!strcmp(str, "force"))
2719 if (!strcmp(str, "hwp_only"))
2721 if (!strcmp(str, "per_cpu_perf_limits"))
2722 per_cpu_limits = true;
2725 if (!strcmp(str, "support_acpi_ppc"))
2731 early_param("intel_pstate", intel_pstate_setup);
2733 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2734 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2735 MODULE_LICENSE("GPL");