drivers/cpu/riscv_cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu.h>
   8 #include <dm.h>
   9 #include <errno.h>
  10 #include <dm/device-internal.h>
  11 #include <dm/lists.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
  16 {
  17         const char *isa;
  18
  19         isa = dev_read_string(dev, "riscv,isa");
  20         if (size < (strlen(isa) + 1))
  21                 return -ENOSPC;
  22
  23         strcpy(buf, isa);
  24
  25         return 0;
  26 }
  27
  28 static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
  29 {
  30         const char *mmu;
  31
  32         dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
  33
  34         mmu = dev_read_string(dev, "mmu-type");
  35         if (!mmu)
  36                 info->features |= BIT(CPU_FEAT_MMU);
  37
  38         return 0;
  39 }
  40
  41 static int riscv_cpu_get_count(struct udevice *dev)
  42 {
  43         ofnode node;
  44         int num = 0;
  45
  46         ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
  47                 const char *device_type;
  48
  49                 /* skip if hart is marked as not available in the device tree */
  50                 if (!ofnode_is_available(node))
  51                         continue;
  52
  53                 device_type = ofnode_read_string(node, "device_type");
  54                 if (!device_type)
  55                         continue;
  56                 if (strcmp(device_type, "cpu") == 0)
  57                         num++;
  58         }
  59
  60         return num;
  61 }
  62
  63 static int riscv_cpu_bind(struct udevice *dev)
  64 {
  65         struct cpu_platdata *plat = dev_get_parent_platdata(dev);
  66         struct driver *drv;
  67         int ret;
  68
  69         /* save the hart id */
  70         plat->cpu_id = dev_read_addr(dev);
  71         /* first examine the property in current cpu node */
  72         ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
  73         /* if not found, then look at the parent /cpus node */
  74         if (ret)
  75                 dev_read_u32(dev->parent, "timebase-frequency",
  76                              &plat->timebase_freq);
  77
  78         /*
  79          * Bind riscv-timer driver on boot hart.
  80          *
  81          * We only instantiate one timer device which is enough for U-Boot.
  82          * Pass the "timebase-frequency" value as the driver data for the
  83          * timer device.
  84          *
  85          * Return value is not checked since it's possible that the timer
  86          * driver is not included.
  87          */
  88         if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
  89                 drv = lists_driver_lookup_name("riscv_timer");
  90                 if (!drv) {
  91                         debug("Cannot find the timer driver, not included?\n");
  92                         return 0;
  93                 }
  94
  95                 device_bind_with_driver_data(dev, drv, "riscv_timer",
  96                                              plat->timebase_freq, ofnode_null(),
  97                                              NULL);
  98         }
  99
 100         return 0;
 101 }
 102
 103 static const struct cpu_ops riscv_cpu_ops = {
 104         .get_desc       = riscv_cpu_get_desc,
 105         .get_info       = riscv_cpu_get_info,
 106         .get_count      = riscv_cpu_get_count,
 107 };
 108
 109 static const struct udevice_id riscv_cpu_ids[] = {
 110         { .compatible = "riscv" },
 111         { }
 112 };
 113
 114 U_BOOT_DRIVER(riscv_cpu) = {
 115         .name = "riscv_cpu",
 116         .id = UCLASS_CPU,
 117         .of_match = riscv_cpu_ids,
 118         .bind = riscv_cpu_bind,
 119         .ops = &riscv_cpu_ops,
 120         .flags = DM_FLAG_PRE_RELOC,
 121 };