1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/system.h>
11 #include <asm/arch/sci/sci.h>
12 #include <asm/arch/sys_proto.h>
13 #include <asm/arch-imx/cpu.h>
14 #include <asm/armv8/cpu.h>
15 #include <linux/bitops.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 struct cpu_imx_platdata {
28 const char *get_imx8_type(u32 imxtype)
32 case MXC_CPU_IMX8QXP_A0:
41 const char *get_imx8_rev(u32 rev)
55 const char *get_core_name(struct udevice *dev)
57 if (device_is_compatible(dev, "arm,cortex-a35"))
59 else if (device_is_compatible(dev, "arm,cortex-a53"))
61 else if (device_is_compatible(dev, "arm,cortex-a72"))
67 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
68 static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
70 struct udevice *thermal_dev;
73 if (!strcmp(plat->name, "A72"))
74 ret = uclass_get_device(UCLASS_THERMAL, 1, &thermal_dev);
76 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
79 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
89 static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
95 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
97 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
103 ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
104 plat->type, plat->rev, plat->name, plat->freq_mhz);
106 if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
107 temp = cpu_imx_get_temp(plat);
110 if (temp != 0xdeadbeef)
111 ret = snprintf(buf, size, " at %dC", temp);
113 ret = snprintf(buf, size, " - invalid sensor data");
116 snprintf(buf + ret, size - ret, "\n");
121 static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
123 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
125 info->cpu_freq = plat->freq_mhz * 1000;
126 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
130 static int cpu_imx_get_count(struct udevice *dev)
135 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
136 const char *device_type;
138 if (!ofnode_is_available(node))
141 device_type = ofnode_read_string(node, "device_type");
145 if (!strcmp(device_type, "cpu"))
152 static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size)
154 snprintf(buf, size, "NXP");
158 static int cpu_imx_is_current(struct udevice *dev)
160 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
162 if (plat->mpidr == (read_mpidr() & 0xffff))
168 static const struct cpu_ops cpu_imx8_ops = {
169 .get_desc = cpu_imx_get_desc,
170 .get_info = cpu_imx_get_info,
171 .get_count = cpu_imx_get_count,
172 .get_vendor = cpu_imx_get_vendor,
173 .is_current = cpu_imx_is_current,
176 static const struct udevice_id cpu_imx8_ids[] = {
177 { .compatible = "arm,cortex-a35" },
178 { .compatible = "arm,cortex-a53" },
179 { .compatible = "arm,cortex-a72" },
183 static ulong imx8_get_cpu_rate(struct udevice *dev)
188 if (device_is_compatible(dev, "arm,cortex-a35"))
190 else if (device_is_compatible(dev, "arm,cortex-a53"))
192 else if (device_is_compatible(dev, "arm,cortex-a72"))
197 ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
198 (sc_pm_clock_rate_t *)&rate);
200 printf("Could not read CPU frequency: %d\n", ret);
207 static int imx8_cpu_probe(struct udevice *dev)
209 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
212 cpurev = get_cpu_rev();
213 plat->cpurev = cpurev;
214 plat->name = get_core_name(dev);
215 plat->rev = get_imx8_rev(cpurev & 0xFFF);
216 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
217 plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
218 plat->mpidr = dev_read_addr(dev);
219 if (plat->mpidr == FDT_ADDR_T_NONE) {
220 printf("%s: Failed to get CPU reg property\n", __func__);
227 U_BOOT_DRIVER(cpu_imx8_drv) = {
230 .of_match = cpu_imx8_ids,
231 .ops = &cpu_imx8_ops,
232 .probe = imx8_cpu_probe,
233 .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
234 .flags = DM_FLAG_PRE_RELOC,