1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
8 #include <clk-uclass.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-h3-ccu.h>
13 #include <dt-bindings/reset/sun8i-h3-ccu.h>
15 static struct ccu_clk_gate h3_gates[] = {
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(23)),
22 [CLK_BUS_EHCI0] = GATE(0x060, BIT(24)),
23 [CLK_BUS_EHCI1] = GATE(0x060, BIT(25)),
24 [CLK_BUS_EHCI2] = GATE(0x060, BIT(26)),
25 [CLK_BUS_EHCI3] = GATE(0x060, BIT(27)),
26 [CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
27 [CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
28 [CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
29 [CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
31 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
32 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
33 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
34 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
36 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
37 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
39 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
40 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
41 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
42 [CLK_USB_PHY3] = GATE(0x0cc, BIT(11)),
43 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
44 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
45 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
46 [CLK_USB_OHCI3] = GATE(0x0cc, BIT(19)),
49 static struct ccu_reset h3_resets[] = {
50 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
51 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
52 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
53 [RST_USB_PHY3] = RESET(0x0cc, BIT(3)),
55 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
56 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
57 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
58 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
59 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
60 [RST_BUS_OTG] = RESET(0x2c0, BIT(23)),
61 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(24)),
62 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(25)),
63 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(26)),
64 [RST_BUS_EHCI3] = RESET(0x2c0, BIT(27)),
65 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
66 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
67 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(30)),
68 [RST_BUS_OHCI3] = RESET(0x2c0, BIT(31)),
70 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
71 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
72 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
73 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
76 static const struct ccu_desc h3_ccu_desc = {
81 static int h3_clk_bind(struct udevice *dev)
83 return sunxi_reset_bind(dev, ARRAY_SIZE(h3_resets));
86 static const struct udevice_id h3_ccu_ids[] = {
87 { .compatible = "allwinner,sun8i-h3-ccu",
88 .data = (ulong)&h3_ccu_desc },
89 { .compatible = "allwinner,sun50i-h5-ccu",
90 .data = (ulong)&h3_ccu_desc },
94 U_BOOT_DRIVER(clk_sun8i_h3) = {
95 .name = "sun8i_h3_ccu",
97 .of_match = h3_ccu_ids,
98 .priv_auto_alloc_size = sizeof(struct ccu_priv),
99 .ops = &sunxi_clk_ops,
100 .probe = sunxi_clk_probe,