drivers/clk/sunxi/clk_a80.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/arch/ccu.h>
  12 #include <dt-bindings/clock/sun9i-a80-ccu.h>
  13 #include <dt-bindings/reset/sun9i-a80-ccu.h>
  14
  15 static const struct ccu_clk_gate a80_gates[] = {
  16         [CLK_SPI0]              = GATE(0x430, BIT(31)),
  17         [CLK_SPI1]              = GATE(0x434, BIT(31)),
  18         [CLK_SPI2]              = GATE(0x438, BIT(31)),
  19         [CLK_SPI3]              = GATE(0x43c, BIT(31)),
  20
  21         [CLK_BUS_MMC]           = GATE(0x580, BIT(8)),
  22         [CLK_BUS_SPI0]          = GATE(0x580, BIT(20)),
  23         [CLK_BUS_SPI1]          = GATE(0x580, BIT(21)),
  24         [CLK_BUS_SPI2]          = GATE(0x580, BIT(22)),
  25         [CLK_BUS_SPI3]          = GATE(0x580, BIT(23)),
  26
  27         [CLK_BUS_UART0]         = GATE(0x594, BIT(16)),
  28         [CLK_BUS_UART1]         = GATE(0x594, BIT(17)),
  29         [CLK_BUS_UART2]         = GATE(0x594, BIT(18)),
  30         [CLK_BUS_UART3]         = GATE(0x594, BIT(19)),
  31         [CLK_BUS_UART4]         = GATE(0x594, BIT(20)),
  32         [CLK_BUS_UART5]         = GATE(0x594, BIT(21)),
  33 };
  34
  35 static const struct ccu_reset a80_resets[] = {
  36         [RST_BUS_MMC]           = RESET(0x5a0, BIT(8)),
  37         [RST_BUS_SPI0]          = RESET(0x5a0, BIT(20)),
  38         [RST_BUS_SPI1]          = RESET(0x5a0, BIT(21)),
  39         [RST_BUS_SPI2]          = RESET(0x5a0, BIT(22)),
  40         [RST_BUS_SPI3]          = RESET(0x5a0, BIT(23)),
  41
  42         [RST_BUS_UART0]         = RESET(0x5b4, BIT(16)),
  43         [RST_BUS_UART1]         = RESET(0x5b4, BIT(17)),
  44         [RST_BUS_UART2]         = RESET(0x5b4, BIT(18)),
  45         [RST_BUS_UART3]         = RESET(0x5b4, BIT(19)),
  46         [RST_BUS_UART4]         = RESET(0x5b4, BIT(20)),
  47         [RST_BUS_UART5]         = RESET(0x5b4, BIT(21)),
  48 };
  49
  50 static const struct ccu_clk_gate a80_mmc_gates[] = {
  51         [0]                     = GATE(0x0, BIT(16)),
  52         [1]                     = GATE(0x4, BIT(16)),
  53         [2]                     = GATE(0x8, BIT(16)),
  54         [3]                     = GATE(0xc, BIT(16)),
  55 };
  56
  57 static const struct ccu_reset a80_mmc_resets[] = {
  58         [0]                     = GATE(0x0, BIT(18)),
  59         [1]                     = GATE(0x4, BIT(18)),
  60         [2]                     = GATE(0x8, BIT(18)),
  61         [3]                     = GATE(0xc, BIT(18)),
  62 };
  63
  64 static const struct ccu_desc a80_ccu_desc = {
  65         .gates = a80_gates,
  66         .resets = a80_resets,
  67 };
  68
  69 static const struct ccu_desc a80_mmc_clk_desc = {
  70         .gates = a80_mmc_gates,
  71         .resets = a80_mmc_resets,
  72 };
  73
  74 static int a80_clk_bind(struct udevice *dev)
  75 {
  76         ulong count = ARRAY_SIZE(a80_resets);
  77
  78         if (device_is_compatible(dev, "allwinner,sun9i-a80-mmc-config-clk"))
  79                 count = ARRAY_SIZE(a80_mmc_resets);
  80
  81         return sunxi_reset_bind(dev, count);
  82 }
  83
  84 static const struct udevice_id a80_ccu_ids[] = {
  85         { .compatible = "allwinner,sun9i-a80-ccu",
  86           .data = (ulong)&a80_ccu_desc },
  87         { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
  88           .data = (ulong)&a80_mmc_clk_desc },
  89         { }
  90 };
  91
  92 U_BOOT_DRIVER(clk_sun9i_a80) = {
  93         .name           = "sun9i_a80_ccu",
  94         .id             = UCLASS_CLK,
  95         .of_match       = a80_ccu_ids,
  96         .priv_auto_alloc_size   = sizeof(struct ccu_priv),
  97         .ops            = &sunxi_clk_ops,
  98         .probe          = sunxi_clk_probe,
  99         .bind           = a80_clk_bind,
 100 };