drivers/clk/sunxi/clk_a31.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions B.V.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/arch/ccu.h>
  12 #include <dt-bindings/clock/sun6i-a31-ccu.h>
  13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
  14
  15 static struct ccu_clk_gate a31_gates[] = {
  16         [CLK_AHB1_MMC0]         = GATE(0x060, BIT(8)),
  17         [CLK_AHB1_MMC1]         = GATE(0x060, BIT(9)),
  18         [CLK_AHB1_MMC2]         = GATE(0x060, BIT(10)),
  19         [CLK_AHB1_MMC3]         = GATE(0x060, BIT(11)),
  20         [CLK_AHB1_OTG]          = GATE(0x060, BIT(24)),
  21         [CLK_AHB1_EHCI0]        = GATE(0x060, BIT(26)),
  22         [CLK_AHB1_EHCI1]        = GATE(0x060, BIT(27)),
  23         [CLK_AHB1_OHCI0]        = GATE(0x060, BIT(29)),
  24         [CLK_AHB1_OHCI1]        = GATE(0x060, BIT(30)),
  25         [CLK_AHB1_OHCI2]        = GATE(0x060, BIT(31)),
  26
  27         [CLK_APB2_UART0]        = GATE(0x06c, BIT(16)),
  28         [CLK_APB2_UART1]        = GATE(0x06c, BIT(17)),
  29         [CLK_APB2_UART2]        = GATE(0x06c, BIT(18)),
  30         [CLK_APB2_UART3]        = GATE(0x06c, BIT(19)),
  31         [CLK_APB2_UART4]        = GATE(0x06c, BIT(20)),
  32         [CLK_APB2_UART5]        = GATE(0x06c, BIT(21)),
  33
  34         [CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
  35         [CLK_USB_PHY1]          = GATE(0x0cc, BIT(9)),
  36         [CLK_USB_PHY2]          = GATE(0x0cc, BIT(10)),
  37         [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(16)),
  38         [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(17)),
  39         [CLK_USB_OHCI2]         = GATE(0x0cc, BIT(18)),
  40 };
  41
  42 static struct ccu_reset a31_resets[] = {
  43         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  44         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  45         [RST_USB_PHY2]          = RESET(0x0cc, BIT(2)),
  46
  47         [RST_AHB1_MMC0]         = RESET(0x2c0, BIT(8)),
  48         [RST_AHB1_MMC1]         = RESET(0x2c0, BIT(9)),
  49         [RST_AHB1_MMC2]         = RESET(0x2c0, BIT(10)),
  50         [RST_AHB1_MMC3]         = RESET(0x2c0, BIT(11)),
  51         [RST_AHB1_OTG]          = RESET(0x2c0, BIT(24)),
  52         [RST_AHB1_EHCI0]        = RESET(0x2c0, BIT(26)),
  53         [RST_AHB1_EHCI1]        = RESET(0x2c0, BIT(27)),
  54         [RST_AHB1_OHCI0]        = RESET(0x2c0, BIT(29)),
  55         [RST_AHB1_OHCI1]        = RESET(0x2c0, BIT(30)),
  56         [RST_AHB1_OHCI2]        = RESET(0x2c0, BIT(31)),
  57
  58         [RST_APB2_UART0]        = RESET(0x2d8, BIT(16)),
  59         [RST_APB2_UART1]        = RESET(0x2d8, BIT(17)),
  60         [RST_APB2_UART2]        = RESET(0x2d8, BIT(18)),
  61         [RST_APB2_UART3]        = RESET(0x2d8, BIT(19)),
  62         [RST_APB2_UART4]        = RESET(0x2d8, BIT(20)),
  63         [RST_APB2_UART5]        = RESET(0x2d8, BIT(21)),
  64 };
  65
  66 static const struct ccu_desc a31_ccu_desc = {
  67         .gates = a31_gates,
  68         .resets = a31_resets,
  69 };
  70
  71 static int a31_clk_bind(struct udevice *dev)
  72 {
  73         return sunxi_reset_bind(dev, ARRAY_SIZE(a31_resets));
  74 }
  75
  76 static const struct udevice_id a31_clk_ids[] = {
  77         { .compatible = "allwinner,sun6i-a31-ccu",
  78           .data = (ulong)&a31_ccu_desc },
  79         { }
  80 };
  81
  82 U_BOOT_DRIVER(clk_sun6i_a31) = {
  83         .name           = "sun6i_a31_ccu",
  84         .id             = UCLASS_CLK,
  85         .of_match       = a31_clk_ids,
  86         .priv_auto_alloc_size   = sizeof(struct ccu_priv),
  87         .ops            = &sunxi_clk_ops,
  88         .probe          = sunxi_clk_probe,
  89         .bind           = a31_clk_bind,
  90 };