1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (C) 2018 Amarula Solutions B.V.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
8 #include <clk-uclass.h>
11 #include <asm/arch/ccu.h>
12 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
13 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
15 static struct ccu_clk_gate a23_gates[] = {
16 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
17 [CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
18 [CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
20 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
21 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
22 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
23 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
24 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
26 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
27 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
28 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
29 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
30 [CLK_USB_OHCI] = GATE(0x0cc, BIT(16)),
33 static struct ccu_reset a23_resets[] = {
34 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
35 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
36 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
38 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
39 [RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
40 [RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
42 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
43 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
44 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
45 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
46 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
49 static const struct ccu_desc a23_ccu_desc = {
54 static int a23_clk_bind(struct udevice *dev)
56 return sunxi_reset_bind(dev, ARRAY_SIZE(a23_resets));
59 static const struct udevice_id a23_clk_ids[] = {
60 { .compatible = "allwinner,sun8i-a23-ccu",
61 .data = (ulong)&a23_ccu_desc },
62 { .compatible = "allwinner,sun8i-a33-ccu",
63 .data = (ulong)&a23_ccu_desc },
67 U_BOOT_DRIVER(clk_sun8i_a23) = {
68 .name = "sun8i_a23_ccu",
70 .of_match = a23_clk_ids,
71 .priv_auto_alloc_size = sizeof(struct ccu_priv),
72 .ops = &sunxi_clk_ops,
73 .probe = sunxi_clk_probe,