drivers/clk/sunxi/clk_a10.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2018 Amarula Solutions.
   4  * Author: Jagan Teki <jagan@amarulasolutions.com>
   5  */
   6
   7 #include <common.h>
   8 #include <clk-uclass.h>
   9 #include <dm.h>
  10 #include <errno.h>
  11 #include <asm/arch/ccu.h>
  12 #include <dt-bindings/clock/sun4i-a10-ccu.h>
  13 #include <dt-bindings/reset/sun4i-a10-ccu.h>
  14
  15 static struct ccu_clk_gate a10_gates[] = {
  16         [CLK_AHB_OTG]           = GATE(0x060, BIT(0)),
  17         [CLK_AHB_EHCI0]         = GATE(0x060, BIT(1)),
  18         [CLK_AHB_OHCI0]         = GATE(0x060, BIT(2)),
  19         [CLK_AHB_EHCI1]         = GATE(0x060, BIT(3)),
  20         [CLK_AHB_OHCI1]         = GATE(0x060, BIT(4)),
  21         [CLK_AHB_MMC0]          = GATE(0x060, BIT(8)),
  22         [CLK_AHB_MMC1]          = GATE(0x060, BIT(9)),
  23         [CLK_AHB_MMC2]          = GATE(0x060, BIT(10)),
  24         [CLK_AHB_MMC3]          = GATE(0x060, BIT(11)),
  25         [CLK_AHB_EMAC]          = GATE(0x060, BIT(17)),
  26         [CLK_AHB_SPI0]          = GATE(0x060, BIT(20)),
  27         [CLK_AHB_SPI1]          = GATE(0x060, BIT(21)),
  28         [CLK_AHB_SPI2]          = GATE(0x060, BIT(22)),
  29         [CLK_AHB_SPI3]          = GATE(0x060, BIT(23)),
  30
  31         [CLK_APB1_UART0]        = GATE(0x06c, BIT(16)),
  32         [CLK_APB1_UART1]        = GATE(0x06c, BIT(17)),
  33         [CLK_APB1_UART2]        = GATE(0x06c, BIT(18)),
  34         [CLK_APB1_UART3]        = GATE(0x06c, BIT(19)),
  35         [CLK_APB1_UART4]        = GATE(0x06c, BIT(20)),
  36         [CLK_APB1_UART5]        = GATE(0x06c, BIT(21)),
  37         [CLK_APB1_UART6]        = GATE(0x06c, BIT(22)),
  38         [CLK_APB1_UART7]        = GATE(0x06c, BIT(23)),
  39
  40         [CLK_SPI0]              = GATE(0x0a0, BIT(31)),
  41         [CLK_SPI1]              = GATE(0x0a4, BIT(31)),
  42         [CLK_SPI2]              = GATE(0x0a8, BIT(31)),
  43
  44         [CLK_USB_OHCI0]         = GATE(0x0cc, BIT(6)),
  45         [CLK_USB_OHCI1]         = GATE(0x0cc, BIT(7)),
  46         [CLK_USB_PHY]           = GATE(0x0cc, BIT(8)),
  47
  48         [CLK_SPI3]              = GATE(0x0d4, BIT(31)),
  49 };
  50
  51 static struct ccu_reset a10_resets[] = {
  52         [RST_USB_PHY0]          = RESET(0x0cc, BIT(0)),
  53         [RST_USB_PHY1]          = RESET(0x0cc, BIT(1)),
  54         [RST_USB_PHY2]          = RESET(0x0cc, BIT(2)),
  55 };
  56
  57 static const struct ccu_desc a10_ccu_desc = {
  58         .gates = a10_gates,
  59         .resets = a10_resets,
  60 };
  61
  62 static int a10_clk_bind(struct udevice *dev)
  63 {
  64         return sunxi_reset_bind(dev, ARRAY_SIZE(a10_resets));
  65 }
  66
  67 static const struct udevice_id a10_ccu_ids[] = {
  68         { .compatible = "allwinner,sun4i-a10-ccu",
  69           .data = (ulong)&a10_ccu_desc },
  70         { .compatible = "allwinner,sun7i-a20-ccu",
  71           .data = (ulong)&a10_ccu_desc },
  72         { }
  73 };
  74
  75 U_BOOT_DRIVER(clk_sun4i_a10) = {
  76         .name           = "sun4i_a10_ccu",
  77         .id             = UCLASS_CLK,
  78         .of_match       = a10_ccu_ids,
  79         .priv_auto_alloc_size   = sizeof(struct ccu_priv),
  80         .ops            = &sunxi_clk_ops,
  81         .probe          = sunxi_clk_probe,
  82         .bind           = a10_clk_bind,
  83 };